coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb
by Timothy Pearson 19 Aug '16

19 Aug '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16268 -gerrit commit 50c579866313439da4739d3a9d656b4fa56c5b17 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Fri Aug 19 17:26:51 2016 -0500 mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb Change-Id: I49925040d951dffb9c11425334674d8d498821f0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/asus/kcma-d8/devicetree.cb | 4 ++-- src/mainboard/asus/kgpe-d16/devicetree.cb | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index 51ff394..f8a2d83 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -49,7 +49,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic # DIMM n-0-0-0 device i2c 50 on end end @@ -173,7 +173,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex chip superio/winbond/w83667hg-a # Super I/O device pnp 2e.0 off end # FDC; Not available on the KCMA-D8 device pnp 2e.1 off end # LPT1; Not available on the KCMA-D8 - device pnp 2e.2 on # COM1 + device pnp 2e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 2b8230a..ff2023d 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -56,7 +56,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic # DIMM n-0-0-0 device i2c 50 on end end @@ -180,7 +180,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex chip superio/winbond/w83667hg-a # Super I/O device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 - device pnp 2e.2 on # COM1 + device pnp 2e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end

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Patch set updated for coreboot: intel/i82801gx 82801ix: Remove OpRegion of SMBus host
by Kyösti Mälkki 19 Aug '16

19 Aug '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16266 -gerrit commit f8d4d79a3f493176ee6671ba231a337bbf8bc65a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 19 23:41:32 2016 +0300 intel/i82801gx 82801ix: Remove OpRegion of SMBus host Defining this OpRegion for SMBus controller prevents linux kernel driver i2c-i801 from registering SMBus under sysfs, with following error in dmesg: ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI) Solution taken from intel/bd82x6x. Worth noting we do not define ENABLE_SMBUS_METHODS anywhere currently. Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801gx/acpi/smbus.asl | 2 +- src/southbridge/intel/i82801ix/acpi/smbus.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/acpi/smbus.asl b/src/southbridge/intel/i82801gx/acpi/smbus.asl index 3c4337f..3b314e4 100644 --- a/src/southbridge/intel/i82801gx/acpi/smbus.asl +++ b/src/southbridge/intel/i82801gx/acpi/smbus.asl @@ -20,6 +20,7 @@ Device (SBUS) { Name (_ADR, 0x001f0003) +#ifdef ENABLE_SMBUS_METHODS OperationRegion (SMBP, PCI_Config, 0x00, 0x100) Field(SMBP, DWordAcc, NoLock, Preserve) { @@ -53,7 +54,6 @@ Device (SBUS) NDLH, 8, // Notify Data High Byte } -#ifdef ENABLE_SMBUS_METHODS // Kill all SMBus communication Method (KILL, 0, Serialized) { diff --git a/src/southbridge/intel/i82801ix/acpi/smbus.asl b/src/southbridge/intel/i82801ix/acpi/smbus.asl index 3c4337f..3b314e4 100644 --- a/src/southbridge/intel/i82801ix/acpi/smbus.asl +++ b/src/southbridge/intel/i82801ix/acpi/smbus.asl @@ -20,6 +20,7 @@ Device (SBUS) { Name (_ADR, 0x001f0003) +#ifdef ENABLE_SMBUS_METHODS OperationRegion (SMBP, PCI_Config, 0x00, 0x100) Field(SMBP, DWordAcc, NoLock, Preserve) { @@ -53,7 +54,6 @@ Device (SBUS) NDLH, 8, // Notify Data High Byte } -#ifdef ENABLE_SMBUS_METHODS // Kill all SMBus communication Method (KILL, 0, Serialized) {

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New patch to review for coreboot: intel/i82801gx 82801ix: Remove OpRegion of SMBus host
by Kyösti Mälkki 19 Aug '16

19 Aug '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16266 -gerrit commit 2b488beef5db6faaad9b12afc26be23c5690cc37 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 19 23:41:32 2016 +0300 intel/i82801gx 82801ix: Remove OpRegion of SMBus host Defining this OpRegion for SMBus controller prevents linux kernel driver i2c-i801 from registering SMBus under sysfs, with following error in dmesg: ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI) Solution taken from intel/bd82x6x. Worth noting we do not define ENABLE_SMBUS_METHODS anywhere currently. Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801gx/acpi/smbus.asl | 2 +- src/southbridge/intel/i82801ix/acpi/smbus.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/acpi/smbus.asl b/src/southbridge/intel/i82801gx/acpi/smbus.asl index 3c4337f..cad9cbc 100644 --- a/src/southbridge/intel/i82801gx/acpi/smbus.asl +++ b/src/southbridge/intel/i82801gx/acpi/smbus.asl @@ -20,6 +20,7 @@ Device (SBUS) { Name (_ADR, 0x001f0003) +ifdef ENABLE_SMBUS_METHODS OperationRegion (SMBP, PCI_Config, 0x00, 0x100) Field(SMBP, DWordAcc, NoLock, Preserve) { @@ -53,7 +54,6 @@ Device (SBUS) NDLH, 8, // Notify Data High Byte } -#ifdef ENABLE_SMBUS_METHODS // Kill all SMBus communication Method (KILL, 0, Serialized) { diff --git a/src/southbridge/intel/i82801ix/acpi/smbus.asl b/src/southbridge/intel/i82801ix/acpi/smbus.asl index 3c4337f..3b314e4 100644 --- a/src/southbridge/intel/i82801ix/acpi/smbus.asl +++ b/src/southbridge/intel/i82801ix/acpi/smbus.asl @@ -20,6 +20,7 @@ Device (SBUS) { Name (_ADR, 0x001f0003) +#ifdef ENABLE_SMBUS_METHODS OperationRegion (SMBP, PCI_Config, 0x00, 0x100) Field(SMBP, DWordAcc, NoLock, Preserve) { @@ -53,7 +54,6 @@ Device (SBUS) NDLH, 8, // Notify Data High Byte } -#ifdef ENABLE_SMBUS_METHODS // Kill all SMBus communication Method (KILL, 0, Serialized) {

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New patch to review for coreboot: google/gru: Add USB 2.0 PHY tuning for Kevin
by Martin Roth 19 Aug '16

19 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16265 -gerrit commit d19a91c86aaeb3affb0ced1242245962aac2624c Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 17:58:05 2016 -0700 google/gru: Add USB 2.0 PHY tuning for Kevin This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/370900 Original-Reviewed-by: Guenter Roeck <groeck(a)chromium.org> Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 13 +++++++++++++ src/soc/rockchip/rk3399/include/soc/grf.h | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 8a6cda2..8d9311a 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -158,6 +158,19 @@ static void configure_display(void) static void setup_usb(void) { + /* + * A few magic PHY tuning values that improve eye diagram amplitude + * and make it extra sure we get reliable communication in firmware. + */ + + /* Set max ODT compensation voltage and current tuning reference. */ + write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3); + write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3); + + /* Set max pre-emphasis level, only on Kevin PHY0. */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) + write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7); + setup_usb_otg0(); setup_usb_otg1(); } diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index d76b827..c1fd690 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -73,7 +73,7 @@ struct rk3399_grf_regs { u32 reserved11[3]; u32 usbphy0_ctrl[26]; u32 reserved12[6]; - u32 usbphy1[26]; + u32 usbphy1_ctrl[26]; u32 reserved13[0x72f]; u32 soc_con9; u32 reserved14[0x0a];

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Patch merged into coreboot/master: rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevin
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit ba2b63a20abf3e5955cce43128911f90609beac1 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Jul 25 10:06:09 2016 +0800 rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevin We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16241 for details. -gerrit

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Patch merged into coreboot/master: vboot/vbnv_flash: make I/O connection agnostic
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit b18a6665df2633193b7863e3dd9eca230536405b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:48:58 2016 -0500 vboot/vbnv_flash: make I/O connection agnostic There's no need to be SPI specific w.r.t. how the flash is connected. Therefore, use the RW boot device to write the contents of VBNV. The erasable check was dropped because that information isn't available. All regions should be aligned accordingly on the platform for the underlying hardware implementation. And once the VBNV region fills the erase will fail. BUG=chrome-os-partner:56151 Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16206 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16206 for details. -gerrit

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Patch merged into coreboot/master: vboot: provide RW region device support
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit 5bb9e93ea68db0ffe156f2df2d69397f21c57095 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:46:07 2016 -0500 vboot: provide RW region device support Explicitly provide a RW view of an vboot FMAP region. This is required for platforms which have separate implementations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: If8bf2e1c7ca9bff536fc5c578fe0cf92ccbd2ebc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16205 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16205 for details. -gerrit

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Patch merged into coreboot/master: drivers/elog: use region_device for NV storage
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit d10f9d57c2be360fcecb0f3dece4886ced781e54 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 10 11:37:14 2016 -0500 drivers/elog: use region_device for NV storage Instead of assuming SPI backing use a region_device to abstract away the underlying storage mechanism. BUG=chrome-os-partner:55932 Change-Id: I6b0f5a7e9bea8833fb1bca87e02abefab63acec3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16204 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16204 for details. -gerrit

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Patch merged into coreboot/master: lib/fmap: provide RW region device support
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit bccaab86582957483b0b7e50ead308ed1bff815d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:42:04 2016 -0500 lib/fmap: provide RW region device support Explicitly provide a RW view of an FMAP region. This is required for platforms which have separate implementations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: Ibafa3dc534f53a3d90487f3190c0f8a2e82858c2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16203 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16203 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit e4cc8cd00b3b39eecac604cc402b8111f8fd5657 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 23:55:39 2016 -0500 soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16202 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16202 for details. -gerrit

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coreboot-gerrit August 2016