coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stages
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit 7b2c781dbdb226af1db10547500be91f45ee8cc0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 23:51:42 2016 -0500 soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stages If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16201 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16201 for details. -gerrit

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Patch merged into coreboot/master: drivers/spi: provide optional implementation of boot_device_rw()
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit 6f1155916a8b2f5409d0992963a1c16178794a48 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 18:24:54 2016 -0500 drivers/spi: provide optional implementation of boot_device_rw() On many x86 platforms the boot device is SPI which is memory mapped. However, in order to write to the boot device one needs to use the SPI api. Therefore, provide a common implementation of boot_device_rw() which has no mmap() functionality. It only reads, writes, and erases. This will be used in the existing infrastructure but in a SPI agnostic way. Two options are added: 1. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP 2. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY The former is auto-selected when COMMON_CBFS_SPI_WRAPPER is not selected. The latter can be used to include the implementation in the early stages such as bootblock, verstage, and romstage. BUG=chrome-os-partner:56151 Change-Id: I2aa75f88409309e3f9b9bd79b52d27c0061139c8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16200 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16200 for details. -gerrit

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Patch merged into coreboot/master: drivers/spi: include SPI flash modules for all stages
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit 5180dd2c4b6fa7756c43485a8a0f2ca5015cc774 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 17:04:42 2016 -0500 drivers/spi: include SPI flash modules for all stages It shouldn't matter if COMMON_CBFS_SPI_WRAPPER is selected to include the SPI flash support in all stages. Therefore, include the SPI flash support files in all the stages. While there include the same set of files for all stages. They were out of sync for some reason. BUG=chrome-os-partner:56151 Change-Id: I933335104203315cbbcf965185a7c176974e6356 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16198 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16198 for details. -gerrit

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Patch merged into coreboot/master: drivers/spi: ensure SPI flash is boot device for coreboot tables
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit c0a823c737d984cd212b2018a71b37fbf9146111 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 14:51:38 2016 -0500 drivers/spi: ensure SPI flash is boot device for coreboot tables The spi_flash_probe() routine was setting a global varible unconditonally regardless if the probe was for the boot device or even if the boot devcie was flash. Moreover, there's no need to report the SPI information if the boot device isn't even SPI. Lastly, it's possible that the boot device is a SPI flash, but the platform may never probe (selecting SPI_FLASH) for the actual device connected. In that situation don't fill anything in as no correct information is known. BUG=chrome-os-partner:56151 Change-Id: Ib0eba601df4d77bede313c358c92b0536355bbd0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16197 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16197 for details. -gerrit

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Patch merged into coreboot/master: util/lint: Add a tool to verify a single newline at the end of files
by gerrit＠coreboot.org 19 Aug '16

19 Aug '16

the following patch was just integrated into master: commit 2e03fbced7551211b801f7d01d5c0b0e7dcad323 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jul 28 16:20:59 2016 -0600 util/lint: Add a tool to verify a single newline at the end of files This takes way too long to run - currently about 30 seconds to look at the entire coreboot tree. Change-Id: I403934014b422528715ea95ff652babe5e18c88b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/15976 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/15976 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: Do not halt in poweroff if in SMM
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16259 -gerrit commit 23e01a6d917136451058f6770caa0830db585643 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:42:36 2016 -0700 intel/skylake: Do not halt in poweroff if in SMM Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 Change-Id: I3addc1ea065346fbc5dbec9d1ad49bbd0ae05696 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/skylake/pmutil.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 807579d..31de242 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <halt.h> +#include <rules.h> #include <stdlib.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -435,5 +436,12 @@ uint16_t smbus_tco_regs(void) void poweroff(void) { enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - halt(); + + /* + * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM + * to transition to S5 state. If halt is called in SMM, then it prevents + * the SMI handler from being triggered and system never enters S5. + */ + if (!ENV_SMM) + halt(); }

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Patch set updated for coreboot: google/chromeec: Ensure data is ready before reading it
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16258 -gerrit commit 72d21baf438c1d931c66ab4a7a2f7a658acd2425 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:39:14 2016 -0700 google/chromeec: Ensure data is ready before reading it Before reading the data provided by EC to the host, ensure that data ready flag is set. Otherwise, it could result in reading stale/incorrect data from the data buffer. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is read correctly by host on reef. Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/ec/google/chromeec/ec_lpc.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 06b506b..51a6e53 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -96,7 +96,7 @@ static inline u8 write_byte(u8 val, u16 port) return byte; } -static int google_chromeec_wait_ready(u16 port) +static int google_chromeec_status_check(u16 port, u8 mask, u8 cond) { u8 ec_status = read_byte(port); u32 time_count = 0; @@ -108,8 +108,7 @@ static int google_chromeec_wait_ready(u16 port) */ #define MAX_EC_TIMEOUT_US 1000000 - while (ec_status & - (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) { + while ((ec_status & mask) != cond) { udelay(1); if (time_count++ == MAX_EC_TIMEOUT_US) return -1; @@ -118,6 +117,13 @@ static int google_chromeec_wait_ready(u16 port) return 0; } +static int google_chromeec_wait_ready(u16 port) +{ + return google_chromeec_status_check(port, + EC_LPC_CMDR_PENDING | + EC_LPC_CMDR_BUSY, 0); +} + #if CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP /* Read memmap data through ACPI port 66/62 */ static int read_memmap(u8 *data, u8 offset) @@ -481,6 +487,12 @@ struct chip_operations ec_google_chromeec_ops = { #endif /* __SMM__ */ +static int google_chromeec_data_ready(u16 port) +{ + return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, + EC_LPC_CMDR_DATA); +} + u8 google_chromeec_get_event(void) { if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { @@ -496,6 +508,11 @@ u8 google_chromeec_get_event(void) return 0; } + if (google_chromeec_data_ready(EC_LPC_ADDR_ACPI_CMD)) { + printk(BIOS_ERR, "Timeout waiting for data ready!\n"); + return 0; + } + /* Event (or 0 if none) is returned directly in the data byte */ return read_byte(EC_LPC_ADDR_ACPI_DATA); }

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Patch set updated for coreboot: intel/apollolake: Do not halt in poweroff if in SMM
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16257 -gerrit commit f8671f0398ee1670e606108fdb581ce6242819c0 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:31:50 2016 -0700 intel/apollolake: Do not halt in poweroff if in SMM Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified lidclose behavior on reef. Change-Id: If116c8f4e867543abdc2ff235457c167b5073767 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/pmutil.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index dabc268..aaa4018 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -443,5 +443,12 @@ void vboot_platform_prepare_reboot(void) void poweroff(void) { enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - halt(); + + /* + * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM + * to transition to S5 state. If halt is called in SMM, then it prevents + * the SMI handler from being triggered and system never enters S5. + */ + if (!ENV_SMM) + halt(); }

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Patch set updated for coreboot: intel/apollolake: Fix typo in gpi_status_get
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16256 -gerrit commit 37444669a007c39514d83df64de25918feb2f6c9 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:29:27 2016 -0700 intel/apollolake: Fix typo in gpi_status_get sts_index is calculated incorrectly because of wrong use of parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef and lidclose event was missed. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is seen and handled by SMM in coreboot on reef. Change-Id: I56be4aaf30e2d6712fc597b941206ca59ffaa915 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 8e4ff3e..a2ac091 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -328,7 +328,7 @@ int gpi_status_get(const struct gpi_status *sts, gpio_t gpi) if (comm == NULL) return 0; - sts_index = comm->gpi_offset + (gpi - (comm->first_pad) / + sts_index = comm->gpi_offset + ((gpi - comm->first_pad) / GPIO_MAX_NUM_PER_GROUP); return !!(sts->grp[sts_index] & (1 << (gpi % GPIO_MAX_NUM_PER_GROUP)));

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New patch to review for coreboot: intel/apollolake: Fix typo in gpi_status_get
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16264 -gerrit commit 147321851a5496807ddb1fdaeda85b503069fb44 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:29:27 2016 -0700 intel/apollolake: Fix typo in gpi_status_get sts_index is calculated incorrectly because of wrong use of parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef and lidclose event was missed. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is seen and handled by SMM in coreboot on reef. Change-Id: Ie0869f89b10b14bec41ce84170ad964a0a8820f6 Change-I: I56be4aaf30e2d6712fc597b941206ca59ffaa915 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 8e4ff3e..a2ac091 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -328,7 +328,7 @@ int gpi_status_get(const struct gpi_status *sts, gpio_t gpi) if (comm == NULL) return 0; - sts_index = comm->gpi_offset + (gpi - (comm->first_pad) / + sts_index = comm->gpi_offset + ((gpi - comm->first_pad) / GPIO_MAX_NUM_PER_GROUP); return !!(sts->grp[sts_index] & (1 << (gpi % GPIO_MAX_NUM_PER_GROUP)));

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coreboot-gerrit August 2016