coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

1 participants
1551 discussions

Patch merged into coreboot/master: mainboard: Clean up boot_option/reboot_bits in cmos.layout
by gerrit＠coreboot.org 16 Aug '16

16 Aug '16

the following patch was just integrated into master: commit d23ee5de2233d2f200dc15bf4a7669599c2b2014 Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Aug 11 22:45:55 2016 +0200 mainboard: Clean up boot_option/reboot_bits in cmos.layout Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-by: York Yang <york.yang(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16157 for details. -gerrit

1 0

New patch to review for coreboot: intel/amenia: Update EMMC DLL settings
by Bora Guvendik 16 Aug '16

16 Aug '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16237 -gerrit commit 637398fb48af5c4f132c119698b29fbc64411276 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Tue Aug 16 14:43:16 2016 -0700 intel/amenia: Update EMMC DLL settings Update EMMC DLL setting for amenia board, after that system can boot up with EMMC successfully. BUG=chrome-os-partner:51844 TEST=Boot up with EMMC Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 4b620a0..80fc29c 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -12,6 +12,26 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # EMMC TX DATA Delay 2# + # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 + # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 + # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 + # 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode + register "emmc_tx_data_cntl2" = "0x1c1c1c00" + + # EMMC RX CMD/DATA Delay 1# + # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 + # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 + # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 + # 0x00[6:0] stands for 0 delay for SDR12/Compatibility + register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00" + + # EMMC RX CMD/DATA Delay 2# + # 0x01[17:16] stands for Rx Clock before Output Buffer + # 0x00[14:8] stands for 0 delay for Auto Tuning Mode + # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200 + register "emmc_rx_cmd_data_cntl2" = "0x1001c" + # LPSS S0ix Enable register "lpss_s0ix_enable" = "1"

1 0

Patch set updated for coreboot: soc/intel/skylake: Correct Cache as ram size
by Rizwan Qureshi 16 Aug '16

16 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16236 -gerrit commit 2d5fe75b8d9d45dddb049e2ec5b1d38cfcf16435 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sun Aug 14 15:48:33 2016 +0530 soc/intel/skylake: Correct Cache as ram size DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000 is used to calculate the _car_region_end in car.ld. If the FSP CAR requirement is greater than or even close to DCACHE_RAM_SIZE then, the CAR region for FSP will be determined to be below the overall CAR region boundary i.e, out of CAR memory range. This is working with FSP 1.1 because we provide the FspCarSize and FspCarBase explicitly in a UPD. Hence, FSP is still able to use the upper region of CAR memory for its purpose. However, it will be a problem in case of FSP2.0 where FSP usable CAR is calculated using _car_region_end. So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB) Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 6 +----- src/soc/intel/skylake/bootblock/cache_as_ram.S | 4 ++-- src/soc/intel/skylake/romstage/romstage.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8c8b1b7..3df4bd7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,7 +84,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x10000 + default 0x40000 help The size of the cache-as-ram region required during bootblock and/or romstage. @@ -199,10 +199,6 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. -config DCACHE_RAM_SIZE_TOTAL - hex - default 0x40000 - config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 89a3cf0..3f8f0f0 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -116,7 +116,7 @@ clear_var_mtrr: /* Configure the MTRR mask for the size region */ mov $MTRR_PHYS_MASK(0), %ecx - mov $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax /* size mask */ + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ dec %eax not %eax or $MTRR_PHYS_MASK_VALID, %eax @@ -216,7 +216,7 @@ find_llc_subleaf: wrmsr movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx + movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx movl $CACHE_INIT_VALUE, %eax cld diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fda6087..0ec2f99 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -93,7 +93,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->DdrFreqLimit = config->DdrFreqLimit; if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } }

1 0

New patch to review for coreboot: soc/intel/skylake: Cache as ram size correction
by Rizwan Qureshi 16 Aug '16

16 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16236 -gerrit commit 3717b9d5852ba35827137404b715b1b85391d660 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sun Aug 14 15:48:33 2016 +0530 soc/intel/skylake: Cache as ram size correction DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000 is used to calculate the _car_region_end in car.ld. If the FSP CAR requirement is greater than or even close to DCACHE_RAM_SIZE then, the CAR region for FSP will be determined to be below the overall CAR region boundary i.e, out of CAR memory range. This is working with FSP 1.1 because we provide the FspCarSize and FspCarBase explicitly in a UPD. Hence, FSP is still able to use the upper region of CAR memory for its purpose. However, it will be a problem in case of FSP2.0 where FSP usable CAR is calculated using _car_region_end. So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB) Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 6 +----- src/soc/intel/skylake/bootblock/cache_as_ram.S | 4 ++-- src/soc/intel/skylake/romstage/romstage.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8c8b1b7..3df4bd7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,7 +84,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x10000 + default 0x40000 help The size of the cache-as-ram region required during bootblock and/or romstage. @@ -199,10 +199,6 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. -config DCACHE_RAM_SIZE_TOTAL - hex - default 0x40000 - config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 89a3cf0..3f8f0f0 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -116,7 +116,7 @@ clear_var_mtrr: /* Configure the MTRR mask for the size region */ mov $MTRR_PHYS_MASK(0), %ecx - mov $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax /* size mask */ + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ dec %eax not %eax or $MTRR_PHYS_MASK_VALID, %eax @@ -216,7 +216,7 @@ find_llc_subleaf: wrmsr movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx + movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx movl $CACHE_INIT_VALUE, %eax cld diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fda6087..0ec2f99 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -93,7 +93,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->DdrFreqLimit = config->DdrFreqLimit; if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } }

1 0

Patch merged into coreboot/master: console: Change CONFIG_CHROMEOS requirement from do_printk_va_list()
by gerrit＠coreboot.org 16 Aug '16

16 Aug '16

the following patch was just integrated into master: commit 4f79e6618519fa1aa8e8afaac57fc7dbfeeb4484 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 16:14:15 2016 -0700 console: Change CONFIG_CHROMEOS requirement from do_printk_va_list() CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS. Change the code guard for do_printk_va_list() accordingly, since it's used by vboot (not Chrome OS) code. Change-Id: I44e868d2fd8e1368eeda2f10a35d0a2bd7259759 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16230 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/16230 for details. -gerrit

1 0

Patch merged into coreboot/master: vboot: Move TPM-related Kconfig selects from CHROMEOS to VBOOT
by gerrit＠coreboot.org 16 Aug '16

16 Aug '16

the following patch was just integrated into master: commit 4157bd8d61ad709a29072cb4505b3cc7463e515b Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 16:10:27 2016 -0700 vboot: Move TPM-related Kconfig selects from CHROMEOS to VBOOT CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS. However, the latter still has some 'select' clauses to ensure that required TPM libraries are built. The TPM is an essential part of vboot, and without these libraries the vboot code cannot compile... therefore, they should be moved under CONFIG_VBOOT. Change-Id: I0145558e5127c65c6a82d62f25b5a39e24cb8726 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16229 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16229 for details. -gerrit

1 0

New patch to review for coreboot: google/gru: Add new PWM regulator duty numbers for revision 6
by Martin Roth 16 Aug '16

16 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16235 -gerrit commit c3c0fa9c8e242bc2b01a144e1cf3ff3bb54f6c27 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 11 16:37:57 2016 -0700 google/gru: Add new PWM regulator duty numbers for revision 6 We're changing the PWM regulator bounds on Kevin from rev6 onwards, so we'll need to use different duty cycle values for them. We really want a proper PWM regulator driver that can calculate these values automatically from voltages, but until we have that this patch just hardcodes the new numbers in. (Yes, this is a patch for the mainboard/google/gru board family that only touches a file from the rockchip/rk3399 SoC. That too is something that'll be fixed up in a later CL.) BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted Kevin rev4 (for whatever that's worth...). Change-Id: Ibb6ab5c6517d83ffb5e32cb17d0de33e8ec10293 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4cb2a939295e2b6443c5dbd3374982224322304b Original-Change-Id: I8757cc54f2478d20bb948a1a0a7398b0404a7b1f Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/368410 Original-Commit-Ready: Dan Shi <dshi(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/romstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/soc/rockchip/rk3399/romstage.c b/src/soc/rockchip/rk3399/romstage.c index 8adaa7c..ccf42b9 100644 --- a/src/soc/rockchip/rk3399/romstage.c +++ b/src/soc/rockchip/rk3399/romstage.c @@ -79,12 +79,24 @@ static void init_dvs_outputs(void) */ duty_ns = 2860; /* 0.9v */ + /* TODO: Clean all this up, implement proper pwm_regulator driver. */ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { id = board_id(); if (id <= 2) duty_ns = 1906; /* 1.1v */ else if (id == 3) duty_ns = 2621; /* 0.95v */ + else if (id >= 6) { + /* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */ + pwm_init(0, 3337, 2501); + /* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */ + pwm_init(1, 3337, 2638); + /* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */ + pwm_init(2, 3337, 2647); + /* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */ + pwm_init(3, 3337, 1338); + return; + } } for (i = 0; i < 4; i++)

1 0

New patch to review for coreboot: bd82x6x/early_pch: iobp: use known names instead of magic constants
by Felix Held 16 Aug '16

16 Aug '16

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16214 -gerrit commit d116af8aa8d03f1b8131810a8b91c84bc2dda320 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun Aug 14 13:25:39 2016 +0200 bd82x6x/early_pch: iobp: use known names instead of magic constants Change-Id: I91a828ed076ca10733b47db876fabf5adaa63638 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/southbridge/intel/bd82x6x/early_pch.c | 155 +++++++++++++++--------------- 1 file changed, 78 insertions(+), 77 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 21a996d..dff8bf8 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -31,39 +31,40 @@ #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) static void -wait_2338 (void) +wait_iobp(void) { - while (read8 (DEFAULT_RCBA + 0x2338) & 1); + while (read8(DEFAULT_RCBA + IOBPS) & 1) + ; //implement timeout? } static u32 -read_2338 (u32 edx) +read_iobp(u32 edx) { u32 ret; - write32 (DEFAULT_RCBA + 0x2330, edx); - write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338) + write32(DEFAULT_RCBA + IOBPIRI, edx); + write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) & 0x1ff) | 0x600); - wait_2338 (); - ret = read32 (DEFAULT_RCBA + 0x2334); - wait_2338 (); - read8 (DEFAULT_RCBA + 0x2338); + wait_iobp(); + ret = read32(DEFAULT_RCBA + IOBPD); + wait_iobp(); + read8(DEFAULT_RCBA + IOBPS); //call wait_iobp() instead here? return ret; } static void -write_2338 (u32 edx, u32 val) +write_iobp(u32 edx, u32 val) { - read_2338 (edx); - write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338) + read_iobp(edx); + write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) & 0x1ff) | 0x600); - wait_2338 (); + wait_iobp(); - write32 (DEFAULT_RCBA + 0x2334, val); - wait_2338 (); - write16 (DEFAULT_RCBA + 0x2338, - (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600); - read8 (DEFAULT_RCBA + 0x2338); + write32(DEFAULT_RCBA + IOBPD, val); + wait_iobp(); + write16(DEFAULT_RCBA + IOBPS, + (read16(DEFAULT_RCBA + IOBPS) & 0x1ff) | 0x600); + read8(DEFAULT_RCBA + IOBPS); //call wait_iobp() instead here? } @@ -304,67 +305,67 @@ early_pch_init_native (void) read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - write_2338 (0xea007f62, 0x00590133); - write_2338 (0xec007f62, 0x00590133); - write_2338 (0xec007f64, 0x59555588); - write_2338 (0xea0040b9, 0x0001051c); - write_2338 (0xeb0040a1, 0x800084ff); - write_2338 (0xec0040a1, 0x800084ff); - write_2338 (0xea004001, 0x00008400); - write_2338 (0xeb004002, 0x40201758); - write_2338 (0xec004002, 0x40201758); - write_2338 (0xea004002, 0x00601758); - write_2338 (0xea0040a1, 0x810084ff); - write_2338 (0xeb0040b1, 0x0001c598); - write_2338 (0xec0040b1, 0x0001c598); - write_2338 (0xeb0040b6, 0x0001c598); - write_2338 (0xea0000a9, 0x80ff969f); - write_2338 (0xea0001a9, 0x80ff969f); - write_2338 (0xeb0040b2, 0x0001c396); - write_2338 (0xeb0040b3, 0x0001c396); - write_2338 (0xec0040b2, 0x0001c396); - write_2338 (0xea0001a9, 0x80ff94ff); - write_2338 (0xea000151, 0x0088037f); - write_2338 (0xea0000a9, 0x80ff94ff); - write_2338 (0xea000051, 0x0088037f); + write_iobp(0xea007f62, 0x00590133); + write_iobp(0xec007f62, 0x00590133); + write_iobp(0xec007f64, 0x59555588); + write_iobp(0xea0040b9, 0x0001051c); + write_iobp(0xeb0040a1, 0x800084ff); + write_iobp(0xec0040a1, 0x800084ff); + write_iobp(0xea004001, 0x00008400); + write_iobp(0xeb004002, 0x40201758); + write_iobp(0xec004002, 0x40201758); + write_iobp(0xea004002, 0x00601758); + write_iobp(0xea0040a1, 0x810084ff); + write_iobp(0xeb0040b1, 0x0001c598); + write_iobp(0xec0040b1, 0x0001c598); + write_iobp(0xeb0040b6, 0x0001c598); + write_iobp(0xea0000a9, 0x80ff969f); + write_iobp(0xea0001a9, 0x80ff969f); + write_iobp(0xeb0040b2, 0x0001c396); + write_iobp(0xeb0040b3, 0x0001c396); + write_iobp(0xec0040b2, 0x0001c396); + write_iobp(0xea0001a9, 0x80ff94ff); + write_iobp(SATA_IOBP_SP0G3IR, 0x0088037f); + write_iobp(0xea0000a9, 0x80ff94ff); + write_iobp(SATA_IOBP_SP1G3IR, 0x0088037f); - write_2338 (0xea007f05, 0x00010642); - write_2338 (0xea0040b7, 0x0001c91c); - write_2338 (0xea0040b8, 0x0001c91c); - write_2338 (0xeb0040a1, 0x820084ff); - write_2338 (0xec0040a1, 0x820084ff); - write_2338 (0xea007f0a, 0xc2480000); + write_iobp(0xea007f05, 0x00010642); + write_iobp(0xea0040b7, 0x0001c91c); + write_iobp(0xea0040b8, 0x0001c91c); + write_iobp(0xeb0040a1, 0x820084ff); + write_iobp(0xec0040a1, 0x820084ff); + write_iobp(0xea007f0a, 0xc2480000); - write_2338 (0xec00404d, 0x1ff177f); - write_2338 (0xec000084, 0x5a600000); - write_2338 (0xec000184, 0x5a600000); - write_2338 (0xec000284, 0x5a600000); - write_2338 (0xec000384, 0x5a600000); - write_2338 (0xec000094, 0x000f0501); - write_2338 (0xec000194, 0x000f0501); - write_2338 (0xec000294, 0x000f0501); - write_2338 (0xec000394, 0x000f0501); - write_2338 (0xec000096, 0x00000001); - write_2338 (0xec000196, 0x00000001); - write_2338 (0xec000296, 0x00000001); - write_2338 (0xec000396, 0x00000001); - write_2338 (0xec000001, 0x00008c08); - write_2338 (0xec000101, 0x00008c08); - write_2338 (0xec000201, 0x00008c08); - write_2338 (0xec000301, 0x00008c08); - write_2338 (0xec0040b5, 0x0001c518); - write_2338 (0xec000087, 0x06077597); - write_2338 (0xec000187, 0x06077597); - write_2338 (0xec000287, 0x06077597); - write_2338 (0xec000387, 0x06077597); - write_2338 (0xea000050, 0x00bb0157); - write_2338 (0xea000150, 0x00bb0157); - write_2338 (0xec007f60, 0x77777d77); - write_2338 (0xea00008d, 0x01320000); - write_2338 (0xea00018d, 0x01320000); - write_2338 (0xec0007b2, 0x04514b5e); - write_2338 (0xec00078c, 0x40000200); - write_2338 (0xec000780, 0x02000020); + write_iobp(0xec00404d, 0x1ff177f); + write_iobp(0xec000084, 0x5a600000); + write_iobp(0xec000184, 0x5a600000); + write_iobp(0xec000284, 0x5a600000); + write_iobp(0xec000384, 0x5a600000); + write_iobp(0xec000094, 0x000f0501); + write_iobp(0xec000194, 0x000f0501); + write_iobp(0xec000294, 0x000f0501); + write_iobp(0xec000394, 0x000f0501); + write_iobp(0xec000096, 0x00000001); + write_iobp(0xec000196, 0x00000001); + write_iobp(0xec000296, 0x00000001); + write_iobp(0xec000396, 0x00000001); + write_iobp(0xec000001, 0x00008c08); + write_iobp(0xec000101, 0x00008c08); + write_iobp(0xec000201, 0x00008c08); + write_iobp(0xec000301, 0x00008c08); + write_iobp(0xec0040b5, 0x0001c518); + write_iobp(0xec000087, 0x06077597); + write_iobp(0xec000187, 0x06077597); + write_iobp(0xec000287, 0x06077597); + write_iobp(0xec000387, 0x06077597); + write_iobp(0xea000050, 0x00bb0157); + write_iobp(0xea000150, 0x00bb0157); + write_iobp(0xec007f60, 0x77777d77); + write_iobp(0xea00008d, 0x01320000); + write_iobp(0xea00018d, 0x01320000); + write_iobp(0xec0007b2, 0x04514b5e); + write_iobp(0xec00078c, 0x40000200); + write_iobp(0xec000780, 0x02000020); init_dmi(); }

1 0

Patch set updated for coreboot: bd82x6x/pch: move global variables to static variables in functions
by Stefan Reinauer 16 Aug '16

16 Aug '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16213 -gerrit commit f5c1c10285911646bd0285974897a9294c567150 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sat Aug 13 23:27:15 2016 +0200 bd82x6x/pch: move global variables to static variables in functions Change-Id: I9e5795f9d601e5d2e7331715e5cd3848389cd594 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/southbridge/intel/bd82x6x/pch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 4a5b1c2..974abb1 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -26,11 +26,10 @@ #endif #include "pch.h" -static int pch_revision_id = -1; -static int pch_type = -1; int pch_silicon_revision(void) { + static int pch_revision_id = -1; device_t dev; #ifdef __SMM__ @@ -46,6 +45,7 @@ int pch_silicon_revision(void) int pch_silicon_type(void) { + static int pch_type = -1; device_t dev; #ifdef __SMM__

1 0

New patch to review for coreboot: soc/intel/apollolake: ASL methods for eMMC
by Vaibhav Shankar 16 Aug '16

16 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit b3047f930b32d7de6a83a80e8687e4b8276c7dcf Author: vaibhav <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: ASL methods for eMMC PS0 and PS3 methods implemented to support eMMC power gate in S0ix suspend and resume. Signed-off-by: vaibhav <vaibhav.shankar(a)intel.com> Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 --- src/soc/intel/apollolake/acpi/scs.asl | 103 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 4 + 2 files changed, 107 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..32bed29 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,103 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Broxton *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ +scope (\_SB.PCI0) { + + OperationRegion (SBMM, SystemMemory, OR( OR (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + Offset (0x00), + GENR, 32, + Offset (0x08), + , 5, + GRR3, 1, + } + + // + // SCC power gate control method, this method must be serialized as multiple + // device will control + //the GENR register + // + // Arguments: (2) + // Arg0: 0-AND 1-OR + // Arg1: Value + Method (SCPG, 2, Serialized) + { + Name (TMP, 0x0) + if (LEqual(Arg0, 0x1)) { + Store (\_SB.PCI0.GENR, TMP) + Or (TMP, Arg1, \_SB.PCI0.GENR) + + } ElseIf(LEqual(Arg0, 0x0)) { + Store (\_SB.PCI0.GENR, TMP) + And (TMP, Arg1, \_SB.PCI0.GENR) + } + } + + // + // eMMC + // + Device(SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + //Method for port80 debug + OperationRegion (POST, SystemIO, 0x80, 1) + Field (POST, ByteAcc, Lock, Preserve) + { + DBG0, 8 + } + + Method (_PS0, 0, NotSerialized) // _PS0: Power State 0 + { + // To enable port 80 debug + // Store(0xB1, DBG0) + + // Clear clock gate + \_SB.PCI0.SCPG(0,0xFFFFFFBE) // Clear bit 6 and 0 + Sleep (2) // Sleep 2 ms + // To enable port 80 debug + // Store(0xB2, DBG0) + } + + Method (_PS3, 0, NotSerialized) // _PS3: Power State 3 + { + // + // Enable power gate + // To enable port 80 debug + // Store(0xB3, DBG0) + + // Restore clock gate + \_SB.PCI0.SCPG(1,0x00000041) // restore bit 6 and 0 + + // To enable port 80 debug + //Store(0xB4, DBG0) + } + + } // Device(SDHA) + +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..75b681c 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,9 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2016