coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

1 participants
1551 discussions

Patch set updated for coreboot: soc/intel/skylake: restore MCHBAR and DMIBAR programming
by Rizwan Qureshi 15 Aug '16

15 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16224 -gerrit commit be6975e3b03f99d3e8ea047f7cb813fcedaacfe2 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Aug 15 20:43:58 2016 +0530 soc/intel/skylake: restore MCHBAR and DMIBAR programming Program MCHBAR, DMIBAR, EPBAR, EDRAMBAR and GDXCBAR. Also program the PAM registers. The system agent was being programmed in romstage during pre-console initialization, after moving to C_ENVIRONMENT bootblock this was missing, restoring the same. TEST=Build and Boot Kunimitsu Change-Id: Iaf310cfb83e58eb8d5affb481dfc343f5d45961b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/romstage/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 56a5a92..fda6087 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -45,6 +45,9 @@ /* SOC initialization before RAM is enabled */ void soc_pre_ram_init(struct romstage_params *params) { + /* Program MCHBAR and DMIBAR */ + systemagent_early_init(); + /* Prepare to initialize memory */ soc_fill_pei_data(params->pei_data); }

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Patch set updated for coreboot: console: Change CONFIG_CHROMEOS requirement from do_printk_va_list()
by Julius Werner 15 Aug '16

15 Aug '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16230 -gerrit commit 60b91099fa57fc70522a078c49bf4575d83f9872 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 16:14:15 2016 -0700 console: Change CONFIG_CHROMEOS requirement from do_printk_va_list() CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS. Change the code guard for do_printk_va_list() accordingly, since it's used by vboot (not Chrome OS) code. Change-Id: I44e868d2fd8e1368eeda2f10a35d0a2bd7259759 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/include/console/console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/console/console.h b/src/include/console/console.h index f0ab031..202d474 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -60,7 +60,7 @@ static inline void printk(int LEVEL, const char *fmt, ...) {} static inline void do_putchar(unsigned char byte) {} #endif -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_VBOOT) /* FIXME: Collision of varargs with AMD headers without guard. */ #include <console/vtxprintf.h> #if __CONSOLE_ENABLE__

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New patch to review for coreboot: console: Remove CONFIG_CHROMEOS requirement from do_printk_va_list()
by Julius Werner 15 Aug '16

15 Aug '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16230 -gerrit commit be14df63d298071857bc3647f9fd4209fc5f7bd7 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 16:14:15 2016 -0700 console: Remove CONFIG_CHROMEOS requirement from do_printk_va_list() This function is a generic function with a lot of possible uses, and should not be tied to CONFIG_CHROMEOS (especially since it's called from vboot code which is now trying to be independent of CONFIG_CHROMEOS). There is a cryptic comment about a clash with certain AMD headers, but no extra information to follow up... I'll let Jenkins judge whether it still has any merit today. Change-Id: I44e868d2fd8e1368eeda2f10a35d0a2bd7259759 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/include/console/console.h | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/include/console/console.h b/src/include/console/console.h index f0ab031..09137a9 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -20,6 +20,7 @@ #include <rules.h> #include <arch/cpu.h> #include <console/post_codes.h> +#include <console/vtxprintf.h> #include <commonlib/loglevel.h> #ifndef __ROMCC__ @@ -48,6 +49,7 @@ void __attribute__ ((noreturn)) die(const char *msg); asmlinkage void console_init(void); int console_log_level(int msg_level); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +void do_printk_va_list(int msg_level, const char *fmt, va_list args); void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ @@ -57,17 +59,8 @@ void do_putchar(unsigned char byte); static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } static inline void printk(int LEVEL, const char *fmt, ...) {} -static inline void do_putchar(unsigned char byte) {} -#endif - -#if CONFIG_CHROMEOS -/* FIXME: Collision of varargs with AMD headers without guard. */ -#include <console/vtxprintf.h> -#if __CONSOLE_ENABLE__ -void do_printk_va_list(int msg_level, const char *fmt, va_list args); -#else static inline void do_printk_va_list(int l, const char *fmt, va_list args) {} -#endif +static inline void do_putchar(unsigned char byte) {} #endif #endif /* !__ROMCC__ */

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New patch to review for coreboot: vboot: Move TPM-related Kconfig selects from CHROMEOS to VBOOT
by Julius Werner 15 Aug '16

15 Aug '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16229 -gerrit commit 125aa49ee8eddb1597c3b8353dc062e38c17854a Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 16:10:27 2016 -0700 vboot: Move TPM-related Kconfig selects from CHROMEOS to VBOOT CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS. However, the latter still has some 'select' clauses to ensure that required TPM libraries are built. The TPM is an essential part of vboot, and without these libraries the vboot code cannot compile... therefore, they should be moved under CONFIG_VBOOT. Change-Id: I0145558e5127c65c6a82d62f25b5a39e24cb8726 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/vboot/Kconfig | 4 ++++ src/vendorcode/google/chromeos/Kconfig | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index a008208..0838167 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -136,6 +136,10 @@ config VBOOT_OPROM_MATTERS config VBOOT bool "Verify firmware with vboot." default n + select TPM if !MAINBOARD_HAS_TPM2 + select TPM2 if MAINBOARD_HAS_TPM2 + select TPM_INIT_FAILURE_IS_FATAL if PC80_SYSTEM && LPC_TPM + select SKIP_TPM_STARTUP_ON_NORMAL_BOOT if PC80_SYSTEM && LPC_TPM depends on HAVE_HARD_RESET help Enabling VBOOT will use vboot to verify the components of the firmware diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 5134731..063a5a5 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -21,10 +21,6 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" default n - select TPM if !MAINBOARD_HAS_TPM2 - select TPM2 if MAINBOARD_HAS_TPM2 - select TPM_INIT_FAILURE_IS_FATAL if PC80_SYSTEM && LPC_TPM - select SKIP_TPM_STARTUP_ON_NORMAL_BOOT if PC80_SYSTEM && LPC_TPM select ELOG if SPI_FLASH select COLLECT_TIMESTAMPS select VBOOT

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Patch merged into coreboot/master: reef: Increase TSR2 threshold to 100
by gerrit＠coreboot.org 15 Aug '16

15 Aug '16

the following patch was just integrated into master: commit e4cc4733ebd4c6fc77de5f0a9963e9a938e57e5d Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 11 12:39:54 2016 -0700 reef: Increase TSR2 threshold to 100 This is a temporary work-around since the current threshold of 70 on TSR2 results in thermal trip and shutdown while the kernel is booting. Changing this threshold to 100 allows kernel to boot up to userspace. Following values were read: $ cat /sys/class/thermal/thermal_zone4/temp 81800 $ cat /sys/class/thermal/thermal_zone4/type TSR2 BUG=chrome-os-partner:56155 BRANCH=None TEST=Boots to OS. Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/16156 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16156 for details. -gerrit

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Patch set updated for coreboot: soc/marvell/mvmap2315: Add MCU driver
by hakim giydan 15 Aug '16

15 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15529 -gerrit commit f4e8c6f1ae7f73eaf9e3061dc9541935fc1ed4b5 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Mon Aug 15 14:04:20 2016 -0700 soc/marvell/mvmap2315: Add MCU driver Testing: booted successfully. Change-Id: I003f6929b00476d46be931773cd35418fe6622a6 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/bootblock.c | 8 ++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/mcu.h | 116 ++++++++++++++++++ src/soc/marvell/mvmap2315/mcu.c | 130 +++++++++++++++++++++ src/soc/marvell/mvmap2315/pmic.c | 9 +- 6 files changed, 265 insertions(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index b1f7751..4b8a53f 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -26,6 +26,7 @@ bootblock-y += gic.c bootblock-y += gpio.c bootblock-y += flash.c bootblock-y += load_validate.c +bootblock-y += mcu.c bootblock-y += media.c bootblock-y += nvm.c bootblock-y += pinmux.c diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 7a8919c..04f2436 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -27,6 +27,7 @@ #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> +#include <soc/mcu.h> #include <soc/pmic.h> #include <soc/uart.h> @@ -60,6 +61,13 @@ void bootblock_soc_init(void) boot_path = get_boot_path(); } else { printk(BIOS_DEBUG, "Low power restart. Skip MCU code load.\n"); + + sned_hash_msg(GET_HASH); + receive_hash_msg_respond(); + + printk(BIOS_DEBUG, + "MCU hash validation not currently implemented\n"); + boot_path = get_boot_path(); } diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 0a3f555..4cb8993 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -27,6 +27,8 @@ #define MVMAP2315_GPIOH_BASE 0xE0142200 #define MVMAP2315_WDT0_BASE 0XE1010000 #define MVMAP2315_WDT1_BASE 0XE1020000 +#define MVMAP2315_SP_IPC_BASE 0xED0C2000 +#define MVMAP2315_MCU_MSG_BUFF_BASE 0xEE03FF8C #define MVMAP2315_A2BUS_BANKED_BASE 0xF0000000 #define MVMAP2315_A2BUS_ALIAS6_BASE 0xF0002000 diff --git a/src/soc/marvell/mvmap2315/include/soc/mcu.h b/src/soc/marvell/mvmap2315/include/soc/mcu.h new file mode 100644 index 0000000..1d4014c --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/mcu.h @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MCU_H__ +#define __SOC_MARVELL_MVMAP2315_MCU_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_MCU_MSG_OFFSET 0xCE000000 + +enum { + GET_HASH = 0x0, + ABORT_HASH = 0x1, + START_HASH = 0x2, + SYNC_HASH = 0x3, +}; + +enum { + ABORT = 0x0, + FINISHED = 0x1, + BUSY = 0x2 +}; + +enum { + MSG_READY = 1, + MSG_RECEIVED = 8, + MSG_READY_RECEIVED = 9, +}; + +struct sp_hash_request_msg { + u8 protocol_version; + u8 csum; + u16 cmd_id; + u8 cmd_version; + u8 reserved0; + u16 length; + u8 hash_subcmd; + u8 hash_type; + u8 nonce_size; + u8 reserved1; + u32 offset; + u32 size; + u8 nonce_data[64]; +}; + +check_member(sp_hash_request_msg, nonce_data, 0x14); +static struct sp_hash_request_msg * const mvmap2315_mcu_msg_buff + = (void *)MVMAP2315_MCU_MSG_BUFF_BASE; + +struct mcu_hash_msg { + u8 protocol_version; + u8 csum; + u16 result; + u16 length; + u8 status; + u8 type; + u8 digest_size; + u8 reserved0; + u32 offset; + u32 size; + u8 digest_data[64]; +}; + +struct mcu_pwr_status_msg { + u8 protocol_version; + u8 csum; + u16 cmd_id; + u8 cmd_version; + u8 reserved; + u16 length; + u8 status; +}; + +#define MVMAP2315_IPC_IRQSET_MSGSENT BIT(0) +#define MVMAP2315_IPC_IRQCLR_MSGREADY BIT(0) +#define MVMAP2315_IPC_IRQCLR_MSGRECEIVED BIT(3) +#define MVMAP2315_IPC_IRQACK BIT(3) +#define MVMAP2315_MCU_IPC_IRQ BIT(6) +struct mvmap2315_ipc_regs { + u32 isrr; + u32 wdr0; + u32 wdr1; + u32 isrw; + u32 icr; + u32 iir; + u32 rdr0; + u32 rdr1; + u32 maj_mid_rev; + u32 cfg_rev; + u32 dummy; +}; + +check_member(mvmap2315_ipc_regs, dummy, 0x28); +static struct mvmap2315_ipc_regs * const mvmap2315_sp_ipc + = (void *)MVMAP2315_SP_IPC_BASE; + +void mcu_irq(void); +void send_mcu_msg(void *msg, u32 size); +void *receive_mcu_msg(void); +void sned_hash_msg(u8 subcmd); +void *receive_hash_msg_respond(void); + +#endif /* __SOC_MARVELL_MVMAP2315_MCU_H__ */ diff --git a/src/soc/marvell/mvmap2315/mcu.c b/src/soc/marvell/mvmap2315/mcu.c new file mode 100644 index 0000000..c334cda --- /dev/null +++ b/src/soc/marvell/mvmap2315/mcu.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/gic.h> +#include <soc/mcu.h> + +static u8 mvmap2315_calc_checksum(const void *data, u32 size) +{ + u8 csum; + const u8 *bytes = data; + int i; + + for (i = csum = 0; i < size; i++) + csum += bytes[i]; + + return (~csum) && 0xFF; +} + +void mcu_irq(void) +{ + printk(BIOS_DEBUG, "waiting for MCU msg...\n"); + while (!(read32(&mvmap2315_bcm_gicd->ispendr2) & + MVMAP2315_MCU_IPC_IRQ)) + ; +} + +void send_mcu_msg(void *msg, u32 size) +{ + printk(BIOS_DEBUG, "sending msg to MCU...\n"); + write32(&mvmap2315_sp_ipc->wdr0, (u32)msg); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQSET_MSGSENT); +} + +void *receive_mcu_msg(void) +{ + void *msg; + + printk(BIOS_DEBUG, "receiving msg to MCU...\n"); + + write32(&mvmap2315_sp_ipc->dummy, 0xA5A5A5A5); + + switch (read32(&mvmap2315_sp_ipc->iir)) { + case MSG_READY: + msg = (void *)(read32(&mvmap2315_sp_ipc->rdr0) + + MVMAP2315_MCU_MSG_OFFSET); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGREADY); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQACK); + break; + case MSG_RECEIVED: + msg = NULL; + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGRECEIVED); + break; + case MSG_READY_RECEIVED: + msg = (void *)(read32(&mvmap2315_sp_ipc->rdr0) + + MVMAP2315_MCU_MSG_OFFSET); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGREADY); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGRECEIVED); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQACK); + + break; + default: + msg = NULL; + write32(&mvmap2315_sp_ipc->icr, read32(&mvmap2315_sp_ipc->iir)); + break; + } + + return msg; +} + +void sned_hash_msg(u8 subcmd) +{ + printk(BIOS_DEBUG, "requesting MCU hash...\n"); + + mvmap2315_mcu_msg_buff->protocol_version = 0x3; + mvmap2315_mcu_msg_buff->cmd_id = 0x2A; + mvmap2315_mcu_msg_buff->reserved0 = 0x0; + mvmap2315_mcu_msg_buff->length = 76; + mvmap2315_mcu_msg_buff->csum = 0; + mvmap2315_mcu_msg_buff->hash_subcmd = subcmd; + mvmap2315_mcu_msg_buff->hash_type = 0; + mvmap2315_mcu_msg_buff->nonce_size = 0; + mvmap2315_mcu_msg_buff->reserved1 = 0; + mvmap2315_mcu_msg_buff->offset = 0; + mvmap2315_mcu_msg_buff->size = 32; + mvmap2315_mcu_msg_buff->csum = mvmap2315_calc_checksum( + (void *)mvmap2315_mcu_msg_buff, + sizeof(struct sp_hash_request_msg)); + + send_mcu_msg((void *)mvmap2315_mcu_msg_buff, + sizeof(struct sp_hash_request_msg)); +} + +void *receive_hash_msg_respond(void) +{ + struct mcu_hash_msg *mvmap2315_hash_msg_response; + + printk(BIOS_DEBUG, "waiting for MCU hash response msg...\n"); + + mcu_irq(); + + mvmap2315_hash_msg_response = receive_mcu_msg(); + + mcu_irq(); + + receive_mcu_msg(); + + return mvmap2315_hash_msg_response; +} diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c index 5c43fd2..a8448cc 100644 --- a/src/soc/marvell/mvmap2315/pmic.c +++ b/src/soc/marvell/mvmap2315/pmic.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <soc/apmu.h> #include <soc/clock.h> +#include <soc/mcu.h> #include <soc/pmic.h> static void syspwr_init(void) @@ -117,5 +118,11 @@ void mcu_start(void) u32 get_boot_path(void) { - return FULL_BOOT; + struct mcu_pwr_status_msg *msg; + + mcu_irq(); + + msg = receive_mcu_msg(); + + return msg->status; }

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Patch set updated for coreboot: console/serialice: Add SerialICE
by Antonello Dettori 15 Aug '16

15 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 8087085ad83ef2b78cef8d571ba6942476944e9a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520 and Lenovo X60. Needs tests: * Ramstage Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/Kconfig | 34 ++++ src/arch/x86/c_start.S | 2 +- src/arch/x86/exception.c | 7 +- src/console/Makefile.inc | 2 + src/console/console.c | 23 --- src/console/init.c | 9 +- src/console/serialice.c | 430 ++++++++++++++++++++++++++++++++++++++++ src/console/serialice_priv.h | 105 ++++++++++ src/include/console/serialice.h | 30 +++ src/include/console/streams.h | 6 - src/include/console/uart.h | 8 - src/include/console/usb.h | 10 - src/include/debug-com.h | 24 +++ src/lib/Makefile.inc | 5 + src/lib/debug-com.c | 99 +++++++++ 15 files changed, 740 insertions(+), 54 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 001132e..a3acf1e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1118,6 +1118,40 @@ config DEBUG_BOOT_STATE Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + default n + depends on ARCH_X86 + depends on CONSOLE_SERIAL || CONSOLE_USB + depends on !GDB_STUB + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +if DEBUG_SERIALICE + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + depends on CONSOLE_SERIAL || USBDEBUG_IN_ROMSTAGE + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + +endif + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 9a64fa6..0946432 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -111,7 +111,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT - call gdb_hw_init + call debug_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index cbf0358..d913f58 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -14,6 +14,7 @@ #include <console/console.h> #include <console/streams.h> #include <string.h> +#include <debug-com.h> #if CONFIG_GDB_STUB @@ -231,17 +232,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - gdb_tx_byte(ch); + debug_tx_byte(ch); } static inline void stub_flush(void) { - gdb_tx_flush(); + debug_tx_flush(); } static inline int stub_getc(void) { - return gdb_rx_byte(); + return debug_rx_byte(); } static int hex(char ch) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 68afb8a..9514fd3 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/console.c b/src/console/console.c index 7b0dfc2..bb659b4 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -74,26 +74,3 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes) while (number_of_bytes--) console_tx_byte(*buffer++); } - - -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -void gdb_hw_init(void) -{ - __gdb_hw_init(); -} - -void gdb_tx_byte(unsigned char byte) -{ - __gdb_tx_byte(byte); -} - -void gdb_tx_flush(void) -{ - __gdb_tx_flush(); -} - -unsigned char gdb_rx_byte(void) -{ - return __gdb_rx_byte(); -} -#endif diff --git a/src/console/init.c b/src/console/init.c index 189079b..0fe6d7e 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -14,13 +14,14 @@ * GNU General Public License for more details. */ +#include <option.h> +#include <rules.h> +#include <version.h> #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> -#include <option.h> -#include <rules.h> -#include <version.h> /* While in romstage, console loglevel is built-time constant. */ static ROMSTAGE_CONST int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; @@ -43,6 +44,8 @@ asmlinkage void console_init(void) console_hw_init(); + serialice_main(); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..d33e925 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,430 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/serialice.h> +#include <arch/io.h> +#include <debug-com.h> +#include "serialice_priv.h" + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + debug_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + debug_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + val = debug_rx_byte(); + if (val) { +#if ECHO_MODE + sio_putc(val); +#endif + return val; + } + + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = s_cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = s_cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = s_cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = s_cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +void serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } +} diff --git a/src/console/serialice_priv.h b/src/console/serialice_priv.h new file mode 100644 index 0000000..0004c9a --- /dev/null +++ b/src/console/serialice_priv.h @@ -0,0 +1,105 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +#include <stdint.h> + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 s_cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 s_cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 s_cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 s_cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..a2b27e7 --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,30 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#define ECHO_MODE 1 + +#if (ENV_RAMSTAGE && CONFIG_DEBUG_SERIALICE_RAMSTAGE) || \ + (ENV_ROMSTAGE && CONFIG_DEBUG_SERIALICE_ROMSTAGE) +void serialice_main(void); +#else +static inline void serialice_main(void) { } +#endif + +#endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 6e944a6..9b62585 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -27,10 +27,4 @@ void console_tx_flush(void); */ void console_write_line(uint8_t *buffer, size_t number_of_bytes); -/* For remote GDB debugging. */ -void gdb_hw_init(void); -void gdb_tx_byte(unsigned char byte); -void gdb_tx_flush(void); -unsigned char gdb_rx_byte(void); - #endif /* _CONSOLE_STREAMS_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ffcc088..00c2083 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -69,14 +69,6 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE -static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } -static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } -#endif - #endif /* __ROMCC__ */ #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..ebf7a2b 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -31,7 +31,6 @@ int usb_can_rx_byte(int idx); ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) #define USB_PIPE_FOR_CONSOLE 0 -#define USB_PIPE_FOR_GDB 0 #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } @@ -43,13 +42,4 @@ static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} #endif -/* */ -#if 0 && CONFIG_GDB_STUB && \ - ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } -#endif - #endif /* _CONSOLE_USB_H_ */ diff --git a/src/include/debug-com.h b/src/include/debug-com.h new file mode 100644 index 0000000..d716ee9 --- /dev/null +++ b/src/include/debug-com.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DEBUG_COM_H_ +#define _DEBUG_COM_H_ + +#include <stdint.h> + +void debug_hw_init(void); +void debug_tx_byte(unsigned char byte); +void debug_tx_flush(void); +unsigned char debug_rx_byte(void); + +#endif /* _DEBUG_COM_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5f708a6..9a51c90 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -228,6 +228,11 @@ postcar-y += prog_ops.c postcar-y += rmodule.c postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += debug-com.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += debug-com.c +romstage-$(CONFIG_GDB_STUB) += debug-com.c +ramstage-$(CONFIG_GDB_STUB) += debug-com.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld diff --git a/src/lib/debug-com.c b/src/lib/debug-com.c new file mode 100644 index 0000000..b8cfaa7 --- /dev/null +++ b/src/lib/debug-com.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <stdint.h> +#include <console/uart.h> +#include <console/usb.h> +#include <debug-com.h> + +#define CONFIG_UART_FOR_GDB 0 +#define USB_PIPE_FOR_GDB 0 + +#define CONFIG_UART_FOR_SERIALICE 0 +#define USB_PIPE_FOR_SERIALICE 0 + +/* Configure functions to use GDB arguments */ +#if __CONSOLE_USB_ENABLE__ && CONFIG_GDB_STUB + +static inline void __debug_hw_init(void) { usbdebug_init(); } +static inline void __debug_tx_byte(u8 data) + { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __debug_tx_flush(void) + { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __debug_rx_byte(void) + { return usb_rx_byte(USB_PIPE_FOR_GDB); } + +#elif __CONSOLE_SERIAL_ENABLE__ && CONFIG_GDB_STUB + +static inline void __debug_hw_init(void) + { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __debug_tx_byte(u8 data) + { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __debug_tx_flush(void) + { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __debug_rx_byte(void) + { return uart_rx_byte(CONFIG_UART_FOR_GDB); } + +/* Configure functions to use SerialICE arguments */ +#elif __CONSOLE_USB_ENABLE__ && CONFIG_DEBUG_SERIALICE + +static inline void __debug_hw_init(void) { usbdebug_init(); } +static inline void __debug_tx_byte(u8 data) + { usb_tx_byte(USB_PIPE_FOR_SERIALICE, data); } +static inline void __debug_tx_flush(void) + { usb_tx_flush(USB_PIPE_FOR_SERIALICE); } +static inline u8 __debug_rx_byte(void) + { return usb_rx_byte(USB_PIPE_FOR_SERIALICE); } + +#elif __CONSOLE_SERIAL_ENABLE__ && CONFIG_DEBUG_SERIALICE + +static inline void __debug_hw_init(void) + { uart_init(CONFIG_UART_FOR_SERIALICE); } +static inline void __debug_tx_byte(u8 data) + { uart_tx_byte(CONFIG_UART_FOR_SERIALICE, data); } +static inline void __debug_tx_flush(void) + { uart_tx_flush(CONFIG_UART_FOR_SERIALICE); } +static inline u8 __debug_rx_byte(void) + { return uart_rx_byte(CONFIG_UART_FOR_SERIALICE); } + +#else + +static inline void __debug_hw_init(void) {} +static inline void __debug_tx_byte(u8 data) {} +static inline void __debug_tx_flush(void) {} +static inline u8 __debug_rx_byte(void) { return 0; } + +#endif + + +void debug_hw_init(void) +{ + __debug_hw_init(); +} + +void debug_tx_byte(unsigned char byte) +{ + __debug_tx_byte(byte); +} + +void debug_tx_flush(void) +{ + __debug_tx_flush(); +} + +unsigned char debug_rx_byte(void) +{ + return __debug_rx_byte(); +} +

1 0

Patch set updated for coreboot: vboot/vbnv_flash: make I/O connection agnostic
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16206 -gerrit commit a5bddfd54f893af4823b0e3435233bd50adf2113 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:48:58 2016 -0500 vboot/vbnv_flash: make I/O connection agnostic There's no need to be SPI specific w.r.t. how the flash is connected. Therefore, use the RW boot device to write the contents of VBNV. The erasable check was dropped because that information isn't available. All regions should be aligned accordingly on the platform for the underlying hardware implementation. And once the VBNV region fills the erase will fail. BUG=chrome-os-partner:56151 Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vboot/Kconfig | 3 +- src/vboot/vbnv_flash.c | 82 +++++++++----------------------------------------- 2 files changed, 16 insertions(+), 69 deletions(-) diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index a008208..30d322e 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -29,7 +29,7 @@ config VBOOT_VBNV_CMOS config VBOOT_VBNV_CMOS_BACKUP_TO_FLASH bool "Back up Vboot non-volatile storage from CMOS to flash." default n - depends on VBOOT_VBNV_CMOS + depends on VBOOT_VBNV_CMOS && BOOT_DEVICE_SUPPORTS_WRITES help Vboot non-volatile storage data will be backed up from CMOS to flash and restored from flash if the CMOS is invalid due to power loss. @@ -42,6 +42,7 @@ config VBOOT_VBNV_EC config VBOOT_VBNV_FLASH def_bool n + depends on BOOT_DEVICE_SUPPORTS_WRITES help VBNV is stored in flash storage diff --git a/src/vboot/vbnv_flash.c b/src/vboot/vbnv_flash.c index 717ff23..d061228 100644 --- a/src/vboot/vbnv_flash.c +++ b/src/vboot/vbnv_flash.c @@ -17,7 +17,6 @@ #include <assert.h> #include <commonlib/region.h> #include <console/console.h> -#include <spi_flash.h> #include <string.h> #include <vb2_api.h> #include <vboot_nvstorage.h> @@ -31,17 +30,14 @@ struct vbnv_flash_ctx { /* VBNV flash is initialized */ int initialized; - /* Offset of the current nvdata in SPI flash */ + /* Offset of the current nvdata in flash */ int blob_offset; - /* Offset of the topmost nvdata blob in SPI flash */ + /* Offset of the topmost nvdata blob in flash */ int top_offset; - /* SPI flash handler used when saving data */ - struct spi_flash *flash; - - /* FMAP descriptor of the NVRAM area */ - struct region_device region; + /* Region to store and retrieve the VBNV contents. */ + struct region_device vbnv_dev; /* Cache of the current nvdata */ uint8_t cache[BLOB_SIZE]; @@ -66,13 +62,14 @@ static inline int can_overwrite(uint8_t current, uint8_t new) static int init_vbnv(void) { struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + struct region_device *rdev = &ctx->vbnv_dev; uint8_t buf[BLOB_SIZE]; uint8_t empty_blob[BLOB_SIZE]; int offset; int i; - if (vboot_named_region_device("RW_NVRAM", &ctx->region) || - region_device_sz(&ctx->region) < BLOB_SIZE) { + if (vboot_named_region_device_rw("RW_NVRAM", rdev) || + region_device_sz(rdev) < BLOB_SIZE) { printk(BIOS_ERR, "%s: failed to locate NVRAM\n", __func__); return 1; } @@ -82,7 +79,7 @@ static int init_vbnv(void) empty_blob[i] = erase_value(); offset = 0; - ctx->top_offset = region_device_sz(&ctx->region) - BLOB_SIZE; + ctx->top_offset = region_device_sz(rdev) - BLOB_SIZE; /* * after the loop, offset is supposed to point the blob right before @@ -91,7 +88,7 @@ static int init_vbnv(void) * used. */ for (i = 0; i <= ctx->top_offset; i += BLOB_SIZE) { - if (rdev_readat(&ctx->region, buf, i, BLOB_SIZE) < 0) { + if (rdev_readat(rdev, buf, i, BLOB_SIZE) < 0) { printk(BIOS_ERR, "failed to read nvdata\n"); return 1; } @@ -101,7 +98,7 @@ static int init_vbnv(void) } /* reread the nvdata and write it to the cache */ - if (rdev_readat(&ctx->region, ctx->cache, offset, BLOB_SIZE) < 0) { + if (rdev_readat(rdev, ctx->cache, offset, BLOB_SIZE) < 0) { printk(BIOS_ERR, "failed to read nvdata\n"); return 1; } @@ -112,61 +109,12 @@ static int init_vbnv(void) return 0; } -static void vbnv_is_erasable(void) -{ - /* - * We check whether the region is aligned or not in advance to ensure - * we can erase the region when it's all used up. - * - * The region offset & size are determined by fmap.dts yet the check can - * be confidently done only by the spi flash driver. We use the same - * check as the one used by spi_flash_cmd_erase, which happens to be - * common to all the spi flash parts we support. - * - * TODO: Check by calling can_erase implemented by each spi flash driver - */ - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); - - assert(!(region_device_offset(&ctx->region) % ctx->flash->sector_size)); - assert(!(region_device_sz(&ctx->region) % ctx->flash->sector_size)); -} - -static int vbnv_flash_probe(void) -{ - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); - - if (!ctx->flash) { - ctx->flash = - spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); - if (!ctx->flash) { - printk(BIOS_ERR, "failed to probe spi flash\n"); - return 1; - } - /* - * Called here instead of init_vbnv to reduce impact on boot - * speed. - */ - vbnv_is_erasable(); - } - - /* - * Handle the case where spi_flash_probe returns a CAR_GLOBAL - * in early execution on x86 but then later is moved to RAM. - */ - ctx->flash = car_get_var_ptr(ctx->flash); - - return 0; -} - static int erase_nvram(void) { struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + const struct region_device *rdev = &ctx->vbnv_dev; - if (vbnv_flash_probe()) - return 1; - - if (ctx->flash->erase(ctx->flash, region_device_offset(&ctx->region), - region_device_sz(&ctx->region))) { + if (rdev_eraseat(rdev, 0, region_device_sz(rdev)) < 0) { printk(BIOS_ERR, "failed to erase nvram\n"); return 1; } @@ -191,6 +139,7 @@ void save_vbnv_flash(const uint8_t *vbnv_copy) struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); int new_offset; int i; + const struct region_device *rdev = &ctx->vbnv_dev; if (!ctx->initialized) if (init_vbnv()) @@ -216,10 +165,7 @@ void save_vbnv_flash(const uint8_t *vbnv_copy) } } - if (!vbnv_flash_probe() && - !ctx->flash->write(ctx->flash, - region_device_offset(&ctx->region) + new_offset, - BLOB_SIZE, vbnv_copy)) { + if (rdev_writeat(rdev, vbnv_copy, new_offset, BLOB_SIZE) < 0) { /* write was successful. safely move pointer forward */ ctx->blob_offset = new_offset; memcpy(ctx->cache, vbnv_copy, BLOB_SIZE);

1 0

Patch set updated for coreboot: drivers/elog: use region_device for NV storage
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16204 -gerrit commit b65509f189b8515292c0c40d8869c229fc6c98dd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 10 11:37:14 2016 -0500 drivers/elog: use region_device for NV storage Instead of assuming SPI backing use a region_device to abstract away the underlying storage mechanism. BUG=chrome-os-partner:55932 Change-Id: I6b0f5a7e9bea8833fb1bca87e02abefab63acec3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/elog/Kconfig | 4 +- src/drivers/elog/elog.c | 98 +++++++++++++++++----------------- src/vendorcode/google/chromeos/Kconfig | 2 +- 3 files changed, 51 insertions(+), 53 deletions(-) diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index cb5d3d4..c7bed75 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -14,9 +14,9 @@ ## config ELOG - depends on SPI_FLASH bool "Support for flash based event log" default n + depends on BOOT_DEVICE_SUPPORTS_WRITES help Enable support for flash based event logging. @@ -39,7 +39,7 @@ config ELOG_CBMEM endif config ELOG_GSMI - depends on ELOG && SPI_FLASH_SMM && SMM_TSEG + depends on ELOG && SMM_TSEG bool "SMI interface to write and clear event log" default n help diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 3d8c85c8..0f72e7c 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -29,8 +29,6 @@ #include <lib.h> #include <rtc.h> #include <smbios.h> -#include <spi-generic.h> -#include <spi_flash.h> #include <stdint.h> #include <string.h> #include <elog.h> @@ -47,8 +45,6 @@ /* * Static variables for ELOG state */ -static u16 total_size; -static u32 flash_base; static u16 full_threshold; static u16 shrink_size; @@ -60,7 +56,7 @@ static u16 shrink_size; static size_t mirror_last_write; static size_t nv_last_write; -static struct spi_flash *elog_spi; +static struct region_device nv_dev; /* Device that mirrors the eventlog in memory. */ static struct mem_region_device mirror_dev; @@ -83,7 +79,7 @@ static size_t elog_events_start(void) static size_t elog_events_total_space(void) { - return total_size - elog_events_start(); + return region_device_sz(&nv_dev) - elog_events_start(); } static struct event_header *elog_get_event_buffer(size_t offset, size_t size) @@ -187,7 +183,7 @@ static void elog_debug_dump_buffer(const char *msg) if (buffer == NULL) return; - hexdump(buffer, total_size); + hexdump(buffer, region_device_sz(rdev)); rdev_munmap(rdev, buffer); } @@ -318,27 +314,26 @@ static size_t elog_is_event_valid(size_t offset) * the flash backing store. This will not erase the flash and it assumes the * flash area has been erased appropriately. */ -static void elog_flash_write(size_t offset, size_t size) +static void elog_nv_write(size_t offset, size_t size) { void *address; const struct region_device *rdev = mirror_dev_get(); - if (!size || !elog_spi) + if (!size) return; address = rdev_mmap(rdev, offset, size); - /* Ensure offset is absolute. */ - offset += flash_base; - - elog_debug("elog_flash_write(address=0x%p offset=0x%08x size=%u)\n", + elog_debug("%s(address=0x%p offset=0x%08x size=%u)\n", __func__, address, offset, size); if (address == NULL) return; /* Write the data to flash */ - elog_spi->write(elog_spi, offset, size, address); + if (rdev_writeat(&nv_dev, address, offset, size) != size) + printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n", + offset, size); rdev_munmap(rdev, address); } @@ -347,16 +342,14 @@ static void elog_flash_write(size_t offset, size_t size) * Erase the first block specified in the address. * Only handles flash area within a single flash block. */ -static void elog_flash_erase(void) +static void elog_nv_erase(void) { - if (!elog_spi) - return; - - elog_debug("elog_flash_erase(offset=0x%08x size=%u)\n", - flash_base, total_size); + size_t size = region_device_sz(&nv_dev); + elog_debug("%s()\n", __func__); /* Erase the sectors in this region */ - elog_spi->erase(elog_spi, flash_base, total_size); + if (rdev_eraseat(&nv_dev, 0, size) != size) + printk(BIOS_ERR, "ELOG: erase failure.\n"); } /* @@ -413,10 +406,15 @@ static int elog_scan_flash(void) elog_debug("elog_scan_flash()\n"); void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); + size_t size = region_device_sz(&nv_dev); /* Fill memory buffer by reading from SPI */ mirror_buffer = rdev_mmap_full(rdev); - elog_spi->read(elog_spi, flash_base, total_size, mirror_buffer); + if (rdev_readat(&nv_dev, mirror_buffer, 0, size) != size) { + rdev_munmap(rdev, mirror_buffer); + printk(BIOS_ERR, "ELOG: NV read failure.\n"); + return -1; + } rdev_munmap(rdev, mirror_buffer); /* No writes have been done yet. */ @@ -590,10 +588,12 @@ static inline u8 *elog_flash_offset_to_address(void) if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) return NULL; - if (!elog_spi) + if (!region_device_sz(&nv_dev)) return NULL; - return rdev_mmap(boot_device_ro(), flash_base, total_size); + /* Get a view into the read-only boot device. */ + return rdev_mmap(boot_device_ro(), region_device_offset(&nv_dev), + region_device_sz(&nv_dev)); } /* @@ -605,12 +605,13 @@ int elog_smbios_write_type15(unsigned long *current, int handle) struct smbios_type15 *t = (struct smbios_type15 *)*current; int len = sizeof(struct smbios_type15); uintptr_t log_address; + size_t elog_size = region_device_sz(&nv_dev); if (IS_ENABLED(CONFIG_ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ - void *cbmem = cbmem_add(CBMEM_ID_ELOG, total_size); + void *cbmem = cbmem_add(CBMEM_ID_ELOG, elog_size); if (cbmem) - rdev_readat(mirror_dev_get(), cbmem, 0, total_size); + rdev_readat(mirror_dev_get(), cbmem, 0, elog_size); log_address = (uintptr_t)cbmem; } else { log_address = (uintptr_t)elog_flash_offset_to_address(); @@ -625,7 +626,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle) t->type = SMBIOS_EVENT_LOG; t->length = len - 2; t->handle = handle; - t->area_length = total_size - 1; + t->area_length = elog_size - 1; t->header_offset = 0; t->data_offset = sizeof(struct elog_header); t->access_method = SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32; @@ -656,26 +657,30 @@ int elog_clear(void) static int elog_find_flash(void) { - struct region r; + size_t total_size; size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE; + struct region_device *rdev = &nv_dev; - elog_debug("elog_find_flash()\n"); + elog_debug("%s()\n", __func__); /* Find the ELOG base and size in FMAP */ - if (fmap_locate_area("RW_ELOG", &r) < 0) { + if (fmap_locate_area_as_rdev_rw("RW_ELOG", rdev) < 0) { printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP\n"); return -1; } - if (region_sz(&r) < 4*KiB) { + if (region_device_sz(rdev) < 4*KiB) { printk(BIOS_WARNING, "ELOG: Needs a minium size of 4KiB: %zu\n", - region_sz(&r)); + region_device_sz(rdev)); return -1; } - flash_base = region_offset(&r); + printk(BIOS_INFO, "ELOG: NV offset 0x%zx size 0x%zx\n", + region_device_offset(rdev), region_device_sz(rdev)); + /* Keep 4KiB max size until large malloc()s have been fixed. */ - total_size = MIN(4*KiB, region_sz(&r)); + total_size = MIN(4*KiB, region_device_sz(rdev)); + rdev_chain(rdev, rdev, 0, total_size); full_threshold = total_size - reserved_space; shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; @@ -702,13 +707,13 @@ static int elog_sync_to_nv(void) /* Erase if necessary. */ if (erase_needed) { - elog_flash_erase(); + elog_nv_erase(); elog_nv_reset_last_write(); } size = elog_nv_region_to_update(&offset); - elog_flash_write(offset, size); + elog_nv_write(offset, size); elog_nv_increment_last_write(size); /* @@ -737,6 +742,7 @@ static int elog_sync_to_nv(void) int elog_init(void) { void *mirror_buffer; + size_t elog_size; switch (elog_initialized) { case ELOG_UNINITIALIZED: @@ -750,23 +756,17 @@ int elog_init(void) elog_debug("elog_init()\n"); - /* Probe SPI chip. SPI controller must already be initialized. */ - elog_spi = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); - if (!elog_spi) { - printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); - return -1; - } - /* Set up the backing store */ if (elog_find_flash() < 0) return -1; - mirror_buffer = malloc(total_size); + elog_size = region_device_sz(&nv_dev); + mirror_buffer = malloc(elog_size); if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; } - mem_region_device_rw_init(&mirror_dev, mirror_buffer, total_size); + mem_region_device_rw_init(&mirror_dev, mirror_buffer, elog_size); /* * Mark as initialized to allow elog_init() to be called and deemed @@ -780,11 +780,9 @@ int elog_init(void) return -1; } - printk(BIOS_INFO, "ELOG: FLASH @0x%p [SPI 0x%08x]\n", - mirror_buffer, flash_base); - - printk(BIOS_INFO, "ELOG: area is %d bytes, full threshold %d," - " shrink size %d\n", total_size, full_threshold, shrink_size); + printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d," + " shrink size %d\n", region_device_sz(&nv_dev), + full_threshold, shrink_size); #if !defined(__SMM__) /* Log boot count event except in S3 resume */ diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 5134731..684a18f 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -25,7 +25,7 @@ config CHROMEOS select TPM2 if MAINBOARD_HAS_TPM2 select TPM_INIT_FAILURE_IS_FATAL if PC80_SYSTEM && LPC_TPM select SKIP_TPM_STARTUP_ON_NORMAL_BOOT if PC80_SYSTEM && LPC_TPM - select ELOG if SPI_FLASH + select ELOG if BOOT_DEVICE_SUPPORTS_WRITES select COLLECT_TIMESTAMPS select VBOOT help

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Patch set updated for coreboot: vboot: provide RW region device support
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16205 -gerrit commit f921f36247453b5796d284a3d6f7889c586acccd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:46:07 2016 -0500 vboot: provide RW region device support Explicitly provide a RW view of an vboot FMAP region. This is required for platforms which have separate implementations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: If8bf2e1c7ca9bff536fc5c578fe0cf92ccbd2ebc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vboot/vboot_common.c | 5 +++++ src/vboot/vboot_common.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/vboot/vboot_common.c b/src/vboot/vboot_common.c index 319e0de..7e1ca9d 100644 --- a/src/vboot/vboot_common.c +++ b/src/vboot/vboot_common.c @@ -30,6 +30,11 @@ int vboot_named_region_device(const char *name, struct region_device *rdev) return fmap_locate_area_as_rdev(name, rdev); } +int vboot_named_region_device_rw(const char *name, struct region_device *rdev) +{ + return fmap_locate_area_as_rdev(name, rdev); +} + /* ========================== VBOOT HANDOFF APIs =========================== */ int vboot_get_handoff_info(void **addr, uint32_t *size) { diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index d64b5bb..59fd44c 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -23,6 +23,9 @@ /* Locate vboot area by name. Returns 0 on success and -1 on error. */ int vboot_named_region_device(const char *name, struct region_device *rdev); +/* Like vboot_named_region_device() but provides a RW region device. */ +int vboot_named_region_device_rw(const char *name, struct region_device *rdev); + /* * Function to check if there is a request to enter recovery mode. Returns * reason code if request to enter recovery mode is present, otherwise 0.

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coreboot-gerrit August 2016