coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Kconfig: introduce writable boot device notion
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16211 -gerrit commit cb84485c5762f0a0b24e0d11dbf9a219b5c04829 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 15:00:10 2016 -0500 Kconfig: introduce writable boot device notion Indicate to the build system that a platform provides support for a writable boot device. The following will provide the necessary support: COMMON_CBFS_SPI_WRAPPER users soc/intel/apollolake soc/intel/baytrail soc/intel/braswell soc/intel/broadwell soc/intel/skylake The SPI_FLASH option is auto-selected if the platform provides write supoprt for the boot device and SPI flash is the boot device. Other platforms may provide similar support, but they do that in a device specific manner such as selecting SPI_FLASH explicitly. This provides clearance against build failures where chipsets don't provide SPI API implementations even though the platform may use a SPI flash to boot. BUG=chrome-os-partner:56151 Change-Id: If78160f231c8312a313f9b9753607d044345d274 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 7 +++++++ src/drivers/spi/Kconfig | 3 ++- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + 7 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index fd98cc8..7db491f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -482,6 +482,13 @@ config BOOT_DEVICE_MEMORY_MAPPED help Inform system if SPI is memory-mapped or not. +config BOOT_DEVICE_SUPPORTS_WRITES + bool + default n + help + Indicate that the platform has writable boot device + support. + config RTC bool default n diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 030fa6c..5eb9b56 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -18,12 +18,13 @@ config COMMON_CBFS_SPI_WRAPPER default n depends on !ARCH_X86 depends on BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES help Use common wrapper to interface CBFS to SPI bootrom. config SPI_FLASH bool - default y if BOOT_DEVICE_SPI_FLASH + default y if BOOT_DEVICE_SPI_FLASH && BOOT_DEVICE_SUPPORTS_WRITES default n help Select this option if your chipset driver needs to store certain diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index dfc2d4a..0c7f27a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b790008..4009785 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index c652d96..b587988 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index f8ec500..03934d2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8c8b1b7..909dcec 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT + select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select C_ENVIRONMENT_BOOTBLOCK

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Patch set updated for coreboot: lib/boot_device: add RW boot device construct
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16194 -gerrit commit 36de8ad76903186e186517a759a9266d15e4acd0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 10 11:42:42 2016 -0500 lib/boot_device: add RW boot device construct The current boot device usage assumes read-only semantics to the boot device. Any time someone wants to write to the boot device a device-specific API is invoked such as SPI flash. Instead, provide a mechanism to retrieve an object that can be used to perform writes to the boot device. On systems where the implementations are symmetric these devices can be treated one-in-the-same. However, for x86 systems with memory mapped SPI the read-only boot device provides different operations. BUG=chrome-os-partner:55932 Change-Id: I0af324824f9e1a8e897c2453c36e865b59c4e004 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot_device.h | 16 ++++++++++++++++ src/lib/boot_device.c | 24 ++++++++++++++++++------ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/src/include/boot_device.h b/src/include/boot_device.h index 3964a95..cc70442 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -18,9 +18,18 @@ #include <commonlib/region.h> +/* + * Please note that the read-only boot device may not be coherent with + * the read-write boot device. Thus, mixing mmap() and writeat() is + * most likely not to work so don't rely on such semantics. + */ + /* Return the region_device for the read-only boot device. */ const struct region_device *boot_device_ro(void); +/* Return the region_device for the read-write boot device. */ +const struct region_device *boot_device_rw(void); + /* * Create a sub-region of the read-only boot device. * Returns 0 on success, < 0 on error. @@ -29,6 +38,13 @@ int boot_device_ro_subregion(const struct region *sub, struct region_device *subrd); /* + * Create a sub-region of the read-write boot device. + * Returns 0 on success, < 0 on error. + */ +int boot_device_rw_subregion(const struct region *sub, + struct region_device *subrd); + +/* * Initialize the boot device. This may be called multiple times within * a stage so boot device implementations should account for this behavior. **/ diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index 42fe5df..e7968f4 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -20,18 +20,30 @@ void __attribute__((weak)) boot_device_init(void) /* Provide weak do-nothing init. */ } +static int boot_device_subregion(const struct region *sub, + struct region_device *subrd, + const struct region_device *parent) +{ + if (parent == NULL) + return -1; + + return rdev_chain(subrd, parent, region_offset(sub), region_sz(sub)); +} + int boot_device_ro_subregion(const struct region *sub, struct region_device *subrd) { - const struct region_device *boot_dev; - /* Ensure boot device has been initialized at least once. */ boot_device_init(); - boot_dev = boot_device_ro(); + return boot_device_subregion(sub, subrd, boot_device_ro()); +} - if (boot_dev == NULL) - return -1; +int boot_device_rw_subregion(const struct region *sub, + struct region_device *subrd) +{ + /* Ensure boot device has been initialized at least once. */ + boot_device_init(); - return rdev_chain(subrd, boot_dev, region_offset(sub), region_sz(sub)); + return boot_device_subregion(sub, subrd, boot_device_rw()); }

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Patch set updated for coreboot: soc/intel/apollolake: make SPI support early stages
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16195 -gerrit commit c600065f729c76f6f1a1ec8c22c2f81c0416b745 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 17:09:57 2016 -0500 soc/intel/apollolake: make SPI support early stages Using malloc() in SPI code is unnecessary as there's only one SPI device that the SoC support code handles: boot device. Therefore, use CAR to for the storage to work around the current limiations of the SPI API which expects one to return pointers to objects that are writable. BUG=chrome-os-partner:56151 Change-Id: If4f5484e27d68b2dd1b17a281cf0b760086850a7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/spi.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 7b390bb..139d36c 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ +#include <arch/early_variables.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -315,6 +316,9 @@ static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg) return E_NOT_IMPLEMENTED; } +static struct spi_slave boot_spi CAR_GLOBAL; +static struct spi_flash boot_flash CAR_GLOBAL; + /* * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. * For details see: @@ -328,11 +332,7 @@ static struct spi_flash *nuclear_flash_probe(struct spi_slave *spi) struct spi_flash *flash; uint32_t flash_bits; - flash = malloc(sizeof(*flash)); - if (!flash) { - printk(BIOS_ERR, "%s(): Could not allocate memory\n", __func__); - return NULL; - } + flash = car_get_var_ptr(&boot_flash); /* * bytes = (bits + 1) / 8; @@ -371,14 +371,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) if ((bus != 0) || (cs != 0)) return NULL; - struct spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_ERR, "%s(): Could not allocate memory\n", __func__); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); + struct spi_slave *slave = car_get_var_ptr(&boot_spi); slave->bus = bus; slave->cs = cs;

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Patch set updated for coreboot: Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16192 -gerrit commit b52b495b81f732d66305ded35a971b98cc433c91 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 14:40:09 2016 -0500 Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 7 ------- src/drivers/elog/elog.c | 2 +- src/drivers/spi/Kconfig | 7 +++++++ src/lib/cbfs_spi.c | 2 +- src/mainboard/google/chell/Kconfig | 4 ---- src/mainboard/google/cosmos/Kconfig | 2 +- src/mainboard/google/foster/Kconfig | 2 +- src/mainboard/google/glados/Kconfig | 4 ---- src/mainboard/google/gru/Kconfig | 2 +- src/mainboard/google/gru/bootblock.c | 2 +- src/mainboard/google/lars/Kconfig | 4 ---- src/mainboard/google/nyan/Kconfig | 2 +- src/mainboard/google/nyan_big/Kconfig | 2 +- src/mainboard/google/nyan_blaze/Kconfig | 2 +- src/mainboard/google/oak/Kconfig | 2 +- src/mainboard/google/purin/Kconfig | 4 ---- src/mainboard/google/reef/Kconfig | 4 ---- src/mainboard/google/smaug/Kconfig | 2 +- src/mainboard/google/urara/Kconfig | 2 +- src/mainboard/google/veyron/Kconfig | 2 +- src/mainboard/google/veyron/bootblock.c | 2 +- src/mainboard/google/veyron_brain/Kconfig | 2 +- src/mainboard/google/veyron_brain/bootblock.c | 2 +- src/mainboard/google/veyron_danger/Kconfig | 2 +- src/mainboard/google/veyron_danger/bootblock.c | 2 +- src/mainboard/google/veyron_emile/Kconfig | 2 +- src/mainboard/google/veyron_emile/bootblock.c | 2 +- src/mainboard/google/veyron_mickey/Kconfig | 2 +- src/mainboard/google/veyron_mickey/bootblock.c | 2 +- src/mainboard/google/veyron_rialto/Kconfig | 2 +- src/mainboard/google/veyron_rialto/bootblock.c | 2 +- src/mainboard/google/veyron_romy/Kconfig | 2 +- src/mainboard/google/veyron_romy/bootblock.c | 2 +- src/mainboard/intel/amenia/Kconfig | 4 ---- src/mainboard/intel/kunimitsu/Kconfig | 4 ---- src/soc/mediatek/mt8173/spi.c | 2 +- src/vboot/vbnv_flash.c | 3 ++- 37 files changed, 36 insertions(+), 63 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 54a1fef..c4507bc 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -147,13 +147,6 @@ config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING the SPI contents to RAM before performing the load can speed up the boot process. -config BOOT_MEDIA_SPI_BUS - int - default 0 - depends on SPI_FLASH - help - Most x86 systems which boot from SPI flash boot using bus 0. - config SOC_SETS_MSRS bool default n diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 55b8974..0b7dee3 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -751,7 +751,7 @@ int elog_init(void) elog_debug("elog_init()\n"); /* Probe SPI chip. SPI controller must already be initialized. */ - elog_spi = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0); + elog_spi = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); if (!elog_spi) { printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); return -1; diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 35435a6..ee48d67 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -23,6 +23,13 @@ config SPI_FLASH if SPI_FLASH +# Keep at 0 because lots of boards assume this default. +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 0 + help + Which SPI bus the boot device is connected to. + config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n if COMMON_CBFS_SPI_WRAPPER diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c index 2677ac4..bbe9125 100644 --- a/src/lib/cbfs_spi.c +++ b/src/lib/cbfs_spi.c @@ -59,7 +59,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); void boot_device_init(void) { - int bus = CONFIG_BOOT_MEDIA_SPI_BUS; + int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS; int cs = 0; if (spi_flash_info != NULL) diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig index 6fcdad4..38db373 100644 --- a/src/mainboard/google/chell/Kconfig +++ b/src/mainboard/google/chell/Kconfig @@ -32,10 +32,6 @@ config IRQ_SLOT_COUNT int default 18 -config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "google/chell" diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig index 19d5955..62cd821 100644 --- a/src/mainboard/google/cosmos/Kconfig +++ b/src/mainboard/google/cosmos/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 3de9a4c..8a9e53d 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -60,7 +60,7 @@ config FOSTER_BCT_CFG_EMMC endchoice -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 7 depends on FOSTER_BCT_CFG_SPI diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 83049b7..e70094f 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -32,10 +32,6 @@ config IRQ_SLOT_COUNT int default 18 -config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "google/glados" diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index d5733c8..3150839 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -67,7 +67,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 5 -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 1 diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 8f88043..e80f4a3 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -63,7 +63,7 @@ void bootblock_mainboard_init(void) /* Set pinmux and configure spi flashrom. */ write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); /* Set pinmux and configure EC SPI. */ write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5); diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 1bcb576..2a4973e 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -36,10 +36,6 @@ config IRQ_SLOT_COUNT int default 18 -config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "google/lars" diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index fedf18f..e68ad4e 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -62,7 +62,7 @@ config NYAN_BCT_CFG_EMMC endchoice -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 6 depends on NYAN_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 5c4009a..3f94637 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -63,7 +63,7 @@ config NYAN_BIG_BCT_CFG_EMMC endchoice -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 6 depends on NYAN_BIG_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index a11b3eb..e47ebfa 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -64,7 +64,7 @@ config NYAN_BLAZE_BCT_CFG_EMMC endchoice -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 6 depends on NYAN_BLAZE_BCT_CFG_SPI diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 975cdab..1228cff 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -60,7 +60,7 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 9 diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index d415211..eabab2b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS - int - default 0 - config DRAM_SIZE_MB int default 256 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5fafa8b..b7813b7 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -12,10 +12,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select SYSTEM_TYPE_LAPTOP -config BOOT_MEDIA_SPI_BUS - int - default 0 - config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 000304f..15ff2b3 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -67,7 +67,7 @@ config SMAUG_BCT_CFG_EMMC endchoice -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 7 depends on SMAUG_BCT_CFG_SPI diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 6054a02..e7b9e0e 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -52,7 +52,7 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xB8101500 -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 1 diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index c21cd3f..b6a687c 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -60,7 +60,7 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int default 100 -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index c355410..1f4eec2 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -64,7 +64,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); /* spi0 for chrome ec */ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0); diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index 41a7456..1348f23 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_brain/bootblock.c +++ b/src/mainboard/google/veyron_brain/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index cb1dc71..ab667d8 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -48,7 +48,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_danger/bootblock.c +++ b/src/mainboard/google/veyron_danger/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_emile/Kconfig b/src/mainboard/google/veyron_emile/Kconfig index 059dd1f..d5884f9 100644 --- a/src/mainboard/google/veyron_emile/Kconfig +++ b/src/mainboard/google/veyron_emile/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_emile/bootblock.c b/src/mainboard/google/veyron_emile/bootblock.c index 2fe913e..7261275 100644 --- a/src/mainboard/google/veyron_emile/bootblock.c +++ b/src/mainboard/google/veyron_emile/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 6f489ff..d1a481f 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 9321812..b6d3f65 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index aab05a6..dae046b 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index c151727..e91034e 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google" -config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_romy/bootblock.c +++ b/src/mainboard/google/veyron_romy/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index d4e2c56..9549672 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,10 +14,6 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI -config BOOT_MEDIA_SPI_BUS - int - default 0 - config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 56590da..67143ca 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -35,10 +35,6 @@ config IRQ_SLOT_COUNT int default 18 -config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "intel/kunimitsu" diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index dc674f3..c35b1fc 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -170,7 +170,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) assert(read32(&eslave->regs->spi_cfg0_reg) != 0); spi_sw_reset(eslave->regs); return &eslave->slave; - case CONFIG_BOOT_MEDIA_SPI_BUS: + case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: slave.bus = bus; slave.cs = cs; slave.force_programmer_specific = 1; diff --git a/src/vboot/vbnv_flash.c b/src/vboot/vbnv_flash.c index 8b60be2..717ff23 100644 --- a/src/vboot/vbnv_flash.c +++ b/src/vboot/vbnv_flash.c @@ -136,7 +136,8 @@ static int vbnv_flash_probe(void) struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); if (!ctx->flash) { - ctx->flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0); + ctx->flash = + spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); if (!ctx->flash) { printk(BIOS_ERR, "failed to probe spi flash\n"); return 1;

1 0

Patch set updated for coreboot: vboot/vbnv_flash: make I/O connection agnostic
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16206 -gerrit commit 41eb74ec78798630c3b6183f4c82a3d6d5ea6a2b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:48:58 2016 -0500 vboot/vbnv_flash: make I/O connection agnostic There's no need to be SPI specific w.r.t. how the flash is connected. Therefore, use the RW boot device to write the contents of VBNV. The erasable check was dropped because that information isn't available. All regions should be aligned accordingly on the platform for the underlying hardware implementation. And once the VBNV region fills the erase will fail. BUG=chrome-os-partner:56151 Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vboot/Kconfig | 3 +- src/vboot/vbnv_flash.c | 82 +++++++++----------------------------------------- 2 files changed, 16 insertions(+), 69 deletions(-) diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index a008208..30d322e 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -29,7 +29,7 @@ config VBOOT_VBNV_CMOS config VBOOT_VBNV_CMOS_BACKUP_TO_FLASH bool "Back up Vboot non-volatile storage from CMOS to flash." default n - depends on VBOOT_VBNV_CMOS + depends on VBOOT_VBNV_CMOS && BOOT_DEVICE_SUPPORTS_WRITES help Vboot non-volatile storage data will be backed up from CMOS to flash and restored from flash if the CMOS is invalid due to power loss. @@ -42,6 +42,7 @@ config VBOOT_VBNV_EC config VBOOT_VBNV_FLASH def_bool n + depends on BOOT_DEVICE_SUPPORTS_WRITES help VBNV is stored in flash storage diff --git a/src/vboot/vbnv_flash.c b/src/vboot/vbnv_flash.c index 717ff23..d061228 100644 --- a/src/vboot/vbnv_flash.c +++ b/src/vboot/vbnv_flash.c @@ -17,7 +17,6 @@ #include <assert.h> #include <commonlib/region.h> #include <console/console.h> -#include <spi_flash.h> #include <string.h> #include <vb2_api.h> #include <vboot_nvstorage.h> @@ -31,17 +30,14 @@ struct vbnv_flash_ctx { /* VBNV flash is initialized */ int initialized; - /* Offset of the current nvdata in SPI flash */ + /* Offset of the current nvdata in flash */ int blob_offset; - /* Offset of the topmost nvdata blob in SPI flash */ + /* Offset of the topmost nvdata blob in flash */ int top_offset; - /* SPI flash handler used when saving data */ - struct spi_flash *flash; - - /* FMAP descriptor of the NVRAM area */ - struct region_device region; + /* Region to store and retrieve the VBNV contents. */ + struct region_device vbnv_dev; /* Cache of the current nvdata */ uint8_t cache[BLOB_SIZE]; @@ -66,13 +62,14 @@ static inline int can_overwrite(uint8_t current, uint8_t new) static int init_vbnv(void) { struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + struct region_device *rdev = &ctx->vbnv_dev; uint8_t buf[BLOB_SIZE]; uint8_t empty_blob[BLOB_SIZE]; int offset; int i; - if (vboot_named_region_device("RW_NVRAM", &ctx->region) || - region_device_sz(&ctx->region) < BLOB_SIZE) { + if (vboot_named_region_device_rw("RW_NVRAM", rdev) || + region_device_sz(rdev) < BLOB_SIZE) { printk(BIOS_ERR, "%s: failed to locate NVRAM\n", __func__); return 1; } @@ -82,7 +79,7 @@ static int init_vbnv(void) empty_blob[i] = erase_value(); offset = 0; - ctx->top_offset = region_device_sz(&ctx->region) - BLOB_SIZE; + ctx->top_offset = region_device_sz(rdev) - BLOB_SIZE; /* * after the loop, offset is supposed to point the blob right before @@ -91,7 +88,7 @@ static int init_vbnv(void) * used. */ for (i = 0; i <= ctx->top_offset; i += BLOB_SIZE) { - if (rdev_readat(&ctx->region, buf, i, BLOB_SIZE) < 0) { + if (rdev_readat(rdev, buf, i, BLOB_SIZE) < 0) { printk(BIOS_ERR, "failed to read nvdata\n"); return 1; } @@ -101,7 +98,7 @@ static int init_vbnv(void) } /* reread the nvdata and write it to the cache */ - if (rdev_readat(&ctx->region, ctx->cache, offset, BLOB_SIZE) < 0) { + if (rdev_readat(rdev, ctx->cache, offset, BLOB_SIZE) < 0) { printk(BIOS_ERR, "failed to read nvdata\n"); return 1; } @@ -112,61 +109,12 @@ static int init_vbnv(void) return 0; } -static void vbnv_is_erasable(void) -{ - /* - * We check whether the region is aligned or not in advance to ensure - * we can erase the region when it's all used up. - * - * The region offset & size are determined by fmap.dts yet the check can - * be confidently done only by the spi flash driver. We use the same - * check as the one used by spi_flash_cmd_erase, which happens to be - * common to all the spi flash parts we support. - * - * TODO: Check by calling can_erase implemented by each spi flash driver - */ - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); - - assert(!(region_device_offset(&ctx->region) % ctx->flash->sector_size)); - assert(!(region_device_sz(&ctx->region) % ctx->flash->sector_size)); -} - -static int vbnv_flash_probe(void) -{ - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); - - if (!ctx->flash) { - ctx->flash = - spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); - if (!ctx->flash) { - printk(BIOS_ERR, "failed to probe spi flash\n"); - return 1; - } - /* - * Called here instead of init_vbnv to reduce impact on boot - * speed. - */ - vbnv_is_erasable(); - } - - /* - * Handle the case where spi_flash_probe returns a CAR_GLOBAL - * in early execution on x86 but then later is moved to RAM. - */ - ctx->flash = car_get_var_ptr(ctx->flash); - - return 0; -} - static int erase_nvram(void) { struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + const struct region_device *rdev = &ctx->vbnv_dev; - if (vbnv_flash_probe()) - return 1; - - if (ctx->flash->erase(ctx->flash, region_device_offset(&ctx->region), - region_device_sz(&ctx->region))) { + if (rdev_eraseat(rdev, 0, region_device_sz(rdev)) < 0) { printk(BIOS_ERR, "failed to erase nvram\n"); return 1; } @@ -191,6 +139,7 @@ void save_vbnv_flash(const uint8_t *vbnv_copy) struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); int new_offset; int i; + const struct region_device *rdev = &ctx->vbnv_dev; if (!ctx->initialized) if (init_vbnv()) @@ -216,10 +165,7 @@ void save_vbnv_flash(const uint8_t *vbnv_copy) } } - if (!vbnv_flash_probe() && - !ctx->flash->write(ctx->flash, - region_device_offset(&ctx->region) + new_offset, - BLOB_SIZE, vbnv_copy)) { + if (rdev_writeat(rdev, vbnv_copy, new_offset, BLOB_SIZE) < 0) { /* write was successful. safely move pointer forward */ ctx->blob_offset = new_offset; memcpy(ctx->cache, vbnv_copy, BLOB_SIZE);

1 0

Patch set updated for coreboot: drivers/elog: use region_device for NV storage
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16204 -gerrit commit e2b74ce2f3ba429e1b3b54b0c4e5955cd0beaf53 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 10 11:37:14 2016 -0500 drivers/elog: use region_device for NV storage Instead of assuming SPI backing use a region_device to abstract away the underlying storage mechanism. BUG=chrome-os-partner:55932 Change-Id: I6b0f5a7e9bea8833fb1bca87e02abefab63acec3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/elog/Kconfig | 4 +- src/drivers/elog/elog.c | 98 +++++++++++++++++----------------- src/vendorcode/google/chromeos/Kconfig | 2 +- 3 files changed, 51 insertions(+), 53 deletions(-) diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index cb5d3d4..c7bed75 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -14,9 +14,9 @@ ## config ELOG - depends on SPI_FLASH bool "Support for flash based event log" default n + depends on BOOT_DEVICE_SUPPORTS_WRITES help Enable support for flash based event logging. @@ -39,7 +39,7 @@ config ELOG_CBMEM endif config ELOG_GSMI - depends on ELOG && SPI_FLASH_SMM && SMM_TSEG + depends on ELOG && SMM_TSEG bool "SMI interface to write and clear event log" default n help diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 3d8c85c8..0f72e7c 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -29,8 +29,6 @@ #include <lib.h> #include <rtc.h> #include <smbios.h> -#include <spi-generic.h> -#include <spi_flash.h> #include <stdint.h> #include <string.h> #include <elog.h> @@ -47,8 +45,6 @@ /* * Static variables for ELOG state */ -static u16 total_size; -static u32 flash_base; static u16 full_threshold; static u16 shrink_size; @@ -60,7 +56,7 @@ static u16 shrink_size; static size_t mirror_last_write; static size_t nv_last_write; -static struct spi_flash *elog_spi; +static struct region_device nv_dev; /* Device that mirrors the eventlog in memory. */ static struct mem_region_device mirror_dev; @@ -83,7 +79,7 @@ static size_t elog_events_start(void) static size_t elog_events_total_space(void) { - return total_size - elog_events_start(); + return region_device_sz(&nv_dev) - elog_events_start(); } static struct event_header *elog_get_event_buffer(size_t offset, size_t size) @@ -187,7 +183,7 @@ static void elog_debug_dump_buffer(const char *msg) if (buffer == NULL) return; - hexdump(buffer, total_size); + hexdump(buffer, region_device_sz(rdev)); rdev_munmap(rdev, buffer); } @@ -318,27 +314,26 @@ static size_t elog_is_event_valid(size_t offset) * the flash backing store. This will not erase the flash and it assumes the * flash area has been erased appropriately. */ -static void elog_flash_write(size_t offset, size_t size) +static void elog_nv_write(size_t offset, size_t size) { void *address; const struct region_device *rdev = mirror_dev_get(); - if (!size || !elog_spi) + if (!size) return; address = rdev_mmap(rdev, offset, size); - /* Ensure offset is absolute. */ - offset += flash_base; - - elog_debug("elog_flash_write(address=0x%p offset=0x%08x size=%u)\n", + elog_debug("%s(address=0x%p offset=0x%08x size=%u)\n", __func__, address, offset, size); if (address == NULL) return; /* Write the data to flash */ - elog_spi->write(elog_spi, offset, size, address); + if (rdev_writeat(&nv_dev, address, offset, size) != size) + printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n", + offset, size); rdev_munmap(rdev, address); } @@ -347,16 +342,14 @@ static void elog_flash_write(size_t offset, size_t size) * Erase the first block specified in the address. * Only handles flash area within a single flash block. */ -static void elog_flash_erase(void) +static void elog_nv_erase(void) { - if (!elog_spi) - return; - - elog_debug("elog_flash_erase(offset=0x%08x size=%u)\n", - flash_base, total_size); + size_t size = region_device_sz(&nv_dev); + elog_debug("%s()\n", __func__); /* Erase the sectors in this region */ - elog_spi->erase(elog_spi, flash_base, total_size); + if (rdev_eraseat(&nv_dev, 0, size) != size) + printk(BIOS_ERR, "ELOG: erase failure.\n"); } /* @@ -413,10 +406,15 @@ static int elog_scan_flash(void) elog_debug("elog_scan_flash()\n"); void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); + size_t size = region_device_sz(&nv_dev); /* Fill memory buffer by reading from SPI */ mirror_buffer = rdev_mmap_full(rdev); - elog_spi->read(elog_spi, flash_base, total_size, mirror_buffer); + if (rdev_readat(&nv_dev, mirror_buffer, 0, size) != size) { + rdev_munmap(rdev, mirror_buffer); + printk(BIOS_ERR, "ELOG: NV read failure.\n"); + return -1; + } rdev_munmap(rdev, mirror_buffer); /* No writes have been done yet. */ @@ -590,10 +588,12 @@ static inline u8 *elog_flash_offset_to_address(void) if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) return NULL; - if (!elog_spi) + if (!region_device_sz(&nv_dev)) return NULL; - return rdev_mmap(boot_device_ro(), flash_base, total_size); + /* Get a view into the read-only boot device. */ + return rdev_mmap(boot_device_ro(), region_device_offset(&nv_dev), + region_device_sz(&nv_dev)); } /* @@ -605,12 +605,13 @@ int elog_smbios_write_type15(unsigned long *current, int handle) struct smbios_type15 *t = (struct smbios_type15 *)*current; int len = sizeof(struct smbios_type15); uintptr_t log_address; + size_t elog_size = region_device_sz(&nv_dev); if (IS_ENABLED(CONFIG_ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ - void *cbmem = cbmem_add(CBMEM_ID_ELOG, total_size); + void *cbmem = cbmem_add(CBMEM_ID_ELOG, elog_size); if (cbmem) - rdev_readat(mirror_dev_get(), cbmem, 0, total_size); + rdev_readat(mirror_dev_get(), cbmem, 0, elog_size); log_address = (uintptr_t)cbmem; } else { log_address = (uintptr_t)elog_flash_offset_to_address(); @@ -625,7 +626,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle) t->type = SMBIOS_EVENT_LOG; t->length = len - 2; t->handle = handle; - t->area_length = total_size - 1; + t->area_length = elog_size - 1; t->header_offset = 0; t->data_offset = sizeof(struct elog_header); t->access_method = SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32; @@ -656,26 +657,30 @@ int elog_clear(void) static int elog_find_flash(void) { - struct region r; + size_t total_size; size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE; + struct region_device *rdev = &nv_dev; - elog_debug("elog_find_flash()\n"); + elog_debug("%s()\n", __func__); /* Find the ELOG base and size in FMAP */ - if (fmap_locate_area("RW_ELOG", &r) < 0) { + if (fmap_locate_area_as_rdev_rw("RW_ELOG", rdev) < 0) { printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP\n"); return -1; } - if (region_sz(&r) < 4*KiB) { + if (region_device_sz(rdev) < 4*KiB) { printk(BIOS_WARNING, "ELOG: Needs a minium size of 4KiB: %zu\n", - region_sz(&r)); + region_device_sz(rdev)); return -1; } - flash_base = region_offset(&r); + printk(BIOS_INFO, "ELOG: NV offset 0x%zx size 0x%zx\n", + region_device_offset(rdev), region_device_sz(rdev)); + /* Keep 4KiB max size until large malloc()s have been fixed. */ - total_size = MIN(4*KiB, region_sz(&r)); + total_size = MIN(4*KiB, region_device_sz(rdev)); + rdev_chain(rdev, rdev, 0, total_size); full_threshold = total_size - reserved_space; shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; @@ -702,13 +707,13 @@ static int elog_sync_to_nv(void) /* Erase if necessary. */ if (erase_needed) { - elog_flash_erase(); + elog_nv_erase(); elog_nv_reset_last_write(); } size = elog_nv_region_to_update(&offset); - elog_flash_write(offset, size); + elog_nv_write(offset, size); elog_nv_increment_last_write(size); /* @@ -737,6 +742,7 @@ static int elog_sync_to_nv(void) int elog_init(void) { void *mirror_buffer; + size_t elog_size; switch (elog_initialized) { case ELOG_UNINITIALIZED: @@ -750,23 +756,17 @@ int elog_init(void) elog_debug("elog_init()\n"); - /* Probe SPI chip. SPI controller must already be initialized. */ - elog_spi = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); - if (!elog_spi) { - printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); - return -1; - } - /* Set up the backing store */ if (elog_find_flash() < 0) return -1; - mirror_buffer = malloc(total_size); + elog_size = region_device_sz(&nv_dev); + mirror_buffer = malloc(elog_size); if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; } - mem_region_device_rw_init(&mirror_dev, mirror_buffer, total_size); + mem_region_device_rw_init(&mirror_dev, mirror_buffer, elog_size); /* * Mark as initialized to allow elog_init() to be called and deemed @@ -780,11 +780,9 @@ int elog_init(void) return -1; } - printk(BIOS_INFO, "ELOG: FLASH @0x%p [SPI 0x%08x]\n", - mirror_buffer, flash_base); - - printk(BIOS_INFO, "ELOG: area is %d bytes, full threshold %d," - " shrink size %d\n", total_size, full_threshold, shrink_size); + printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d," + " shrink size %d\n", region_device_sz(&nv_dev), + full_threshold, shrink_size); #if !defined(__SMM__) /* Log boot count event except in S3 resume */ diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 5134731..684a18f 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -25,7 +25,7 @@ config CHROMEOS select TPM2 if MAINBOARD_HAS_TPM2 select TPM_INIT_FAILURE_IS_FATAL if PC80_SYSTEM && LPC_TPM select SKIP_TPM_STARTUP_ON_NORMAL_BOOT if PC80_SYSTEM && LPC_TPM - select ELOG if SPI_FLASH + select ELOG if BOOT_DEVICE_SUPPORTS_WRITES select COLLECT_TIMESTAMPS select VBOOT help

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Patch set updated for coreboot: vboot: provide RW region device support
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16205 -gerrit commit 49520a60dd6be60e8ad9a0cf34f35d0623f7ac1f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:46:07 2016 -0500 vboot: provide RW region device support Explicitly provide a RW view of an vboot FMAP region. This is required for platforms which have separate implementations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: If8bf2e1c7ca9bff536fc5c578fe0cf92ccbd2ebc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vboot/vboot_common.c | 5 +++++ src/vboot/vboot_common.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/vboot/vboot_common.c b/src/vboot/vboot_common.c index 319e0de..7e1ca9d 100644 --- a/src/vboot/vboot_common.c +++ b/src/vboot/vboot_common.c @@ -30,6 +30,11 @@ int vboot_named_region_device(const char *name, struct region_device *rdev) return fmap_locate_area_as_rdev(name, rdev); } +int vboot_named_region_device_rw(const char *name, struct region_device *rdev) +{ + return fmap_locate_area_as_rdev(name, rdev); +} + /* ========================== VBOOT HANDOFF APIs =========================== */ int vboot_get_handoff_info(void **addr, uint32_t *size) { diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index d64b5bb..59fd44c 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -23,6 +23,9 @@ /* Locate vboot area by name. Returns 0 on success and -1 on error. */ int vboot_named_region_device(const char *name, struct region_device *rdev); +/* Like vboot_named_region_device() but provides a RW region device. */ +int vboot_named_region_device_rw(const char *name, struct region_device *rdev); + /* * Function to check if there is a request to enter recovery mode. Returns * reason code if request to enter recovery mode is present, otherwise 0.

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Patch set updated for coreboot: soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16202 -gerrit commit eec4c8e19cf0cc08d2d8c7363d172d6ec9ad7da7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 23:55:39 2016 -0500 soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages If the boot device is SPI flash use use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 909dcec..f13c84e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE @@ -46,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP - select SPI_FLASH select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE

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Patch set updated for coreboot: lib/fmap: provide RW region device support
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16203 -gerrit commit 9eb4d7fccf167f67af6dcfd82224fd2dfa3ccc2d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 12 12:42:04 2016 -0500 lib/fmap: provide RW region device support Explicitly provide a RW view of an FMAP region. This is required for platforms which have separeate implemenations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: Ibafa3dc534f53a3d90487f3190c0f8a2e82858c2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/fmap.h | 4 ++++ src/lib/fmap.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/src/include/fmap.h b/src/include/fmap.h index 684a05c..5834831 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -27,6 +27,10 @@ int find_fmap_directory(struct region_device *fmrd); * 0 on success, < 0 on error. */ int fmap_locate_area_as_rdev(const char *name, struct region_device *area); +/* Just like fmap_locate_area_as_rdev(), however the region device is + * created from the RW boot device. */ +int fmap_locate_area_as_rdev_rw(const char *name, struct region_device *area); + /* Locate the named area in the fmap and fill in a region with the * offset and size of that area within the boot media. Return 0 on success, * < 0 on error. */ diff --git a/src/lib/fmap.c b/src/lib/fmap.c index bf99037..9602134 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -80,6 +80,16 @@ int fmap_locate_area_as_rdev(const char *name, struct region_device *area) return boot_device_ro_subregion(&ar, area); } +int fmap_locate_area_as_rdev_rw(const char *name, struct region_device *area) +{ + struct region ar; + + if (fmap_locate_area(name, &ar)) + return -1; + + return boot_device_rw_subregion(&ar, area); +} + int fmap_locate_area(const char *name, struct region *ar) { struct region_device fmrd;

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Patch set updated for coreboot: Kconfig: lay groundwork for not assuming SPI flash boot device
by Aaron Durbin 15 Aug '16

15 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16191 -gerrit commit 8fe3375b3fc977a99eaae412d0ae89aec59fa110 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 11 11:02:26 2016 -0500 Kconfig: lay groundwork for not assuming SPI flash boot device Almost all boards and chipsets within the codebase assume or use SPI flash as the boot device. Therefore, provide an option for the boards/chipsets which don't currently support SPI flash as the boot device. The default is to assume SPI flash is the boot device unless otherwise instructed. This falls in line with the current assumptions, but it also allows one to differentiate a platform desiring SPI flash support while it not being the actual boot device. One thing to note is that while google/daisy does boot with SPI flash part no SPI API interfaces were ever implemented. Therefore, mark that board as not having a SPI boot device. BUG=chrome-os-partner:56151 Change-Id: Id4e0b4ec5e440e41421fbb6d0ca2be4185b62a6e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 12 ++++++++++++ src/cpu/allwinner/a10/Kconfig | 1 + src/cpu/ti/am335x/Kconfig | 1 + src/drivers/spi/Kconfig | 1 + src/mainboard/emulation/qemu-armv7/Kconfig | 1 + src/mainboard/emulation/qemu-power8/Kconfig | 1 + src/mainboard/emulation/qemu-riscv/Kconfig | 1 + src/mainboard/emulation/spike-riscv/Kconfig | 1 + src/mainboard/google/daisy/Kconfig | 1 + 9 files changed, 20 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 3af2769..04b8d24 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -471,6 +471,18 @@ endmenu source "src/acpi/Kconfig" +# This option is for the current boards/chipsets where SPI flash +# is not the boot device. Currently nearly all boards/chipsets assume +# SPI flash is the boot device. +config BOOT_DEVICE_NOT_SPI_FLASH + bool + default n + +config BOOT_DEVICE_SPI_FLASH + bool + default y if !BOOT_DEVICE_NOT_SPI_FLASH + default n + config RTC bool default n diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 0e5aba9..6451b4a 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -14,5 +14,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select UART_OVERRIDE_REFCLK + select BOOT_DEVICE_NOT_SPI_FLASH endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index f44c69d..939bca7 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -8,5 +8,6 @@ config CPU_TI_AM335X select BOOTBLOCK_CONSOLE select GENERIC_UDELAY select UART_OVERRIDE_REFCLK + select BOOT_DEVICE_NOT_SPI_FLASH bool default n diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 194e61f..35435a6 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -15,6 +15,7 @@ config SPI_FLASH bool + default y if BOOT_DEVICE_SPI_FLASH default n help Select this option if your chipset driver needs to store certain diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 2654f0f..e801ae3 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 + select BOOT_DEVICE_NOT_SPI_FLASH config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index 7946c3e..6adcf72 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_BOOTBLOCK_POWER8 select HAVE_UART_SPECIAL select ARCH_POWER8 + select BOOT_DEVICE_NOT_SPI_FLASH config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 37d787a..cd11f95 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select ARCH_BOOTBLOCK_RISCV select HAVE_UART_SPECIAL + select BOOT_DEVICE_NOT_SPI_FLASH config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index a762220..574f23c 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select ARCH_BOOTBLOCK_RISCV select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH config MAINBOARD_DIR string diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 9f6a615..cef3f61 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -17,6 +17,7 @@ if BOARD_GOOGLE_DAISY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select BOOT_DEVICE_NOT_SPI_FLASH select CPU_SAMSUNG_EXYNOS5250 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C

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coreboot-gerrit August 2016