coreboot-gerrit May 2016

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Patch set updated for filo: fs: Don't reimplement log2
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14374 -gerrit commit a9912562e6c2c2e08f6fad0f079221b79ecb99cf Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 18:04:29 2016 -0700 fs: Don't reimplement log2 libpayload already provides an implementation, that is available for all platforms. Use that one instead of this incomplete version. Change-Id: Idcfc09ddc008ccb2eeb46081e25c2b7c1c1cce15 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- fs/filesys.h | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/fs/filesys.h b/fs/filesys.h index 168413b..2fe61a4 100644 --- a/fs/filesys.h +++ b/fs/filesys.h @@ -23,38 +23,6 @@ #include <config.h> #include <fs.h> -#if defined(__i386__) -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz (unsigned long word) -{ - __asm__ ("bsfl %1,%0" - : "=r" (word) - : "r" (~word)); - return word; -} -#elif defined(__ppc__) -static inline unsigned long __ilog2(unsigned long x) -{ - unsigned long lz; - asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); - return 31 - lz; -} - -static inline unsigned long ffz(unsigned long x) -{ - if ((x = ~x) == 0) - return 32; - - return __ilog2(x & -x); -} -#endif - -#define log2(n) ffz(~(n)) - - static inline int substring (const char *s1, const char *s2) {

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Patch set updated for coreboot: utils: introduce find_usbdebug.sh to help find USB debug ports
by Stefan Tauner 02 May '16

02 May '16

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/9305 -gerrit commit 7b88baa66f7d0bf0c75872dee1a2fe59e6fb3040 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon May 2 23:16:57 2016 +0200 utils: introduce find_usbdebug.sh to help find USB debug ports Carl-Daniel made this script a long time ago but it never was picked up in the tree. Now that USB debugging is way more common it makes sense to include it. I have made a number of changes to the original version: * -h help text * check for running as root * enhanced readability (test -> if) * new execution flow and refined output that better shows the device(s) attached to the debug port(s) * handling of Intel rate-matching hubs * hiding of (bogus) error messages from lspci and lsusb Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Change-Id: Iadf775e990f5c5f91a28d57e3331d1f59acee305 --- util/find_usbdebug/find_usbdebug.sh | 169 ++++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh new file mode 100755 index 0000000..30bf86f --- /dev/null +++ b/util/find_usbdebug/find_usbdebug.sh @@ -0,0 +1,169 @@ +#!/bin/bash + +# Copyright 2008 Carl-Daniel Hailfinger +# Copyright 2015 Stefan Tauner +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +LANG=C +# Some tools emmit errors that don't matter (bugs in lspci/PCI firmware and lsusb). +# To shown them anyway (e.g. for debugging) comment next line. +exec 2>/dev/null + +if [ "$1" = "-h" ]; then + printf "Usage: $0 [-h | path to dmesg log] + +This script tries to find USB ports compatible with USB2/EHCI debug devices and +helps you to find their physical locations. To that end, attach at least one +uniquely identifiable device to a USB port and run this script. The device needs +to be visible in the output of \"lsusb -t\" (debug devices are often *not*!). + +After determining compatibility of the USB controllers the script will print the +devices attached to the debug port as shown by lsusb. If nothing shows up simply +switch ports and repeat the process. + +Note: usually only one port is supported for debugging.\n" + exit 0 +fi +uid=`id -u` +if [ "$uid" -ne 0 ]; then + echo "Must be run as root. Exiting." + exit 1 +fi +dmesgfile=$1 + +find_devs_in_tree () { + bus=$1 + port=$2 + busstr=`printf "Bus %02d" "$bus"` + portstr="Port $port" + + hubs_to_ignore="8087:0020 8087:0024" + reqlvl=1 + + found= + # Iterate over the output of lsusb -t because it contains the physical port numbers + while IFS='' read -r line; do + # We need to keep track of the current bus "branch" + # Look out for lines starting with /: (that indicate a bus) + if [ "${line#*/:}" != "$line" ]; then + if [ "${line#*$busstr}" != "$line" ]; then + cur_bus=$busstr + else + cur_bus= + fi + continue + fi + + # Skip all lines not belonging to the wanted bus number + if [ "$cur_bus" != "$busstr" ]; then + continue + fi + + # Calculate current USB tier/level + spaces="${line%%[!' ']*}" + curlvl=$((${#spaces} / 4)) + if [ $curlvl -ne $reqlvl ]; then + continue + fi + + # Fetch USB IDs of the current device + dev=`echo ${line#*Dev } | cut -d ',' -f 1` + lsusbline=`lsusb -s "$bus":"$dev"` + if [[ ! "$lsusbline" =~ .*([[:xdigit:]]{4}:[[:xdigit:]]{4}) ]]; then + printf "Unexpected output from \"%s\": \"%s\"\n" "lsusb -s $bus:$dev" "$usbline" + exit 1 + fi + ids=${BASH_REMATCH[1]} + + # Skip over rate matching hubs + if [[ "$hubs_to_ignore" == *"$ids"* ]]; then + ((reqlvl += 1)) + continue + fi + + # Check for matching physical USB port + if [ "${line#*$portstr}" != "$line" ]; then + echo "$lsusbline" + return + fi + done<< EOF +$(lsusb -t) +EOF + if [ -z "$found" ]; then + echo "none" + fi +} + +debug_lspci_devs=`lspci -nvvD | + grep -i "^[0-9a-f]\|debug port" | + grep -iB1 --no-group-separator "debug port" | + grep -vi "debug port" | + cut -f 1 -d" " | + sort | + xargs echo` + +if [ -z "$debug_lspci_devs" ]; then + printf "No USB controller with debug capability found by lspci.\n +Possible reasons: lspci too old, USB controller does not support a debug device, ... Exiting.\n" + exit 1 +fi +printf "The following PCI devices support a USB debug port (says lspci): $debug_lspci_devs\n" + +debug_dmesg_devs_with_port=`( test -z "$dmesgfile" && + dmesg || + cat "$dmesgfile") | + grep -i "ehci.*debug port" | + sed "s/.* $[0-9a-f]*:*[0-9a-f]\{2\}:[0-9a-f]\{2\}\.[0-9a-f]$.*ebug port /\1 /" | + sort` + +debug_dmesg_devs=`echo "$debug_dmesg_devs_with_port" | + cut -f 1 -d" " | + xargs echo` + +if [ -z "$debug_dmesg_devs" ]; then + printf "dmesg does not show any supported ports.\n +Possible reasons: dmesg scrolled off, kernel too old, USB controller does not support a debug device, ... Exiting.\n +Note: You can specify a file containing kernel messages as an argument to this program (e.g. /var/log/dmesg)." + exit 1 +fi + +if [ "$debug_lspci_devs" != "$debug_dmesg_devs" ]; then + echo "lspci and the kernel do not agree on USB debug device support. Exiting." + exit 1 +fi + +printf "and the kernel agrees, good.\n\n" + +while true; do + for dev in $debug_dmesg_devs; do + bus=`lsusb -v | + grep "^Bus\|iSerial.*" | + grep -B1 --no-group-separator "iSerial.*$dev" | + grep "^Bus" | + sed "s/Bus *0*$[0-9a-f]*$.*/\1/"` + port=`echo "$debug_dmesg_devs_with_port" | + grep "^$dev" | + cut -f 2 -d" "` + + echo "Device(s) currently connected to the debug-capable port $port on PCI device $dev, USB bus $bus:" + + find_devs_in_tree "$bus" "$port" + echo + done + + echo "Enter 'q' to abort or anything else to repeat" + read -r r + if [ $? -ne 0 -o "$r" = "q" ]; then + break; + fi +done + +exit 0

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Patch set updated for coreboot: soc/apollolake: Set BootMode based on previous sleep state
by Ravishankar Sarawadi 02 May '16

02 May '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14550 -gerrit commit fb7f6f13b9ad03c52d5055511af919039ad69cef Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 15:20:14 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 70 +++++++++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..22f2fb2 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,28 +16,34 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <arch/cpu.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <arch/symbols.h> +#include <assert.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <device/pci_def.h> +#include <device/resource.h> #include <fsp/api.h> #include <fsp/util.h> -#include <device/resource.h> -#include <string.h> -#include <soc/iomap.h> +#include <reset.h> +#include <romstage_handoff.h> #include <soc/intel/common/mrc_cache.h> -#include <soc/pci_devs.h> +#include <soc/iomap.h> #include <soc/northbridge.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <string.h> #define FIT_POINTER (0x100000000ULL - 0x40) +static struct chipset_power_state power_state CAR_GLOBAL; + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -77,6 +83,22 @@ static void disable_watchdog(void) outl(reg, ACPI_PMIO_BASE + 0x68); } +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); + asmlinkage void car_stage_entry(void) { void *hob_list_ptr, *mrc_data; @@ -84,6 +106,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; + int prev_sleep_state; + struct romstage_handoff *handoff; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -91,6 +116,8 @@ asmlinkage void car_stage_entry(void) disable_watchdog(); + prev_sleep_state = fill_power_state(ps); + /* Make sure the blob does not override our data in CAR */ range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); @@ -102,8 +129,17 @@ asmlinkage void car_stage_entry(void) fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ - cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, - range_entry_size(&fsp_mem)); + if (prev_sleep_state != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem)); + } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem))) { + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); + } + } /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != @@ -114,7 +150,8 @@ asmlinkage void car_stage_entry(void) fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ - if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && + (prev_sleep_state != SLEEP_STATE_S3)) { /* TODO: treat MRC data as const */ mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); @@ -122,6 +159,13 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to stash MRC data\n"); } + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -157,6 +201,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + int prev_sleep_state = chipset_prev_sleep_state(ps); fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -185,8 +231,12 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; - printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + arch_upd->Bootmode = + prev_sleep_state == SLEEP_STATE_S3 ? + FSP_BOOT_ON_S3_RESUME: + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", + mrc_cache->size, arch_upd->Bootmode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); }

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Patch set updated for coreboot: soc/apollolake/romstage: Do not cast const to non-const pointers
by Alexandru Gagniuc 02 May '16

02 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14574 -gerrit commit 478fa3850956111f68bbad48c74984be0f8a8315 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon May 2 13:40:15 2016 -0700 soc/apollolake/romstage: Do not cast const to non-const pointers That was a workaround for the MRC cache API, which has since been reworked. The workaround is no longer needed. Change-Id: I1c1883f3ea37245615248459cd993ed774bf92de Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..42af6c0 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -79,7 +79,8 @@ static void disable_watchdog(void) asmlinkage void car_stage_entry(void) { - void *hob_list_ptr, *mrc_data; + void *hob_list_ptr; + const void *mrc_data; struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; @@ -116,8 +117,7 @@ asmlinkage void car_stage_entry(void) /* Save MRC Data to CBMEM */ if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { - /* TODO: treat MRC data as const */ - mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); + mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); }

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New patch to review for coreboot: soc/apollolake/romstage: Do not cast const to non-const pointers
by Alexandru Gagniuc 02 May '16

02 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14574 -gerrit commit 695028a101f93bb4c0fde31e1557a85d352acf3f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon May 2 13:40:15 2016 -0700 soc/apollolake/romstage: Do not cast const to non-const pointers That was a workaround for the MRC cache API, which has since been reworked. The workaround is no longer needed. Change-Id: I1c1883f3ea37245615248459cd993ed774bf92de Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..62c5787 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -79,7 +79,8 @@ static void disable_watchdog(void) asmlinkage void car_stage_entry(void) { - void *hob_list_ptr, *mrc_data; + void *hob_list_ptr; + const void *mrc_data; struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; @@ -117,7 +118,7 @@ asmlinkage void car_stage_entry(void) if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { /* TODO: treat MRC data as const */ - mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); + mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); }

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Patch set updated for coreboot: board_status: Allow for parsing longopts
by David Hendricks 02 May '16

02 May '16

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14523 -gerrit commit 40a303ab68b802c5acd3bbe9b55d953ae4e305c6 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 26 14:07:42 2016 -0700 board_status: Allow for parsing longopts This converts the argument parsing to allow us to add longopts using GNU getopt(1). Shortopts should be reserved for general parameters. Longopts can be used to tweak specific behaviors. For example, we might wish to add options to set SSH port, timeout, and authentication parameters with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc. This is virtually untested, it would be nice if someone else can hijack this patch to test and clean it up where necessary. Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/board_status/board_status.sh | 48 ++++++++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index b315be1..6106589 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -188,31 +188,53 @@ Options " } -while getopts "Chi:r:s:S:u" opt; do - case "$opt" in - h) +getopt -T +if [ $? -ne 4 ]; then + echo "GNU-compatible getopt(1) required." + exit $EXIT_FAILURE +fi + +# TODO: add longopts in the quotes after -l +ARGS=$(getopt -o Chi:r:s:S:u -l "" -n "$0" -- "$@"); +if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi +eval set -- "$ARGS" +while true ; do + case "$1" in + -h) show_help exit $EXIT_SUCCESS ;; - C) + -C) CLOBBER_OUTPUT=1 ;; - i) - COREBOOT_IMAGE="$OPTARG" + -i) + shift + COREBOOT_IMAGE="$1" ;; - r) - REMOTE_HOST="$OPTARG" + -r) + shift + REMOTE_HOST="$1" ;; - s) - SERIAL_DEVICE="$OPTARG" + -s) + shift + SERIAL_DEVICE="$1" ;; - S) - SERIAL_PORT_SPEED="$OPTARG" + -S) + shift + SERIAL_PORT_SPEED="$1" ;; - u) + -u) UPLOAD_RESULTS=1 ;; + --) + shift + break + ;; + *) + echo "error processing options at '$1'" + exit $EXIT_FAILURE esac + shift done grep -rH 'coreboot.org' .git/config >/dev/null 2>&1

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Patch set updated for coreboot: vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h
by Leroy P Leahy 02 May '16

02 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14452 -gerrit commit 7c9d434ba1403c632ab71add18620d90b2ebb9af Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Mar 11 07:55:55 2016 -0800 vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h Update the file to match the QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: I090578d32165d34863548aec0e4a38fe915683c6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 62 ++++++++++------------- 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h index b6b6cc4..ef0cf09 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -36,18 +36,20 @@ are permitted provided that the following conditions are met: #pragma pack(1) -// -// TODO - Port to fit Quark SoC. -// +/** TODO - Port to fit Quark SoC. +**/ -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 +#define MAX_CHANNELS_NUM 1 +#define MAX_DIMMS_NUM 1 typedef struct { UINT8 DimmId; UINT32 SizeInMb; UINT16 MfgId; - UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ + /** Module part number for DDR3 is 18 bytes however for + DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + **/ + UINT8 ModulePartNum[20]; } DIMM_INFO; typedef struct { @@ -80,33 +82,34 @@ typedef struct { UINT64 Signature; /** Offset 0x0028 **/ - UINT8 Revision; -/** Offset 0x0029 - Tseg Size - Size of SMRAM memory reserved. + UINT64 Revision; +/** Offset 0x0030 **/ - UINT8 PcdSmmTsegSize; -/** Offset 0x002A + UINT32 PcdRmuBinaryBaseAddress; +/** Offset 0x0034 **/ - UINT32 PcdPlatformDataBaseAddress; -/** Offset 0x002E + UINT32 PcdRmuBinaryLen; +/** Offset 0x0038 **/ - UINT32 PcdPlatformDataMaxLen; -/** Offset 0x0032 + UINT8 PcdSmmTsegSize; +/** Offset 0x0039 **/ - UINT8 ReservedMemoryInitUpd[14]; + UINT8 PcdPlatformType; +/** Offset 0x003A +**/ + UINT8 ReservedMemoryInitUpd[22]; } MEMORY_INIT_UPD; typedef struct { -/** Offset 0x0040 +/** Offset 0x0050 **/ UINT64 Signature; -/** Offset 0x0048 +/** Offset 0x0058 **/ - UINT8 Revision; -/** Offset 0x0049 + UINT64 Revision; +/** Offset 0x0060 **/ - UINT8 ReservedSiliconInitUpd[183]; + UINT8 ReservedSiliconInitUpd[32]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ @@ -119,10 +122,7 @@ typedef struct _UPD_DATA_REGION { UINT64 Signature; /** Offset 0x0008 **/ - UINT8 Revision; -/** Offset 0x0009 -**/ - UINT8 ReservedUpd0[7]; + UINT64 Revision; /** Offset 0x0010 **/ UINT32 MemoryInitUpdOffset; @@ -135,10 +135,10 @@ typedef struct _UPD_DATA_REGION { /** Offset 0x0020 **/ MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0040 +/** Offset 0x0050 **/ SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0100 +/** Offset 0x0080 **/ UINT16 PcdRegionTerminator; } UPD_DATA_REGION; @@ -157,12 +157,6 @@ typedef struct _VPD_DATA_REGION { /** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[16]; -/** Offset 0x0020 -**/ - UINT32 PcdFspReservedMemoryLength; } VPD_DATA_REGION; #pragma pack()

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Patch set updated for filo: Point to the correct libpayload path
by Stefan Reinauer 02 May '16

02 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14355 -gerrit commit c3d7e519ea853397c9caa65892f46bb64da57ca3 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 13 16:23:48 2016 -0700 Point to the correct libpayload path libpayload is not standalone, so assume it lives under coreboot to make out of the box builds easier. Change-Id: Ib6240e7459a7e56f911c01e1ebe9f535cc0e50ad Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index aae5db0..051af05 100644 --- a/Makefile +++ b/Makefile @@ -26,10 +26,14 @@ export obj := $(src)/build export objk := $(src)/build/util/kconfig ifndef LIBCONFIG_PATH - LIBCONFIG_PATH := $(src)/../libpayload +LIBCONFIG_PATH := $(src)/../coreboot/payloads/libpayload endif export LIBCONFIG_PATH +ifeq ($(wildcard $(LIBCONFIG_PATH)/*),) +$(error Could not find libpayload at $(LIBCONFIG_PATH)) +endif + export KERNELVERSION := $(PROGRAM_VERSION) export KCONFIG_AUTOHEADER := $(obj)/config.h export KCONFIG_AUTOCONFIG := $(obj)/auto.conf

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Patch merged into coreboot/master: soc/intel/quark: Remove UPD parameters
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit eee0e229764e965996479d7eb07e6086176b8bf0 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Mar 11 07:55:24 2016 -0800 soc/intel/quark: Remove UPD parameters Remove the UPD parameters to match QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14451 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: Set BootMode based on previous sleep state
by Ravishankar Sarawadi 02 May '16

02 May '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14550 -gerrit commit f3792e999ad46640b6a28ce36b2bc16caf6e99c9 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 15:20:14 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 61 ++++++++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..a9c8f3d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -17,6 +17,7 @@ */ #include <assert.h> +#include <reset.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> @@ -35,9 +36,15 @@ #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <soc/pm.h> +#include <fsp/api.h> +#include <romstage_handoff.h> +#include <arch/early_variables.h> #define FIT_POINTER (0x100000000ULL - 0x40) +static struct chipset_power_state power_state CAR_GLOBAL; + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -77,6 +84,22 @@ static void disable_watchdog(void) outl(reg, ACPI_PMIO_BASE + 0x68); } +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); + asmlinkage void car_stage_entry(void) { void *hob_list_ptr, *mrc_data; @@ -84,6 +107,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; + int prev_sleep_state; + struct romstage_handoff *handoff; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -91,6 +117,8 @@ asmlinkage void car_stage_entry(void) disable_watchdog(); + prev_sleep_state = fill_power_state(ps); + /* Make sure the blob does not override our data in CAR */ range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); @@ -102,8 +130,17 @@ asmlinkage void car_stage_entry(void) fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ - cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, - range_entry_size(&fsp_mem)); + if (prev_sleep_state != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem)); + } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem))) { +#if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); +#endif + } /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != @@ -114,7 +151,8 @@ asmlinkage void car_stage_entry(void) fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ - if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && + (prev_sleep_state != SLEEP_STATE_S3)) { /* TODO: treat MRC data as const */ mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); @@ -122,6 +160,13 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to stash MRC data\n"); } + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -157,6 +202,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + int prev_sleep_state = chipset_prev_sleep_state(ps); fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -185,8 +232,12 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; - printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + arch_upd->Bootmode = + prev_sleep_state == SLEEP_STATE_S3 ? + FSP_BOOT_ON_S3_RESUME: + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", + mrc_cache->size, arch_upd->Bootmode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); }

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coreboot-gerrit May 2016