coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

1 participants
1843 discussions

Patch set updated for coreboot: soc/intel/common/mrc_cache: Honor MRC data as a constant pointer
by Alexandru Gagniuc 02 May '16

02 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14250 -gerrit commit 9203e85252ae5eb37f86f80240028049225cd634 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Mar 4 14:38:19 2016 -0800 soc/intel/common/mrc_cache: Honor MRC data as a constant pointer The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp1_1/romstage.c | 2 +- src/soc/intel/common/mrc_cache.c | 6 +++--- src/soc/intel/common/mrc_cache.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 3d698bb..c035f60 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -372,7 +372,7 @@ __attribute__((weak)) int mrc_cache_get_current( } /* Save the memory configuration data */ -__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size) +__attribute__((weak)) int mrc_cache_stash_data(const void *data, size_t size) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 1f59875..e96f7a7 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -162,7 +162,7 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return mrc_cache_get_current_with_version(cache, 0); } /* Fill in mrc_saved_data structure with payload. */ -static void mrc_cache_fill(struct mrc_saved_data *cache, void *data, +static void mrc_cache_fill(struct mrc_saved_data *cache, const void *data, size_t size, uint32_t version) { cache->signature = MRC_DATA_SIGNATURE; @@ -173,7 +173,7 @@ static void mrc_cache_fill(struct mrc_saved_data *cache, void *data, cache->size); } -int mrc_cache_stash_data_with_version(void *data, size_t size, +int mrc_cache_stash_data_with_version(const void *data, size_t size, uint32_t version) { int cbmem_size; @@ -199,7 +199,7 @@ int mrc_cache_stash_data_with_version(void *data, size_t size, return 0; } -int mrc_cache_stash_data(void *data, size_t size) +int mrc_cache_stash_data(const void *data, size_t size) { return mrc_cache_stash_data_with_version(data, size, 0); } diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 25d9316..9b14c1e 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -34,8 +34,8 @@ int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, uint32_t version); /* Stash the resulting MRC data to be saved in non-volatile storage later. */ -int mrc_cache_stash_data(void *data, size_t size); -int mrc_cache_stash_data_with_version(void *data, size_t size, +int mrc_cache_stash_data(const void *data, size_t size); +int mrc_cache_stash_data_with_version(const void *data, size_t size, uint32_t version); #endif /* _COMMON_MRC_CACHE_H_ */

1 0

Patch merged into coreboot/master: lib/coreboot_table: use the architecture dependent table size
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit a6e9051bc6843bb8f42df9c29cd254914ece93b4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 21 14:06:17 2016 -0500 lib/coreboot_table: use the architecture dependent table size Utilize the architecture dependent coreboot table size value from <arch/cbconfig.h> Change-Id: I80d51a5caf7c455b0b47c380e1d79cf522502a4c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14455 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14455 for details. -gerrit

1 0

Patch set updated for coreboot: soc/apollolake: Set BootMode based on previous sleep state
by Ravishankar Sarawadi 02 May '16

02 May '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14550 -gerrit commit 393a8cf23c77a39b4948a285792b27e9279c0be4 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 15:20:14 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 61 ++++++++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..4323e60 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -17,6 +17,7 @@ */ #include <assert.h> +#include <reset.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> @@ -35,9 +36,15 @@ #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <soc/pm.h> +#include <fsp/api.h> +#include <romstage_handoff.h> +#include <arch/early_variables.h> #define FIT_POINTER (0x100000000ULL - 0x40) +static struct chipset_power_state power_state CAR_GLOBAL; + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -77,6 +84,22 @@ static void disable_watchdog(void) outl(reg, ACPI_PMIO_BASE + 0x68); } +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); + asmlinkage void car_stage_entry(void) { void *hob_list_ptr, *mrc_data; @@ -84,6 +107,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; + int prev_sleep_state; + struct romstage_handoff *handoff; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -91,6 +117,8 @@ asmlinkage void car_stage_entry(void) disable_watchdog(); + prev_sleep_state = fill_power_state(ps); + /* Make sure the blob does not override our data in CAR */ range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); @@ -102,8 +130,17 @@ asmlinkage void car_stage_entry(void) fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ - cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, - range_entry_size(&fsp_mem)); + if (prev_sleep_state != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem)); + } else if(cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem))) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); +#endif + } /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != @@ -114,7 +151,8 @@ asmlinkage void car_stage_entry(void) fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ - if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && + (prev_sleep_state != SLEEP_STATE_S3)) { /* TODO: treat MRC data as const */ mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); @@ -122,6 +160,13 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to stash MRC data\n"); } + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -157,6 +202,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + int prev_sleep_state = chipset_prev_sleep_state(ps); fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -185,8 +232,12 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; - printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + arch_upd->Bootmode = + prev_sleep_state == SLEEP_STATE_S3 ? + FSP_BOOT_ON_S3_RESUME: + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", + mrc_cache->size, arch_upd->Bootmode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); }

1 0

Patch set updated for coreboot: lib/coreboot_table: use the architecture dependent table size
by Aaron Durbin 02 May '16

02 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14455 -gerrit commit 44aaca6a852347be954ca6dfb1ed1211647e95ff Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 21 14:06:17 2016 -0500 lib/coreboot_table: use the architecture dependent table size Utilize the architecture dependent coreboot table size value from <arch/cbconfig.h> Change-Id: I80d51a5caf7c455b0b47c380e1d79cf522502a4c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 9 --------- src/arch/arm/include/arch/cbconfig.h | 2 ++ src/arch/arm64/include/arch/cbconfig.h | 2 ++ src/arch/mips/include/arch/cbconfig.h | 2 ++ src/arch/power8/include/arch/cbconfig.h | 2 ++ src/arch/riscv/include/arch/cbconfig.h | 2 ++ src/arch/x86/include/arch/cbconfig.h | 2 ++ src/lib/coreboot_table.c | 3 ++- 8 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b656bbf..f9bd661 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -658,15 +658,6 @@ config ACPI_NHLT help Build support for NHLT (non HD Audio) ACPI table generation. - -config COREBOOT_TABLE_SIZE - hex - default 0x8000 if ARCH_X86 - default 0x2000 if !ARCH_X86 - help - The amount of memory to reserve for the coreboot tables in - cbmem. - #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/arm/include/arch/cbconfig.h b/src/arch/arm/include/arch/cbconfig.h index 7bf9452..9467f52 100644 --- a/src/arch/arm/include/arch/cbconfig.h +++ b/src/arch/arm/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/arm64/include/arch/cbconfig.h b/src/arch/arm64/include/arch/cbconfig.h index 7bf9452..9467f52 100644 --- a/src/arch/arm64/include/arch/cbconfig.h +++ b/src/arch/arm64/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/mips/include/arch/cbconfig.h b/src/arch/mips/include/arch/cbconfig.h index 7bf9452..9467f52 100644 --- a/src/arch/mips/include/arch/cbconfig.h +++ b/src/arch/mips/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/power8/include/arch/cbconfig.h b/src/arch/power8/include/arch/cbconfig.h index 7bf9452..9467f52 100644 --- a/src/arch/power8/include/arch/cbconfig.h +++ b/src/arch/power8/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/riscv/include/arch/cbconfig.h b/src/arch/riscv/include/arch/cbconfig.h index 7bf9452..9467f52 100644 --- a/src/arch/riscv/include/arch/cbconfig.h +++ b/src/arch/riscv/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x2000 + #endif diff --git a/src/arch/x86/include/arch/cbconfig.h b/src/arch/x86/include/arch/cbconfig.h index 7bf9452..78a5940 100644 --- a/src/arch/x86/include/arch/cbconfig.h +++ b/src/arch/x86/include/arch/cbconfig.h @@ -23,4 +23,6 @@ * to have the same name across all architectures. */ +#define COREBOOT_TABLE_SIZE 0x8000 + #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 58c6f48..4dbac19 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/cbconfig.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -560,7 +561,7 @@ void write_tables(void) uintptr_t cbtable_start; uintptr_t cbtable_end; size_t cbtable_size; - const size_t max_table_size = CONFIG_COREBOOT_TABLE_SIZE; + const size_t max_table_size = COREBOOT_TABLE_SIZE; cbtable_start = (uintptr_t)cbmem_add(CBMEM_ID_CBTABLE, max_table_size);

1 0

Patch merged into coreboot/master: arch: introduce architecture dependent common variables
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit a2118a21c9e6a65bd90481f222cb436509b3e0bb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 21 14:02:40 2016 -0500 arch: introduce architecture dependent common variables Stefan and others have discussed their interest in only including options in Kconfig that are directly associated with building a coreboot image. There are variables that are architecture dependent that are utilized in the coreboot infrastructure. To meet that goal, introduce <arch/cbconfig.h> header file which defines variables for the coreboot infrastructure that are architecture dependent but utilized in common infrastructure. Change-Id: Ic4cb9e81bab042797539dce004db0f7ee8526ea6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14454 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14454 for details. -gerrit

1 0

Patch set updated for coreboot: coreinfo: make the CBFS list scrollable
by Ben Gardner 02 May '16

02 May '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14546 -gerrit commit 224871ba2f2ea1279028225216ede78fbc6c48c8 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Apr 29 12:45:43 2016 -0500 coreinfo: make the CBFS list scrollable This enables viewing more than ~20 files in the file list on the left. Arrows are added to indicate that more items are available off-screen. This mimics what was done in pci_module. Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- payloads/coreinfo/cbfs_module.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index 6a3d71e..4502505 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -18,6 +18,8 @@ #if IS_ENABLED(CONFIG_MODULE_CBFS) +#define FILES_VISIBLE 19 + #define HEADER_MAGIC 0x4F524243 #define HEADER_ADDR 0xfffffffc #define LARCHIVE_MAGIC 0x455649484352414cLL /* "LARCHIVE" */ @@ -53,7 +55,7 @@ struct cbfile { char filename[0]; } __attribute__ ((packed)); -static int filecount = 0, selected = 0; +static int filecount = 0, selected = 0, start_row = 0; static char **filenames; static struct cbheader *header = NULL; @@ -120,7 +122,7 @@ static int cbfs_module_init(void) static int cbfs_module_redraw(WINDOW * win) { struct cbfile *f; - int i, row = 2; + int i, row, frow; print_module_title(win, "CBFS Listing"); @@ -134,7 +136,11 @@ static int cbfs_module_redraw(WINDOW * win) mvwaddch(win, i, 30, ACS_VLINE); /* Draw the names down the left side. */ - for (i = 0; i < filecount; i++) { + for (frow = 0; frow < FILES_VISIBLE; frow++) { + row = 2 + frow; + i = start_row + frow; + if (i >= filecount) + break; if (i == selected) wattrset(win, COLOR_PAIR(3) | A_BOLD); else @@ -142,11 +148,20 @@ static int cbfs_module_redraw(WINDOW * win) if (strlen(filenames[i]) == 0) { if (findfile(filenames[i])->type == COMPONENT_NULL) - mvwprintw(win, 2 + i, 1, "<free space>"); + mvwprintw(win, row, 1, "<free space>"); else - mvwprintw(win, 2 + i, 1, "<unnamed>"); + mvwprintw(win, row, 1, "<unnamed>"); } else { - mvwprintw(win, 2 + i, 1, "%.25s", filenames[i]); + mvwprintw(win, row, 1, "%.25s", filenames[i]); + } + /* show scroll arrows */ + if (frow == 0 && start_row > 0) { + wattrset(win, COLOR_PAIR(2)); + mvwaddch(win, row, 28, ACS_UARROW); + } + if (frow == FILES_VISIBLE - 1 && i != filecount - 1) { + wattrset(win, COLOR_PAIR(2)); + mvwaddch(win, row, 28, ACS_DARROW); } } @@ -158,6 +173,8 @@ static int cbfs_module_redraw(WINDOW * win) wattrset(win, COLOR_PAIR(2)); + /* Draw the file information */ + row = 2; /* mvwprintw(win, row++, 32, "Offset: 0x%x", f->offset); *//* FIXME */ mvwprintw(win, row, 32, "Type: "); switch (ntohl(f->type)) { @@ -212,12 +229,16 @@ static int cbfs_module_handle(int key) case KEY_DOWN: if (selected + 1 < filecount) { selected++; + if (selected >= start_row + FILES_VISIBLE - 1) + start_row = selected - (FILES_VISIBLE - 1); ret = 1; } break; case KEY_UP: if (selected > 0) { selected--; + if (selected < start_row) + start_row = selected; ret = 1; } break;

1 0

Patch merged into coreboot/master: nb/amd/mct_ddr3: Only initialize ECC bits once
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit 394041b149b578507df7a037c858acbb99918dc4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 24 20:56:31 2016 -0500 nb/amd/mct_ddr3: Only initialize ECC bits once The ECC check bits of all ECC DIMMS were inadvertently initialized twice in the same routine, significantly delaying startup. Part of this was related to an obsolete MCA workaround that has been fixed through multiple commits, therefore the workaround is no longer needed. Only initialize the ECC check bits once. Change-Id: I90ac1147d9b006794d29b866a9cb5b7ead8f01e7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14503 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14503 for details. -gerrit

1 0

Patch set updated for coreboot: cpu/x86: combine multiprocessor and SMM initialization
by Aaron Durbin 02 May '16

02 May '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14557 -gerrit commit f1fae2a3d8c0f2b6586cba60f60400a396111ebb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 22:55:49 2016 -0500 cpu/x86: combine multiprocessor and SMM initialization In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and optionally SMM initialization. The existing MP flight records are utilized but a common flow is provided such that the chipset/cpu only needs to provide a mp_ops structure which has callbacks to gather info and provide hooks at certain points in the sequence. All current users of the MP code can be switched over to this flow since there haven't been any flight records that are overly complicated and long. After the conversion has taken place most of the surface area of the MP API can be hidden away within the compilation unit proper. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mp_init.c | 239 +++++++++++++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/mp.h | 86 +++++++++++++++++ 2 files changed, 325 insertions(+) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 2180d98..c3da6e2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -607,3 +607,242 @@ void smm_initiate_relocation(void) smm_initiate_relocation_parallel(); spin_unlock(&smm_relocation_lock); } + +struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + int do_smm; +} mp_state; + +static int is_smm_enabled(void) +{ + return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm; +} + +static void smm_disable(void) +{ + mp_state.do_smm = 0; +} + +static void smm_enable(void) +{ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + mp_state.do_smm = 1; +} + +static void asmlinkage smm_do_relocation(void *arg) +{ + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + uintptr_t curr_smbase; + uintptr_t perm_smbase; + + p = arg; + runtime = p->runtime; + cpu = p->cpu; + curr_smbase = runtime->smbase; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + /* + * The permanent handler runs with all cpus concurrently. Precalculate + * the location of the new SMBASE. If using SMM modules then this + * calculation needs to match that of the module loader. + */ + perm_smbase = mp_state.perm_smbase; + perm_smbase -= cpu * runtime->save_state_size; + + printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); + + /* Setup code checks this callback for validity. */ + mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); +} + +static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) +{ + int i; + struct smm_runtime *runtime = smm_params->runtime; + + for (i = 0; i < CONFIG_MAX_CPUS; i++) + runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); +} + +static int install_relocation_handler(int num_cpus, size_t save_state_size) +{ + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = smm_do_relocation, + }; + + /* Allow callback to override parameters. */ + if (mp_state.ops.adjust_smm_params != NULL) + mp_state.ops.adjust_smm_params(&smm_params, 0); + + if (smm_setup_relocation_handler(&smm_params)) + return -1; + + adjust_smm_apic_id_map(&smm_params); + + return 0; +} + +static int install_permanent_handler(int num_cpus, uintptr_t smbase, + size_t smsize, size_t save_state_size) +{ + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + + /* Allow callback to override parameters. */ + if (mp_state.ops.adjust_smm_params != NULL) + mp_state.ops.adjust_smm_params(&smm_params, 0); + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08lx\n", smbase); + + if (smm_load_module((void *)smbase, smsize, &smm_params)) + return -1; + + adjust_smm_apic_id_map(&smm_params); + + return 0; +} + +/* Load SMM handlers as part of MP flight record. */ +static void load_smm_handlers(void) +{ + size_t smm_save_state_size = mp_state.smm_save_state_size; + + /* Do nothing if SMM is disabled.*/ + if (!is_smm_enabled()) + return; + + /* Install handlers. */ + if (install_relocation_handler(mp_state.cpu_count, + smm_save_state_size) < 0) { + printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); + smm_disable(); + } + + if (install_permanent_handler(mp_state.cpu_count, mp_state.perm_smbase, + mp_state.perm_smsize, smm_save_state_size) < 0) { + printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); + smm_disable(); + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + wbinvd(); + + /* + * Indicate that the SMM handlers have been loaded and MP + * initialization is about to start. + */ + if (is_smm_enabled() && mp_state.ops.pre_mp_init != NULL) + mp_state.ops.pre_mp_init(); +} + +/* Trigger SMM as part of MP flight record. */ +static void trigger_smm_relocation(void) +{ + /* Do nothing if SMM is disabled.*/ + if (!is_smm_enabled() || mp_state.ops.per_cpu_smm_trigger == NULL) + return; + /* Trigger SMM mode for the currently running processor. */ + mp_state.ops.per_cpu_smm_trigger(); +} + +static struct mp_flight_record mp_steps[] = { + /* Once the APs are up load the SMM handlers. */ + MP_FR_BLOCK_APS(NULL, load_smm_handlers), + /* Perform SMM relocation. */ + MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), + /* Initialize each cpu through the driver framework. */ + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), + /* Wait for APs to finish everything else then let them park. */ + MP_FR_BLOCK_APS(NULL, NULL), +}; + +static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) +{ + /* + * Make copy of the ops so that defaults can be set in the non-const + * structure if needed. + */ + memcpy(&state->ops, ops, sizeof(*ops)); + + if (ops->get_cpu_count != NULL) + state->cpu_count = ops->get_cpu_count(); + + if (ops->get_smm_info != NULL) + ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, + &state->smm_save_state_size); + + /* + * Default to smm_initiate_relocation() if trigger callback isn't + * provided. + */ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && + ops->per_cpu_smm_trigger == NULL) + mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; +} + +int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) +{ + int ret; + void *default_smm_area; + struct mp_params mp_params; + + fill_mp_state(&mp_state, mp_ops); + + memset(&mp_params, 0, sizeof(mp_params)); + + if (mp_state.cpu_count <= 0) { + printk(BIOS_ERR, "Invalid cpu_count: %d\n", mp_state.cpu_count); + return -1; + } + + /* Sanity check SMM state. */ + if (mp_state.perm_smsize != 0 && mp_state.smm_save_state_size != 0 && + mp_state.ops.relocation_handler != NULL) + smm_enable(); + + if (is_smm_enabled()) + printk(BIOS_INFO, "Will perform SMM setup.\n"); + + mp_params.num_cpus = mp_state.cpu_count; + /* Gather microcode information. */ + if (mp_state.ops.get_microcode_info != NULL) + mp_state.ops.get_microcode_info(&mp_params.microcode_pointer, + &mp_params.parallel_microcode_load); + mp_params.adjust_apic_id = mp_state.ops.adjust_cpu_apic_entry; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + + /* Perform backup of default SMM area. */ + default_smm_area = backup_default_smm_area(); + + ret = mp_init(cpu_bus, &mp_params); + + restore_default_smm_area(default_smm_area); + + /* Signal callback on success if it's provided. */ + if (ret == 0 && mp_state.ops.post_mp_init != NULL) + mp_state.ops.post_mp_init(); + + return ret; +} diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 3227975..24c4afe 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -17,6 +17,7 @@ #define _X86_MP_H_ #include <arch/smp/atomic.h> +#include <cpu/x86/smm.h> #define CACHELINE_SIZE 64 @@ -78,6 +79,91 @@ struct mp_params { int num_records; }; +struct mp_ops { + /* + * Return the number of logical x86 execution contexts that + * need to be brought out of SIPI state as well as have SMM + * handlers installed. + */ + int (*get_cpu_count)(void); + /* + * Optionally fill in permanent SMM region and save state size. If + * this callback is not present no SMM handlers will be installed. + * The perm_smsize is the size available to house the permanent SMM + * handler. + */ + void (*get_smm_info)(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + /* + * Optionally provide a function which adjusts the APIC id + * map to cpu number. By default the cpu number and APIC id + * are 1:1. To change the APIC id for a given cpu return the + * new APIC id. It's called for each cpu as indicated by + * get_cpu_count(). + */ + int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); + /* + * Optionally fill in pointer to microcode and indicate if the APs + * can load the microcode in parallel. + */ + void (*get_microcode_info)(const void **microcode, int *parallel); + /* + * Optionally adjust SMM handler parameters to override the default + * values. The is_perm variable indicates if the parameters to adjust + * are for the relocation handler or the permanent handler. This + * function is therefore called twice -- once for each handler. + * By default the parameters for each SMM handler are: + * stack_size num_concurrent_stacks num_concurrent_save_states + * relo: save_state_size get_cpu_count() 1 + * perm: save_state_size get_cpu_count() get_cpu_count() + */ + void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); + /* + * This function is called while each cpu is in the SMM relocation + * handler. Its primary purpose is to adjust the SMBASE for the + * permanent handler. The parameters passed are the current cpu + * running the relocation handler, current SMBASE of relocation handler, + * and the pre-calculated staggered cpu SMBASE address of the permanent + * SMM handler. + */ + void (*relocation_handler)(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase); + /* + * Optional function to use to trigger SMM to perform relocation. If + * not provided, smm_initiate_relocation() is used. + */ + void (*per_cpu_smm_trigger)(void); + /* + * Optionally provide a callback prior to the APs starting SMM + * relocation or cpu driver initialization. However, note that + * This callback is called after SMM handlers have been loaded. + */ + void (*pre_mp_init)(void); + /* + * Optionally provide a callback that is called after the APs + * and the BSP have gone through the initialion sequence. + */ + void (*post_mp_init)(void); +}; + +/* + * mp_init_with_smm() returns < 0 on failure and 0 on success. The mp_ops + * argument is used to drive the multiprocess initialization. The sequence of + * operations is the following: + * 1. get_cpu_count() + * 2. get_smm_info() + * 3. adjust_cpu_apic_entry() + * 4. get_microcode_info() + * 5. adjust_smm_params(is_perm=0) + * 6. adjust_smm_params(is_perm=1) + * 7. pre_mp_init() + * 8. per_cpu_smm_trigger() in parallel for all cpus which calls + * relocation_handler() in SMM. + * 9. mp_initialize_cpu() for each cpu + * 10. post_mp_init() + */ +int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); + /* * mp_init() will set up the SIPI vector and bring up the APs according to * mp_params. Each flight record will be executed according to the plan. Note

1 0

New patch to review for coreboot: intel/baytrail: use fmap information for code caching
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14573 -gerrit commit ed8c748748e172ed9d429e70d24677837ec1d31d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 17:27:01 2016 +0800 intel/baytrail: use fmap information for code caching Instead of using CBFS_SIZE from Kconfig, use values generated from fmap. While at it, make sure that the cached region size is a power of two. Change-Id: I03a919e1381ca3d0e972780b2c7d76c590aaa994 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 9ae10af..46bcc03 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -19,6 +19,8 @@ #include <cpu/x86/post_code.h> #include <cbmem.h> +#include "fmap_config.h" + /* The full cache-as-ram size includes the cache-as-ram portion from coreboot * and the space used by the reference code. These 2 values combined should * be a power of 2 because the MTRR setup assumes that. */ @@ -27,7 +29,7 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE /* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE) +#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) #define CODE_CACHE_BASE (-CODE_CACHE_SIZE) #define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) #define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1)

1 0

New patch to review for coreboot: lib/cbfs: Use fmap derived information about the COREBOOT region
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14572 -gerrit commit 512bac3a9d12b86e166524b02debab374a14de2e Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 17:22:29 2016 +0800 lib/cbfs: Use fmap derived information about the COREBOOT region It used to use CONFIG_CBFS_SIZE. The plan is that CBFS_SIZE only informs default*.fmd generation, while everything else derives its information from there. Also document the existing assumption that boot media should access the COREBOOT region (and not any other potentially existing fmap region containing a CBFS). Change-Id: I08254e4510f71edf99c2c8b56ac8f92008727c4a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/lib/Makefile.inc | 7 +++++++ src/lib/cbfs.c | 9 +++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 3352a30..4c6a395 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -179,6 +179,13 @@ $(call src-to-obj,smm,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h +$(call src-to-obj,bootblock,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,romstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,ramstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,smm,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,verstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,postcar,$(dir)/cbfs.c) : $(obj)/fmap_config.h + romstage-y += bootmode.c ramstage-y += bootmode.c verstage-y += bootmode.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index e1626d7..7b9f932 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -25,6 +25,8 @@ #include <symbols.h> #include <timestamp.h> +#include "fmap_config.h" + #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) #if IS_ENABLED(CONFIG_DEBUG_CBFS) @@ -215,6 +217,7 @@ out: return 0; } +/* This only supports the "COREBOOT" fmap region. */ static int cbfs_master_header_props(struct cbfs_props *props) { struct cbfs_header header; @@ -227,13 +230,15 @@ static int cbfs_master_header_props(struct cbfs_props *props) if (bdev == NULL) return -1; + uint32_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; + /* Find location of header using signed 32-bit offset from * end of CBFS region. */ - offset = CONFIG_CBFS_SIZE - sizeof(int32_t); + offset = fmap_top - sizeof(int32_t); if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) return -1; - offset = CONFIG_CBFS_SIZE + rel_offset; + offset = fmap_top + rel_offset; if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) return -1;

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2016