coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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1843 discussions

Patch merged into filo/master: Use libpayload timer API
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit bd5d0fc8dd435eccc253e53db09681014cbf7c62 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 18:02:10 2016 -0700 Use libpayload timer API Instead of implementing our own, platform specific timer API, use libpayload's code. Change-Id: I29634fdaba8a6b2f644736f29d8aa66380f4c797 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14373 for details. -gerrit

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Patch merged into filo/master: Move i386/linux_head.c to x86/linux_head.c
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit a7394bff40bd73597b92e03a39281cc38fc98ce5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 16:56:41 2016 -0700 Move i386/linux_head.c to x86/linux_head.c Looks like this was created before and merged after the rename i386 -> x86. Change-Id: Ia0ffb505c3fb62151ccfe81603e1c60089c3e109 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14372 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14372 for details. -gerrit

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Patch merged into filo/master: Use LPGCC and LPAS
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit 9f460faf4e5b4932099560b2086400a8f4b14f5a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 16:04:21 2016 -0700 Use LPGCC and LPAS FILO used to have its own ldscript because it used a bigger heap and stack that standard libpayload. These days, heap and stack are configurable in libpayload, so a separate script is not needed anymore. Change-Id: I81f6d8d3b3b3a11b58afd8d29e312d4264922dcd Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14369 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14369 for details. -gerrit

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Patch merged into filo/master: builtins: Only build dumppm and io on x86
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit 8d6313144c6fcd6b21244155a1413069804eaa2f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 13 17:23:52 2016 -0700 builtins: Only build dumppm and io on x86 They're architecture specific. Change-Id: Icc37317a3911a29ca3b472816e6213b688383cdb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14358 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14358 for details. -gerrit

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Patch merged into filo/master: Sync with coreboot's latest xcompile script
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit e7c85fe7178213489cc79f34ff9f34eebc3732f1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 13 17:18:08 2016 -0700 Sync with coreboot's latest xcompile script This requires some rework of the Makefile, since .config now needs to be included before .xcompile, and the toolchain now supports multiple architectures. Change-Id: I8ea3a4ed690144b4bcf3fb41263cf0ad2dfaa03d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14357 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14357 for details. -gerrit

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Patch merged into coreboot/master: cpu/x86/mp_init: remove unused callback arguments
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit 0e556326619ece4c7847ddc6ffccb19b02e22da4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 23:15:12 2016 -0500 cpu/x86/mp_init: remove unused callback arguments The BSP and AP callback declarations both had an optional argument that could be passed. In practice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14556 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit ddf4fa0cc35e6fc65d347b8c9eb4acbe0cba51b9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:43:27 2016 -0500 drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Remedy this failure by using the common car_stage_entry symbol for taking over control flow. Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14549 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/14549 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/assembly_entry: allow early post CAR stages to use common code
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit aef586548a2443f40a49f9f1f5d99c522a89480f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:34:01 2016 -0500 arch/x86/assembly_entry: allow early post CAR stages to use common code The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. The normal path for romstage would be to reload the gdt, however in the previously described scenario has verstage performing that work. Therefore, provide that path under those conditions. The only difference from the C_ENVIRONMENT_BOOTBLOCK scenario is that the stack should not be reloaded since there's no way to know the top of the stack. Change-Id: Ic39ab52a856233d3042ac02a15ae4816ddfe07c7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14548 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/14548 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/asembly_entry: reorder conditional stage entry macros
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit 800b0173c98101ee6ad2c7eaf1951a435c819fd9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:10:28 2016 -0500 arch/x86/asembly_entry: reorder conditional stage entry macros The path that just clears CAR_GLOBAL variables and jumps to the stage entry point needs another condition for separate verstage just after bootblock. However, the current conditional is a negative conditional so swap the logic around to make it easier to extend. Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14547 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/14547 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: Set BootMode based on previous sleep state
by Ravishankar Sarawadi 02 May '16

02 May '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14550 -gerrit commit 6b4f19c4e5e72c3865158021122ea7e344256797 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 15:20:14 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 61 ++++++++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..4d274ed 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -17,6 +17,7 @@ */ #include <assert.h> +#include <reset.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> @@ -35,9 +36,15 @@ #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <soc/pm.h> +#include <fsp/api.h> +#include <romstage_handoff.h> +#include <arch/early_variables.h> #define FIT_POINTER (0x100000000ULL - 0x40) +static struct chipset_power_state power_state CAR_GLOBAL; + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -77,6 +84,22 @@ static void disable_watchdog(void) outl(reg, ACPI_PMIO_BASE + 0x68); } +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); + asmlinkage void car_stage_entry(void) { void *hob_list_ptr, *mrc_data; @@ -84,6 +107,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; + int prev_sleep_state; + struct romstage_handoff *handoff; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -91,6 +117,8 @@ asmlinkage void car_stage_entry(void) disable_watchdog(); + prev_sleep_state = fill_power_state(ps); + /* Make sure the blob does not override our data in CAR */ range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); @@ -102,8 +130,17 @@ asmlinkage void car_stage_entry(void) fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ - cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, - range_entry_size(&fsp_mem)); + if (prev_sleep_state != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem)); + } else if(cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + range_entry_size(&fsp_mem))) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); +#endif + } /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != @@ -114,7 +151,8 @@ asmlinkage void car_stage_entry(void) fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ - if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && + (prev_sleep_state != SLEEP_STATE_S3)) { /* TODO: treat MRC data as const */ mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); @@ -122,6 +160,13 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to stash MRC data\n"); } + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -157,6 +202,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + int prev_sleep_state = chipset_prev_sleep_state(ps); fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -185,8 +232,12 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; - printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + arch_upd->Bootmode = + prev_sleep_state == SLEEP_STATE_S3 ? + FSP_BOOT_ON_S3_RESUME: + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", + mrc_cache->size, arch_upd->Bootmode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); }

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coreboot-gerrit May 2016