coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: coreboot_tables: Extend serial port description
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14111 -gerrit commit df4c3283f7d898498abfd09e17b2c707b6a9303a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Mar 16 10:21:59 2016 -0700 coreboot_tables: Extend serial port description Extend the serial port description to include the input clock frequency and an identifier for the serial port. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Use weak functions to allow the platform to override the input clock frequency and the input clock divisor to enable coreboot to compute the proper baud-rate divisor. Add a payload specific ID field used by the payload to identify the console UART within the system. A Kconfig value provides the default for this field to prevent breaking existing coreboot implementations. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I05a7e864afcd930916658e3efed53ff2efd403ec Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 2 ++ src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++ src/drivers/uart/Kconfig | 7 +++++++ src/drivers/uart/oxpcie_early.c | 2 ++ src/drivers/uart/pl011.c | 2 ++ src/drivers/uart/uart8250io.c | 12 ++++-------- src/drivers/uart/uart8250mem.c | 5 ++++- src/drivers/uart/util.c | 16 ++++++++++++++++ src/include/console/uart.h | 4 ++++ src/lib/coreboot_table.c | 2 ++ src/soc/intel/quark/Kconfig | 5 +++++ 11 files changed, 56 insertions(+), 9 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 276f25f..06d1768 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -121,6 +121,8 @@ struct cb_serial { u32 baseaddr; u32 baud; u32 regwidth; + u32 input_hertz; + u32 id; }; #define CB_TAG_CONSOLE 0x00010 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..926930d 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -173,6 +173,14 @@ struct lb_serial { uint32_t baseaddr; uint32_t baud; uint32_t regwidth; + /* Crystal or input frequency to the chip containing the UART. + * Provide the board specific details to allow the payload to + * initialize the chip containing the UART and make independent + * decisions as to which dividers to select and their values + * to eventually arrive at the desired console baud-rate. */ + uint32_t input_hertz; + /* Payload specific value to identify the console UART */ + uint32_t id; }; #define LB_TAG_CONSOLE 0x0010 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index f4ad011..25dc980 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -41,3 +41,10 @@ config DRIVERS_UART_PL011 bool default n select HAVE_UART_SPECIAL + +config UART_DEVICE_ID + hex + default 0 + help + ID to help the payload identify the proper UART + diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index eb91d31..479408b 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -92,6 +92,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index aa55c68..915273b 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -48,6 +48,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 63bc42f..c83c2d2 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -27,12 +27,6 @@ /* Should support 8250, 16450, 16550, 16550A type UARTs */ -/* Nominal values only, good for the range of choices Kconfig offers for - * set of standard baudrates. - */ -#define BAUDRATE_REFCLK (115200) -#define BAUDRATE_OVERSAMPLE (1) - /* Expected character delay at 1200bps is 9ms for a working UART * and no flow-control. Assume UART as stuck if shift register * or FIFO takes more than 50ms per character to appear empty. @@ -111,8 +105,8 @@ uintptr_t uart_platform_base(int idx) void uart_init(int idx) { unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, - BAUDRATE_OVERSAMPLE); + div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), + uart_input_clock_divider()); uart8250_init(uart_platform_base(idx), div); } @@ -139,6 +133,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..3fdb511 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -117,7 +117,8 @@ void uart_init(int idx) return; unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16); + div = uart_baudrate_divisor(default_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); uart8250_mem_init(base, div); } @@ -156,6 +157,8 @@ void uart_fill_lb(void *data) serial.regwidth = sizeof(uint32_t); else serial.regwidth = sizeof(uint8_t); + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 4121f60..9cda8a2 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -18,6 +18,12 @@ #include "option_table.h" #endif +/* Nominal values only, good for the range of choices Kconfig offers for + * set of standard baudrates. + */ +#define BAUDRATE_REFCLK (115200 * 16) +#define BAUDRATE_OVERSAMPLE (16) + unsigned int default_baudrate(void) { #if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE @@ -42,3 +48,13 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, { return (1 + (2 * refclk) / (baudrate * oversample)) / 2; } + +__attribute__((weak)) unsigned int uart_platform_refclk(void) +{ + return BAUDRATE_REFCLK; +} + +__attribute__((weak)) unsigned int uart_input_clock_divider(void) +{ + return BAUDRATE_OVERSAMPLE; +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..a3d650b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -35,6 +35,10 @@ unsigned int default_baudrate(void); unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); +/* Returns the oversample divisor multiplied by any other divisors that act + * on the input clock + */ +unsigned int uart_input_clock_divider(void); void uart_init(int idx); void uart_tx_byte(int idx, unsigned char data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4dbac19..5482660 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -119,6 +119,8 @@ void lb_add_serial(struct lb_serial *new_serial, void *data) serial->baseaddr = new_serial->baseaddr; serial->baud = new_serial->baud; serial->regwidth = new_serial->regwidth; + serial->input_hertz = new_serial->input_hertz; + serial->id = new_serial->id; } void lb_add_console(uint16_t consoletype, void *data) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index aab509a..d71af30 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -59,6 +59,11 @@ config TTYS0_LCS depends on ENABLE_BUILTIN_HSUART1 default 3 +config UART_DEVICE_ID + hex + depends on ENABLE_BUILTIN_HSUART1 + default 0x09368086 + ##### # Debug support # The following options provide debug support for the Quark coreboot

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Patch set updated for coreboot: mainboard/intel/galileo: Enable I2C and GPIO
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14558 -gerrit commit 1f73cfa8d60159cc49336b268395830e82721636 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 09:07:14 2016 -0700 mainboard/intel/galileo: Enable I2C and GPIO Enable the I2C and GPIO controllers TEST=Build and run on Galileo Gen2 Change-Id: I97bbbb7c5e72edbed14702a4129d9cfa977e1911 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 05edffc..66d32a8 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -39,7 +39,7 @@ chip soc/intel/quark device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 device pci 15.0 on end # 8086 0935 - SPI controller 0 device pci 15.1 on end # 8086 0935 - SPI controller 1 - device pci 15.2 off end # 8086 0934 - I2C/GPIO controller + device pci 15.2 on end # 8086 0934 - I2C/GPIO controller device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0 device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1 device pci 1f.0 on end # 8086 095E - Legacy Bridge

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Patch set updated for coreboot: vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14452 -gerrit commit 512b5ebaa6c3707c87f8b949f2785fed4bb7bddb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Mar 11 07:55:55 2016 -0800 vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h Update the file to match the QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: I090578d32165d34863548aec0e4a38fe915683c6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 62 ++++++++++------------- 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h index b6b6cc4..ef0cf09 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -36,18 +36,20 @@ are permitted provided that the following conditions are met: #pragma pack(1) -// -// TODO - Port to fit Quark SoC. -// +/** TODO - Port to fit Quark SoC. +**/ -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 +#define MAX_CHANNELS_NUM 1 +#define MAX_DIMMS_NUM 1 typedef struct { UINT8 DimmId; UINT32 SizeInMb; UINT16 MfgId; - UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ + /** Module part number for DDR3 is 18 bytes however for + DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + **/ + UINT8 ModulePartNum[20]; } DIMM_INFO; typedef struct { @@ -80,33 +82,34 @@ typedef struct { UINT64 Signature; /** Offset 0x0028 **/ - UINT8 Revision; -/** Offset 0x0029 - Tseg Size - Size of SMRAM memory reserved. + UINT64 Revision; +/** Offset 0x0030 **/ - UINT8 PcdSmmTsegSize; -/** Offset 0x002A + UINT32 PcdRmuBinaryBaseAddress; +/** Offset 0x0034 **/ - UINT32 PcdPlatformDataBaseAddress; -/** Offset 0x002E + UINT32 PcdRmuBinaryLen; +/** Offset 0x0038 **/ - UINT32 PcdPlatformDataMaxLen; -/** Offset 0x0032 + UINT8 PcdSmmTsegSize; +/** Offset 0x0039 **/ - UINT8 ReservedMemoryInitUpd[14]; + UINT8 PcdPlatformType; +/** Offset 0x003A +**/ + UINT8 ReservedMemoryInitUpd[22]; } MEMORY_INIT_UPD; typedef struct { -/** Offset 0x0040 +/** Offset 0x0050 **/ UINT64 Signature; -/** Offset 0x0048 +/** Offset 0x0058 **/ - UINT8 Revision; -/** Offset 0x0049 + UINT64 Revision; +/** Offset 0x0060 **/ - UINT8 ReservedSiliconInitUpd[183]; + UINT8 ReservedSiliconInitUpd[32]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ @@ -119,10 +122,7 @@ typedef struct _UPD_DATA_REGION { UINT64 Signature; /** Offset 0x0008 **/ - UINT8 Revision; -/** Offset 0x0009 -**/ - UINT8 ReservedUpd0[7]; + UINT64 Revision; /** Offset 0x0010 **/ UINT32 MemoryInitUpdOffset; @@ -135,10 +135,10 @@ typedef struct _UPD_DATA_REGION { /** Offset 0x0020 **/ MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0040 +/** Offset 0x0050 **/ SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0100 +/** Offset 0x0080 **/ UINT16 PcdRegionTerminator; } UPD_DATA_REGION; @@ -157,12 +157,6 @@ typedef struct _VPD_DATA_REGION { /** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[16]; -/** Offset 0x0020 -**/ - UINT32 PcdFspReservedMemoryLength; } VPD_DATA_REGION; #pragma pack()

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Patch merged into coreboot/master: .gitignore: add build and libpayload dirs for nvramcui payload
by gerrit＠coreboot.org 03 May '16

03 May '16

the following patch was just integrated into master: commit 127c1317542152a89f24f3518ba910815592887d Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun May 1 15:20:11 2016 +0200 .gitignore: add build and libpayload dirs for nvramcui payload Change-Id: I8a29ca1b07df68b50ab54276c9d9b32a81308e02 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: https://review.coreboot.org/14562 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/14562 for details. -gerrit

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Patch merged into coreboot/master: xcompile: test if gcc is really available
by gerrit＠coreboot.org 03 May '16

03 May '16

the following patch was just integrated into master: commit 98ab22711d6273e70c051a25ed7e76b215e700d5 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun May 1 19:41:28 2016 +0200 xcompile: test if gcc is really available Just because an 'as' with a certain prefix is available does not guarantee that a 'gcc' with the same prefix is available as well. Without a check detect_compiler_runtime() would try to execute an unavailable binary and print something like this: .../xcompile: line 218: arm-linux-gnueabi-gcc: command not found Change-Id: Icbadfeb2860152f7cf7696a9122521d0d881f3aa Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: https://review.coreboot.org/14563 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14563 for details. -gerrit

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Patch merged into coreboot/master: board_status/towiki: Link to CGit instead of Gitweb
by gerrit＠coreboot.org 03 May '16

03 May '16

the following patch was just integrated into master: commit 2d67d125701a78f488d0478cbf0861b4cd193685 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sat Apr 30 21:11:48 2016 +0200 board_status/towiki: Link to CGit instead of Gitweb Gitweb isn't online anymore, so fix a few broken links. Change-Id: I7fdfcb60f83a718c9a5b6c7f7ef4df9206451d95 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/14559 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14559 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume.
by Abhay Kumar 03 May '16

03 May '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14575 -gerrit commit 776e68aefbbb93c709b6ab31e451db40bfd674e8 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Sat Apr 30 13:57:47 2016 -0700 soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume. Change-Id: I9da58eb17111e8c47fffcf7fec96f02c111bdb16 Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6e0a90f..177949c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -29,6 +29,7 @@ #include <soc/cpu.h> #include <soc/nvs.h> #include <soc/pci_devs.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -83,8 +84,12 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; - /* Load VBT before devicetree-specific config. */ - silconfig->GraphicsConfigPtr = fsp_load_vbt(); + /* Load VBT before devicetree-specific config but not in Normal mode + and S3 resume */ + if (developer_mode_enabled() || recovery_mode_enabled()) { + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + }else + silconfig->GraphicsConfigPtr = (uintptr_t)NULL; struct device *dev = NB_DEV_ROOT; if (!dev || !dev->chip_info) {

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New patch to review for filo: fs: get rid of grub_open / grub_read / grub_seek / grub_close indirection
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14577 -gerrit commit 8df28362f653e736b1e66f46d999221a60a6c7c9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon May 2 18:04:18 2016 -0700 fs: get rid of grub_open / grub_read / grub_seek / grub_close indirection Change-Id: Ib1251d8b3c057f8f9a28e1986ae69efba44979ee Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- fs/filesys.h | 5 ----- fs/fsys_cramfs.c | 2 +- fs/fsys_ext2fs.c | 2 +- fs/fsys_minix.c | 2 +- 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/fs/filesys.h b/fs/filesys.h index fea1d35..747e69e 100644 --- a/fs/filesys.h +++ b/fs/filesys.h @@ -104,11 +104,6 @@ typedef enum extern grub_error_t errnum; -#define grub_open file_open -#define grub_read file_read -#define grub_seek file_seek -#define grub_close file_close - /* instrumentation variables */ /* (Not used in FILO) */ extern void (*disk_read_hook) (int, int, int); diff --git a/fs/fsys_cramfs.c b/fs/fsys_cramfs.c index 7866cdb..8bc42d4 100644 --- a/fs/fsys_cramfs.c +++ b/fs/fsys_cramfs.c @@ -339,7 +339,7 @@ cramfs_dir(char *dirname) linkbuf[filemax + len] = '\0'; /* Read the necessary blocks, and reset the file pointer. */ - len = grub_read(linkbuf, filemax); + len = file_read(linkbuf, filemax); filepos = 0; if (!len) return 0; diff --git a/fs/fsys_ext2fs.c b/fs/fsys_ext2fs.c index 51b3faf..527c6f6 100644 --- a/fs/fsys_ext2fs.c +++ b/fs/fsys_ext2fs.c @@ -942,7 +942,7 @@ ext2fs_dir (char *dirname) /* Read the symlink data. * Slow symlink is extents enabled - * But since grub_read invokes ext2fs_read, nothing to change here + * But since file_read invokes ext2fs_read, nothing to change here * */ if (! ext2_is_fast_symlink ()) { diff --git a/fs/fsys_minix.c b/fs/fsys_minix.c index f9b7519..6969ca6 100644 --- a/fs/fsys_minix.c +++ b/fs/fsys_minix.c @@ -381,7 +381,7 @@ minix_dir (char *dirname) linkbuf[filemax + len] = '\0'; /* Read the necessary blocks, and reset the file pointer. */ - len = grub_read (linkbuf, filemax); + len = file_read (linkbuf, filemax); filepos = 0; if (!len) return 0;

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New patch to review for filo: Drop grub_memmove indirection
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14576 -gerrit commit 4e0a3479c440013dcc86055b4c3f8c22f1843bf0 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon May 2 17:57:47 2016 -0700 Drop grub_memmove indirection Change-Id: I982f99063649947cbba5f70ce5fe9e0c61a85523 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- fs/filesys.h | 2 -- fs/fsys_jfs.c | 2 +- fs/fsys_reiserfs.c | 2 +- fs/fsys_xfs.c | 2 +- 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/fs/filesys.h b/fs/filesys.h index 2fe61a4..fea1d35 100644 --- a/fs/filesys.h +++ b/fs/filesys.h @@ -42,8 +42,6 @@ substring (const char *s1, const char *s2) return 1; } -#define grub_memmove memmove - #define MAXINT 0x7fffffff /* This is only used by fsys_* to determine if it's hard disk. If it is, diff --git a/fs/fsys_jfs.c b/fs/fsys_jfs.c index 2e46d93..f0d1ab6 100644 --- a/fs/fsys_jfs.c +++ b/fs/fsys_jfs.c @@ -291,7 +291,7 @@ jfs_dir (char *dirname) return 0; } if (di_size < (di_mode & INLINEEA ? 256 : 128)) { - grub_memmove (linkbuf, inode->di_fastsymlink, di_size); + memmove (linkbuf, inode->di_fastsymlink, di_size); n = di_size; } else if (di_size < JFS_PATH_MAX - 1) { filepos = 0; diff --git a/fs/fsys_reiserfs.c b/fs/fsys_reiserfs.c index d3de6be..2d47486 100644 --- a/fs/fsys_reiserfs.c +++ b/fs/fsys_reiserfs.c @@ -1030,7 +1030,7 @@ reiserfs_dir (char *dirname) /* Copy the remaining name to the end of the symlink data. Note that DIRNAME and LINKBUF may overlap! */ - grub_memmove (linkbuf + filemax, dirname, len+1); + memmove (linkbuf + filemax, dirname, len+1); INFO->fileinfo.k_dir_id = dir_id; INFO->fileinfo.k_objectid = objectid; diff --git a/fs/fsys_xfs.c b/fs/fsys_xfs.c index c71af98..1fb479a 100644 --- a/fs/fsys_xfs.c +++ b/fs/fsys_xfs.c @@ -489,7 +489,7 @@ xfs_read (char *buf, int len) int toread, startpos, endpos; if (icore.di_format == XFS_DINODE_FMT_LOCAL) { - grub_memmove (buf, inode->di_u.di_c + filepos, len); + memmove (buf, inode->di_u.di_c + filepos, len); filepos += len; return len; }

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Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Abhay Kumar 03 May '16

03 May '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 85d27c4d3cd8d64c95cc00468d6ca715ced8316c Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 4 + src/drivers/intel/fsp2_0/graphics.c | 36 ++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/silicon_init.c | 1 + src/soc/intel/apollolake/acpi.c | 85 +++++++++++- src/soc/intel/apollolake/include/soc/pci_ids.h | 5 + src/soc/intel/common/gma.h | 179 +++++++++++++++++++++++++ 7 files changed, 304 insertions(+), 7 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 19e04f7..70fbcbd 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -3,4 +3,8 @@ config PLATFORM_USES_FSP2_0 help Include FSP 2.0 wrappers and functionality +config DISPLAY_VBT + bool "Display Video BIOS Table (VBT)" + default n + diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..cd0149d 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -13,6 +13,7 @@ #include <cbfs.h> #include <console/console.h> #include <fsp/util.h> +#include <lib.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -93,13 +94,36 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) return CB_SUCCESS; } -uintptr_t fsp_load_vbt(void) +uintptr_t fsp_load_vbt() { - void *vbt; + size_t vbt_size; + struct cbfsf file_desc; + union { + optionrom_vbt_t *data; + uint32_t *signature; + } vbt; - vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); - if (!vbt) - printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + if (cbfs_boot_locate(&file_desc,"vbt.bin", NULL)) + printk(BIOS_NOTICE, "Could not locate a VBT file in in CBFS\n"); - return (uintptr_t)vbt; + vbt_size = region_device_sz(&file_desc.data); + vbt.data = malloc(vbt_size); + cbfs_file_data((void *)vbt.data, &file_desc); + vbt.data = rdev_mmap(&file_desc.data, 0, vbt_size); + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return (uintptr_t)NULL; + } + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + hexdump(vbt.data,*vbt_size ); + printk(BIOS_DEBUG, "\n"); +#endif + + rdev_munmap(&file_desc.data, vbt.data); + return (uintptr_t)vbt.data; } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..0497ceb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,7 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 66043c8..4c037eb 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -44,6 +44,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) hdr->silicon_init_entry_offset); status = silicon_init(&upd); + free((void *)&upd.FspsConfig.GraphicsConfigPtr); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); return status; } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a5d1dfa..bbf2595 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,12 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +41,74 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + optionrom_vbt_t *vbt; + vbt = (optionrom_vbt_t *)fsp_load_vbt(); + + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); + free(vbt); +} + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8KiB */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (uintptr_t)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,7 +200,16 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); + current = acpi_write_hpet(device, current, rsdp); + + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); + } static void acpi_create_gnvs(struct global_nvs_t *gnvs) diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 0790c6e..9b4b518 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -42,4 +42,9 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..cf259b0 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,179 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Abhay Kumar <abhay.kumar(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

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coreboot-gerrit May 2016