coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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1843 discussions

Patch merged into coreboot/master: build system: remove CBFSTOOL_PRE1_OPTS
by gerrit＠coreboot.org 03 May '16

03 May '16

the following patch was just integrated into master: commit 5cc0ee270c90c8eb6cec05f70ad9e133858707b3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 16:28:18 2016 +0800 build system: remove CBFSTOOL_PRE1_OPTS It isn't used anymore. Change-Id: Ie554d1dd87ae3f55547466e484c0864e55c9d102 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/14567 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14567 for details. -gerrit

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New patch to review for coreboot: payload: Fix broken Linux kernel as payload
by Werner Zeh 03 May '16

03 May '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14579 -gerrit commit 072ab0ffb0e49b1372a799afe32f4aeb2f2d398c Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue May 3 09:52:12 2016 +0200 payload: Fix broken Linux kernel as payload Commit 785a31d67e8f34065a2483080e4fd7032c3a8aad breaks the usage of Linux kernel as payload. The reason for it is that cbfs-files-y is evaluated before payloads/external/Makefile.inc is sourced and as a consequence ADDITIONAL_PAYLOAD_CONFIG is empty when it is used for payload options. That leads to missing command line and initrd for the kernel which in turn leads to kernel panic when it boots. To avoid it, move the code which adds payload to cbfs completely to payloads/extranal/Makefile.inc. This way, ADDITIONAL_PAYLOAD_CONFIG is set right before the payload itself is added to cbfs-files-y. I have tested this patch with a Linux kernel as well as with SeaBIOS as payload on mc_tcu3 and it works. If someone sees impact to other payloads just let me know. Change-Id: I7aad352f8b3fc1fdba1875b12648b07eba14e282 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- Makefile.inc | 10 ---------- payloads/external/Makefile.inc | 10 ++++++++++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0fb7a3d..508d0f9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -806,16 +806,6 @@ $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf $(CONFIG_CBFS_PREFIX)/ramstage-type := stage $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) -cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload -$(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) -ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) -$(CONFIG_CBFS_PREFIX)/payload-type := flat-binary -else -$(CONFIG_CBFS_PREFIX)/payload-type := payload -endif -$(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG) -$(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG) - cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) $(CONFIG_CBFS_PREFIX)/refcode-type := stage diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5ae9f7e..65b3dd2 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -42,6 +42,16 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))),) ADDITIONAL_PAYLOAD_CONFIG+=$(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))) endif +cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload +$(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) +ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) +$(CONFIG_CBFS_PREFIX)/payload-type := flat-binary +else +$(CONFIG_CBFS_PREFIX)/payload-type := payload +endif +$(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG) +$(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG) + cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_config payload_config-file := $(PAYLOAD_CONFIG) payload_config-type := raw

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New patch to review for coreboot: ec/lenovo/pmh7: Add discrete GPU power function
by Patrick Rudolph 03 May '16

03 May '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14578 -gerrit commit e8bbbfb0a872b762df556ee5db4fc2a5ba279a11 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue May 3 08:55:15 2016 +0200 ec/lenovo/pmh7: Add discrete GPU power function Allow to switch power on Lenovo laptops with discrete GPU. Switching of GPU power decreases idle power by 5W. Tested on Lenovo T520. Needs tests on all other Lenovo devices. Change-Id: I310a3912673558cd1af0582b7f2b23f957473c42 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/hybrid_graphics.c | 4 ++++ src/ec/lenovo/pmh7/pmh7.c | 18 +++++++++++++++++- src/ec/lenovo/pmh7/pmh7.h | 1 + 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index a90a465..603cef8 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <southbridge/intel/common/gpio.h> +#include <ec/lenovo/pmh7/pmh7.h> /* Hybrid graphics allows to connect LVDS interface to either iGPU * or dGPU depending on GPIO level. @@ -51,6 +52,9 @@ static void hybrid_graphics_disable_peg(struct device *dev) if (peg_dev) peg_dev->enabled = 0; + /* Disable power */ + pmh7_discrete_gpu_enable(0); + printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); } diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index b2c3c08..bb06094 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -18,11 +18,25 @@ #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include "pmh7.h" #include "chip.h" +void pmh7_discrete_gpu_enable(int onoff) +{ + /* based on Lenovo T520 */ + if (onoff) { + pmh7_register_set_bit(0x50, 3); + pmh7_register_set_bit(0x50, 6); + pmh7_register_set_bit(0x50, 7); + } else { + pmh7_register_clear_bit(0x50, 3); + pmh7_register_clear_bit(0x50, 6); + pmh7_register_clear_bit(0x50, 7); + } +} + void pmh7_backlight_enable(int onoff) { if (onoff) @@ -121,6 +135,8 @@ static void enable_dev(struct device *dev) if (get_option(&val, "trackpoint") != CB_SUCCESS) val = 1; pmh7_trackpoint_enable(val); + + pmh7_discrete_gpu_enable(1); } struct chip_operations ec_lenovo_pmh7_ops = { diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index 772312c..2894d4b 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -27,6 +27,7 @@ void pmh7_register_clear_bit(int reg, int bit); char pmh7_register_read(int reg); void pmh7_register_write(int reg, int val); +void pmh7_discrete_gpu_enable(int onoff); void pmh7_backlight_enable(int onoff); void pmh7_dock_event_enable(int onoff); void pmh7_touchpad_enable(int onoff);

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Patch set updated for coreboot: Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"
by Patrick Rudolph 03 May '16

03 May '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12895 -gerrit commit 9d5f878c1c1ab92efa1105d9821ec402a45b0478 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 13:21:43 2015 +0100 Revert "mainboard/lenovo/t400: Add initial hybrid graphics support" This reverts commit 59597ead1f26d4c18997bda81b2ec33e52973b80. Will be replaced by lenovo common hybrid driver. Change-Id: I994114734fa931926c34ed04305cddfbeb429b62 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/cmos.default | 1 - src/mainboard/lenovo/t400/cmos.layout | 7 -- src/mainboard/lenovo/t400/romstage.c | 143 --------------------------------- 3 files changed, 151 deletions(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 98ce970..ac9f96d 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,4 +13,3 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI -hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 8e642f8..0c12458 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -79,10 +79,6 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size -# coreboot config options: graphics -944 2 e 12 hybrid_graphics_mode -#946 6 r 0 unused - # coreboot config options: EC 952 8 h 0 volume @@ -136,9 +132,6 @@ enumerations 11 3 128M 11 5 96M 11 6 160M -12 0 Integrated Only -12 1 Discrete Only -12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 147131f..486b738 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -34,118 +33,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) -#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 -#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 -#define HYBRID_GRAPHICS_SWITCHABLE 2 - -#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 -#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 - -#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 - -#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 -#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 - -static void hybrid_graphics_configure_switchable_graphics(bool enable) -{ - uint32_t tmp; - - if (enable) { - /* Disable integrated graphics legacy VGA cycles */ - tmp = pci_read_config16(MCH_DEV, D0F0_GGC); - pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); - - /* Enable secondary VGA controller */ - tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); - pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); - } - else { - /* Enable integrated graphics legacy VGA cycles */ - tmp = pci_read_config16(MCH_DEV, D0F0_GGC); - pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); - - /* Disable secondary VGA controller */ - tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); - pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); - } -} - -static void hybrid_graphics_set_up_gpio(void) -{ - uint32_t tmp; - - /* Enable hybrid graphics GPIO lines */ - tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); - - tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - - /* Set hybrid graphics control GPIO lines to output */ - tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); - - tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); - - /* Set hybrid graphics detect GPIO lines to input */ - tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); - tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); -} - -static bool hybrid_graphics_installed(void) -{ - if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) - return false; - else - return true; -} - -static void hybrid_graphics_switch_to_integrated_graphics(void) -{ - uint32_t tmp; - - /* Disable switchable graphics */ - hybrid_graphics_configure_switchable_graphics(false); - - /* Configure muxes */ - tmp = inl(DEFAULT_GPIOBASE + GP_LVL); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL); - - tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); -} - -static void hybrid_graphics_switch_to_discrete_graphics(void) -{ - uint32_t tmp; - - /* Disable switchable graphics */ - hybrid_graphics_configure_switchable_graphics(false); - - /* Configure muxes */ - tmp = inl(DEFAULT_GPIOBASE + GP_LVL); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL); - - tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); -} - -static void hybrid_graphics_switch_to_dual_graphics(void) -{ - /* Enable switchable graphics */ - hybrid_graphics_configure_switchable_graphics(true); -} - static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -207,31 +94,6 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); - uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; - get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); - - /* Set up hybrid graphics */ - hybrid_graphics_set_up_gpio(); - if (hybrid_graphics_installed()) { - /* Select appropriate hybrid graphics device */ - printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); - if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) - hybrid_graphics_switch_to_integrated_graphics(); - else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) - hybrid_graphics_switch_to_discrete_graphics(); - else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) - hybrid_graphics_switch_to_integrated_graphics(); - /* Switchable graphics are fully enabled after raminit */ - /* FIXME - * Enabling switchable graphics prevents bootup! - * Debug and fix appropriately... - */ - } - else { - printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); - hybrid_graphics_switch_to_integrated_graphics(); - } - /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); @@ -311,11 +173,6 @@ void main(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); - - if (hybrid_graphics_installed()) - if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) - hybrid_graphics_switch_to_dual_graphics(); - #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc.

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Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 03 May '16

03 May '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit 41f9b1b329118dfcecee1a7fa71122ac3a48963e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 ++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 122 ++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 3 + src/mainboard/lenovo/t420/cmos.default | 1 + src/mainboard/lenovo/t420/cmos.layout | 5 +- src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t420s/cmos.default | 1 + src/mainboard/lenovo/t420s/cmos.layout | 5 +- src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t430s/cmos.default | 1 + src/mainboard/lenovo/t430s/cmos.layout | 5 +- src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t520/cmos.default | 1 + src/mainboard/lenovo/t520/cmos.layout | 5 +- src/mainboard/lenovo/t530/Kconfig | 1 + src/mainboard/lenovo/t530/cmos.default | 1 + src/mainboard/lenovo/t530/cmos.layout | 6 +- src/southbridge/intel/i82801ix/Kconfig | 1 + 21 files changed, 172 insertions(+), 5 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..a90a465 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <option.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +#define HYBRID_GRAPHICS_INTEGRATED 0 +#define HYBRID_GRAPHICS_DISCRETE 1 + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; + + printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); +} + +/* Called before VGA enable bits are set and only if dGPU + * is present. Enable/disable VGA devices here. */ +static void hybrid_graphics_enable_peg(struct device *dev) +{ + u8 hybrid_graphics_mode; + + hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + + if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); + dev->enabled = 1; + + /* Disable IGD */ + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (dev && dev->ops->disable) + dev->ops->disable(dev); + dev->enabled = 0; + + printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); + } else + hybrid_graphics_disable_peg(dev); +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index d74a813..a444bf8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index ac9f96d..98ce970 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 0c12458..b0131f6 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -78,6 +78,7 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size +944 2 e 12 hybrid_graphics_mode # coreboot config options: EC 952 8 h 0 volume @@ -132,6 +133,8 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 1b8e212..3a82c97 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -14,3 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index bf0f195..58a4abe 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume @@ -135,6 +136,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 935e659..feacb51 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 1b8e212..3a82c97 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -14,3 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 4362840..3521849 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume @@ -135,6 +136,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bb898cf..e7ed90b 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SANDYBRIDGE_IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 00e8863..ad7dcf5 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 16b499a..94e0280 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values @@ -134,6 +135,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c70581a..ee5dd81 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 00e8863..ad7dcf5 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 2cf3629..044c310 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values @@ -134,6 +135,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c1d0625..085711b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 00e8863..ad7dcf5 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index e21c197..0e28bdd 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume @@ -135,6 +136,9 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only + # ----------------------------------------------------------------- checksums diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 2822774..b3e5069 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS + select SOUTHBRIDGE_INTEL_COMMON_GPIO if SOUTHBRIDGE_INTEL_I82801IX

1 0

Patch set updated for coreboot: soc/intel/quark: Add IntelQNCConfig.h from EDK-II
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14497 -gerrit commit c6bdc8ea5303159d26b4c51bab620207700707e2 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 17:27:44 2016 -0700 soc/intel/quark: Add IntelQNCConfig.h from EDK-II Add the EDK-II Quark file IntelQNCConfig.h. This adds the definitions for the temperature sensor. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/IntelQNCConfig.h | 73 ++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/src/soc/intel/quark/include/soc/IntelQNCConfig.h b/src/soc/intel/quark/include/soc/IntelQNCConfig.h new file mode 100644 index 0000000..0375397 --- /dev/null +++ b/src/soc/intel/quark/include/soc/IntelQNCConfig.h @@ -0,0 +1,73 @@ +/** @file +Some configuration of QNC Package + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __INTEL_QNC_CONFIG_H__ +#define __INTEL_QNC_CONFIG_H__ + +// +// QNC Fixed configurations. +// + +// +// Memory arbiter fixed config values. +// +#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\ + (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \ + (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \ + (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \ + (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \ + )) + +// +// Memory Manager fixed config values. +// +#define V_DRAM_NON_HOST_RQ_LIMIT 2 + +// +// RMU Thermal config fixed config values for TS in Vref Mode. +// +#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04 +#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01 +#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1 +#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b +#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34 + +// +// RMU Thermal config fixed config values for TS in Ratiometric mode. +// +#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04 +#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02 +#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1 +#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f +#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001 +#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01 +#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00 +#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0 +#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0 +#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8 +#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17 + +// +// iCLK fixed config values. +// +#define V_MUXTOP_FLEX2 3 +#define V_MUXTOP_FLEX1 1 + +// +// PCIe Root Port fixed config values. +// +#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER) + +#endif

1 0

Patch set updated for coreboot: soc/intel/quark: Add temperature sensor support
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14565 -gerrit commit 1fe37b6b0e94c16a5eaee9e477b9ff169e482664 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 08:48:52 2016 -0700 soc/intel/quark: Add temperature sensor support Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 93 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 48 ++++++++++++++ src/soc/intel/quark/reg_access.c | 54 ++++++++++++++++ 3 files changed, 195 insertions(+) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 7ea8a06..aecc15a 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -17,9 +17,102 @@ #include <console/console.h> #include <device/device.h> #include <soc/ramstage.h> +#include <soc/reg_access.h> + +/* Cat Trip Clear value must be less than Cat Trip Set value */ +#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 +#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 + +static const struct reg_script init_script[] = { + + /* Setup RMU Thermal sensor registers for Ratiometric mode. */ + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, + ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK + | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK + | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN + | B_TSCGF1_CONFIG_IBGEN + | B_TSCGF1_CONFIG_IBGCHOPEN), + ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) + | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) + | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) + | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGEN_BP) + | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, + ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK + | B_TSCGF2_CONFIG2_ISPARECTRL_MASK + | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), + ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) + | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE + << B_TSCGF2_CONFIG2_ISPARECTRL_BP) + | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, + ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK + | B_TSCGF2_CONFIG_IDSTIMING_MASK), + ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE + << B_TSCGF2_CONFIG_IDSCONTROL_BP) + | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE + << B_TSCGF2_CONFIG_IDSTIMING_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, + V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE + << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), + + /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ + + /* Setup Catastrophic Trip point. + * + * Trip Register fields are 8-bit temperature values of granularity 1 + * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds + * to 205 degrees C. + * + * Add 50 to values to Celsius values to get values for register fields. + */ + REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, + ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), + (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) + << TS_CAT_TRIP_SET_THOLD_BP) + | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) + << TS_CAT_TRIP_CLEAR_THOLD_BP))), + + /* To enable the TS do the following: + * 1) Take the TS out of reset by setting itsrst to 0x0. + * 2) Enable the TS using RMU Thermal sensor mode register. + */ + REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSRST), + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), + + /* Lock all RMU Thermal sensor control & trip point registers. */ + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), + REG_SCRIPT_END +}; static void chip_init(void *chip_info) { + /* Validate the temperature settings */ + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + + /* Set the temperature settings */ + reg_script_run(init_script); + ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + & (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + == (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 934c75d..ddca668 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -18,10 +18,13 @@ #include <fsp/util.h> #include <reg_script.h> +#include <soc/IntelQNCConfig.h> #include <soc/QuarkNcSocId.h> enum { USB_PHY_REGS = 1, + SOC_UNIT_REGS, + RMU_TEMP_REGS, }; enum { @@ -32,6 +35,50 @@ enum { #define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) + +/* RMU temperature register access macros */ +#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + RMU_TEMP_REGS) +#define REG_RMU_TEMP_READ(reg_) \ + REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0) +#define REG_RMU_TEMP_WRITE(reg_, value_) \ + REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_RMU_TEMP_AND(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, value_, 0) +#define REG_RMU_TEMP_RMW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_RXW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_OR(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_) +#define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \ + REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_RMU_TEMP_XOR(reg_, value_) \ + REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_) + +/* Temperature sensor access macros */ +#define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + SOC_UNIT_REGS) +#define REG_SOC_UNIT_READ(reg_) \ + REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0) +#define REG_SOC_UNIT_WRITE(reg_, value_) \ + REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_SOC_UNIT_AND(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, value_, 0) +#define REG_SOC_UNIT_RMW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_RXW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_OR(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_) +#define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \ + REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_SOC_UNIT_XOR(reg_, value_) \ + REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) + +/* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ USB_PHY_REGS) @@ -56,5 +103,6 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_rmu_temp_read(uint32_t reg_address); #endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4a14903..bde151c 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -45,6 +45,40 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } +uint32_t reg_rmu_temp_read(uint32_t reg_address) +{ + /* Read the RMU temperature register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address); + return mdr_read(); +} + +static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value) +{ + /* Write the RMU temperature register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address); +} + +static uint32_t reg_soc_unit_read(uint32_t reg_address) +{ + /* Read the temperature sensor register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_soc_unit_write(uint32_t reg_address, uint32_t value) +{ + /* Write the temperature sensor register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); +} + static uint32_t reg_usb_read(uint32_t reg_address) { /* Read the USB register */ @@ -76,6 +110,16 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case RMU_TEMP_REGS: + ctx->display_prefix = "RMU TEMP: "; + value = reg_rmu_temp_read(step->reg); + break; + + case SOC_UNIT_REGS: + ctx->display_prefix = "SOC Unit: "; + value = reg_soc_unit_read(step->reg); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY: "; value = reg_usb_read(step->reg); @@ -96,6 +140,16 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case RMU_TEMP_REGS: + ctx->display_prefix = "RMU TEMP: "; + reg_rmu_temp_write(step->reg, (uint32_t)step->value); + break; + + case SOC_UNIT_REGS: + ctx->display_prefix = "SOC Unit: "; + reg_soc_unit_write(step->reg, (uint32_t)step->value); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY: "; reg_usb_write(step->reg, (uint32_t)step->value);

1 0

Patch set updated for coreboot: soc/intel/quark: Add USB PHY initialization
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14496 -gerrit commit ad8f47a8c38ff8e576f05dc90068ee132957914f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 2 14:31:02 2016 -0700 soc/intel/quark: Add USB PHY initialization Add register access support using register scripts. Initialize the USB PHY using register scripts. TEST=Build and run on Galileo Gen2 Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/Makefile.inc | 3 + src/soc/intel/quark/include/soc/pci_devs.h | 6 +- src/soc/intel/quark/include/soc/reg_access.h | 60 +++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 7 +- src/soc/intel/quark/reg_access.c | 110 +++++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 25 ------ src/soc/intel/quark/usb.c | 92 ++++++++++++++++++++++ 8 files changed, 271 insertions(+), 33 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index d71af30..bcad73a 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select REG_SCRIPT select SOC_INTEL_COMMON select SOC_SETS_MTRRS select TSC_CONSTANT_RATE diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index d8650fa..3a865b8 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,6 +19,7 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c @@ -27,9 +28,11 @@ ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += pmc.c +ramstage-y += reg_access.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c +ramstage-y += usb.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 4f577ce..a912c4c 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -25,9 +25,11 @@ /* DEVICE 0 (Memroy Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) -/* IO Fabric 1 */ -#define HSUART_DEVID 0x0936 +/* Device IDs */ +#define HSUART_DEVID 0x0936 +#define EHCI_DEVID 0x0939 +/* IO Fabric 1 */ #define SIO1_DEV 0x14 # define HSUART1_DEV SIO1_DEV # define HSUART1_FUNC 5 diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h new file mode 100644 index 0000000..934c75d --- /dev/null +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_REG_ACCESS_H_ +#define _QUARK_REG_ACCESS_H_ + +#include <fsp/util.h> +#include <reg_script.h> +#include <soc/QuarkNcSocId.h> + +enum { + USB_PHY_REGS = 1, +}; + +enum { + SOC_TYPE = REG_SCRIPT_TYPE_SOC_BASE, + /* Add additional SOC access types here*/ +}; + +#define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ + size_, reg_, mask_, value_, timeout_, reg_set_) +#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + USB_PHY_REGS) +#define REG_USB_READ(reg_) \ + REG_USB_ACCESS(READ, reg_, 0, 0, 0) +#define REG_USB_WRITE(reg_, value_) \ + REG_USB_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_USB_AND(reg_, value_) \ + REG_USB_RMW(reg_, value_, 0) +#define REG_USB_RMW(reg_, mask_, value_) \ + REG_USB_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_USB_RXW(reg_, mask_, value_) \ + REG_USB_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_USB_OR(reg_, value_) \ + REG_USB_RMW(reg_, 0xffffffff, value_) +#define REG_USB_POLL(reg_, mask_, value_, timeout_) \ + REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_USB_XOR(reg_, value_) \ + REG_USB_RXW(reg_, 0xffffffff, value_) + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); +uint32_t mdr_read(void); +void mdr_write(uint32_t value); +void mea_write(uint32_t reg_address); + +#endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c2c7e9c..c344ada 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -23,13 +23,8 @@ #endif #include <fsp/romstage.h> -#include <fsp/util.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); -uint32_t mdr_read(void); -void mdr_write(uint32_t value); -void mea_write(uint32_t reg_address); uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c new file mode 100644 index 0000000..4a14903 --- /dev/null +++ b/src/soc/intel/quark/reg_access.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +uint32_t mdr_read(void) +{ + return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); +} + +void mdr_write(uint32_t value) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); +} + +void mea_write(uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +static uint32_t reg_usb_read(uint32_t reg_address) +{ + /* Read the USB register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SC_USB_AFE_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_usb_write(uint32_t reg_address, uint32_t value) +{ + /* Write the USB register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SC_USB_AFE_SB_PORT_ID, + reg_address); +} + +static uint64_t reg_read(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + uint64_t value = 0; + + switch (step->id) { + default: + printk(BIOS_ERR, + "ERROR - Unknown register set (0x%08x)!\n", + step->id); + ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; + return 0; + + case USB_PHY_REGS: + ctx->display_prefix = "USB PHY: "; + value = reg_usb_read(step->reg); + break; + } + return value; +} + +static void reg_write(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + + switch (step->id) { + default: + printk(BIOS_ERR, + "ERROR - Unknown register set (0x%08x)!\n", + step->id); + ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; + return; + + case USB_PHY_REGS: + ctx->display_prefix = "USB PHY: "; + reg_usb_write(step->reg, (uint32_t)step->value); + break; + } +} + +const struct reg_script_bus_entry soc_reg_script_bus_table = { + SOC_TYPE, reg_read, reg_write +}; + +REG_SCRIPT_BUS_ENTRY(soc_reg_script_bus_table); diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 8b237a3..f03be1d 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -21,31 +21,6 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, - (opcode << QNC_MCR_OP_OFFSET) - | ((uint32_t)port << QNC_MCR_PORT_OFFSET) - | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) - | QNC_MCR_BYTE_ENABLES); -} - -uint32_t mdr_read(void) -{ - return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); -} - -void mdr_write(uint32_t value) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); -} - -void mea_write(uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address - & QNC_MEA_MASK); -} - static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) { uint32_t offset; diff --git a/src/soc/intel/quark/usb.c b/src/soc/intel/quark/usb.c new file mode 100644 index 0000000..460ef23 --- /dev/null +++ b/src/soc/intel/quark/usb.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +/* USB Phy Registers */ +#define USB2_GLOBAL_PORT 0x4001 +#define USB2_PLL1 0x7F02 +#define USB2_PLL2 0x7F03 +#define USB2_COMPBG 0x7F04 + +/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL + * reference clock and Port2 as a USB device port, the following sequence must + * be followed + */ +static const struct reg_script init_script[] = { + + /* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b. + * For port 0 & 1 as host and port 2 as device. + */ + REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)), + + /* + * Sighting #4930653 Required BIOS change on Disconnect vref to change + * to 600mV. + */ + REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7), + (BIT10 | BIT7)), + + /* Sideband register write to USB AFE (Phy) + * (pllbypass) to bypass/Disable PLL before switch + */ + REG_USB_OR(USB2_PLL2, BIT29), + + /* Sideband register write to USB AFE (Phy) + * (coreclksel) to select 120MHz (ickusbcoreclk) clk source. + * (Default 0 to select 96MHz (ickusbclk96_npad/ppad)) + */ + REG_USB_OR(USB2_PLL1, BIT1), + + /* Sideband register write to USB AFE (Phy) + * (divide by 8) to achieve internal 480MHz clock + * for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz) + */ + REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6), + + /* Sideband register write to USB AFE (Phy) + * Clear (pllbypass) + */ + REG_USB_AND(USB2_PLL2, ~BIT29), + + /* Sideband register write to USB AFE (Phy) + * Set (startlock) to force the PLL FSM to restart the lock + * sequence due to input clock/freq switch. + */ + REG_USB_OR(USB2_PLL2, BIT24), + REG_SCRIPT_END +}; + +static void init(device_t dev) +{ + printk(BIOS_INFO, "Initializing USB PLLs\n"); + reg_script_run_on_dev(dev, init_script); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = init, +}; + +static const struct pci_driver driver __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = EHCI_DEVID, +};

1 0

Patch set updated for coreboot: lib/reg_script: Add display support
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14553 -gerrit commit 31ddd8edd694674819209b673ef606483540b50f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:07:19 2016 -0700 lib/reg_script: Add display support Add the ability to enable the display of the script: * Added REG_SCRIPT_COMMAND_DISPLAY to enable and disable display output * Added context values to manage display support * display_state - Updated by the command to enable or disable display * display_features - May be updated by step routine to control what the step displays for register and value * display_prefix - Prefix to display before register data * Added REG_SCRIPT_DISPLAY_ON and REG_SCRIPT_DISPLAY_OFF macros to control the display from the register script * Added REG_SCRIPT_DISPLAY_REGISTER and REG_SCRIPT_DISPLAY_VALUE as two features of the common display. With these features enabled the following is output: * Write: <optional prefix> register <-- value * Read: <optional prefix> register --> value TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 22 +++++++++++ src/lib/reg_script.c | 97 ++++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 108 insertions(+), 11 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index da01481..d7ed326 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -47,6 +47,10 @@ enum { REG_SCRIPT_COMMAND_POLL, REG_SCRIPT_COMMAND_SET_DEV, REG_SCRIPT_COMMAND_NEXT, + REG_SCRIPT_COMMAND_DISPLAY, + + /* Insert new types above this comment */ + REG_SCRIPT_COMMAND_END, }; @@ -92,6 +96,9 @@ struct reg_script_context { device_t dev; struct resource *res; const struct reg_script *step; + uint8_t display_state; /* Only modified by reg_script_run_step */ + uint8_t display_features; /* Step routine modifies to control display */ + const char *display_prefix; /* Prefix tag to display */ }; struct reg_script_bus_entry { @@ -132,6 +139,21 @@ struct reg_script_bus_entry { .res_index = res_index_, \ } +/* Display control */ +#define REG_SCRIPT_DISPLAY_ALL 0xff +#define REG_SCRIPT_DISPLAY_REGISTER 0x02 +#define REG_SCRIPT_DISPLAY_VALUE 0x01 +#define REG_SCRIPT_DISPLAY_NOTHING 0 + +#define REG_SCRIPT_DISPLAY_OFF \ + { .command = REG_SCRIPT_COMMAND_DISPLAY, \ + .value = REG_SCRIPT_DISPLAY_NOTHING, \ + } +#define REG_SCRIPT_DISPLAY_ON \ + { .command = REG_SCRIPT_COMMAND_DISPLAY, \ + .value = REG_SCRIPT_DISPLAY_ALL, \ + } + /* * PCI */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 9e20134..ee26dc3 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -418,21 +418,34 @@ static const struct reg_script_bus_entry static uint64_t reg_script_read(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); + uint64_t value = 0; switch (step->type) { case REG_SCRIPT_TYPE_PCI: - return reg_script_read_pci(ctx); + ctx->display_prefix = "PCI: "; + value = reg_script_read_pci(ctx); + break; case REG_SCRIPT_TYPE_IO: - return reg_script_read_io(ctx); + ctx->display_prefix = "IO: "; + value = reg_script_read_io(ctx); + break; case REG_SCRIPT_TYPE_MMIO: - return reg_script_read_mmio(ctx); + ctx->display_prefix = "MMIO: "; + value = reg_script_read_mmio(ctx); + break; case REG_SCRIPT_TYPE_RES: - return reg_script_read_res(ctx); + ctx->display_prefix = "RES: "; + value = reg_script_read_res(ctx); + break; case REG_SCRIPT_TYPE_MSR: - return reg_script_read_msr(ctx); + ctx->display_prefix = "MSR: "; + value = reg_script_read_msr(ctx); + break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); + ctx->display_prefix = "IOSF: "; + value = reg_script_read_iosf(ctx); + break; #endif /* HAS_IOSF */ default: { @@ -441,38 +454,70 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) /* Read from the platform specific bus */ bus = find_bus(step); if (NULL != bus) - return bus->reg_script_read(ctx); + value = bus->reg_script_read(ctx); + break; } printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); - break; + return 0; } - return 0; + + /* Display the register address and data */ + if (ctx->display_features) { + if (ctx->display_prefix != NULL) + printk(BIOS_INFO, "%s", ctx->display_prefix); + if (ctx->display_features & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x --> ", step->reg); + if (ctx->display_features & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (int16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } + } + + return value; } static void reg_script_write(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); + uint64_t value; switch (step->type) { case REG_SCRIPT_TYPE_PCI: + ctx->display_prefix = "PCI: "; reg_script_write_pci(ctx); break; case REG_SCRIPT_TYPE_IO: + ctx->display_prefix = "IO: "; reg_script_write_io(ctx); break; case REG_SCRIPT_TYPE_MMIO: + ctx->display_prefix = "MMIO: "; reg_script_write_mmio(ctx); break; case REG_SCRIPT_TYPE_RES: + ctx->display_prefix = "RES: "; reg_script_write_res(ctx); break; case REG_SCRIPT_TYPE_MSR: + ctx->display_prefix = "MSR: "; reg_script_write_msr(ctx); break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: + ctx->display_prefix = "IOSF: "; reg_script_write_iosf(ctx); break; #endif /* HAS_IOSF */ @@ -484,13 +529,37 @@ static void reg_script_write(struct reg_script_context *ctx) bus = find_bus(step); if (NULL != bus) { bus->reg_script_write(ctx); - return; + break; } } printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); - break; + return; + } + + /* Display the register address and data */ + if (ctx->display_features) { + if (ctx->display_prefix != NULL) + printk(BIOS_INFO, "%s", ctx->display_prefix); + if (ctx->display_features & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x <-- ", step->reg); + value = step->value; + if (ctx->display_features & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (uint16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } } } @@ -557,6 +626,8 @@ static void reg_script_run_step(struct reg_script_context *ctx, { uint64_t value = 0, try; + ctx->display_features = ctx->display_state; + ctx->display_prefix = NULL; switch (step->command) { case REG_SCRIPT_COMMAND_READ: (void)reg_script_read(ctx); @@ -589,6 +660,10 @@ static void reg_script_run_step(struct reg_script_context *ctx, case REG_SCRIPT_COMMAND_NEXT: reg_script_run_next(ctx, step->next); break; + case REG_SCRIPT_COMMAND_DISPLAY: + ctx->display_state = step->value; + break; + default: printk(BIOS_WARNING, "Invalid command: %08x\n", step->command);

1 0

Patch set updated for coreboot: soc/intel/quark: Add script time delay support
by Leroy P Leahy 03 May '16

03 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14555 -gerrit commit 416541aeb6426b3e2fa728e65e5a1993428804b1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 16:36:02 2016 -0700 soc/intel/quark: Add script time delay support Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 6 ++++++ src/soc/intel/quark/reg_access.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index ddca668..63624a3 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,7 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#include <delay.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> @@ -25,6 +26,7 @@ enum { USB_PHY_REGS = 1, SOC_UNIT_REGS, RMU_TEMP_REGS, + TIME_DELAY, }; enum { @@ -78,6 +80,10 @@ enum { #define REG_SOC_UNIT_XOR(reg_, value_) \ REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) +/* Time delays */ +#define TIME_DELAY_USEC(value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, TIME_DELAY) + /* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index bde151c..87454c3 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -150,6 +150,14 @@ static void reg_write(struct reg_script_context *ctx) reg_soc_unit_write(step->reg, (uint32_t)step->value); break; + case TIME_DELAY: + if (ctx->display_features) { + printk(BIOS_INFO, "Delay %lld uSec\n", step->value); + ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; + } + udelay(step->value); + break; + case USB_PHY_REGS: ctx->display_prefix = "USB PHY: "; reg_usb_write(step->reg, (uint32_t)step->value);

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coreboot-gerrit May 2016