coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel/amenia: Declare ChromeEC in devicetree.cb
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14591 -gerrit commit 1a4a131a4aeab3ce6c23a175ffe9839063a94827 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue May 3 11:25:03 2016 -0700 intel/amenia: Declare ChromeEC in devicetree.cb This allows the chomeec driver to declare its resources so that IO windows to LPC are opened up during resource allocation. Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..38a2de2 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -46,7 +46,11 @@ chip soc/intel/apollolake device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC device pci 1e.0 on end # - SDIO - device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end device pci 1f.1 on end # - SMBUS end end

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Patch set updated for coreboot: intel/amenia: Configure the bridge to ChromeEC in the bootblock
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14588 -gerrit commit d2c33ab25413e18c2559056d2c889a1481be99e1 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue May 3 11:02:14 2016 -0700 intel/amenia: Configure the bridge to ChromeEC in the bootblock Communication with ChromeEC, which is on the LPC bus, is needed early on for vboot purposes. I'm not sure if Google wants to have the interface available in bootblock or romstage, so we're confguring it in the bootblock. The bridge is automatically reconfigured during ramstage in a way in which we don't get duplicate windows opened upt to LPC. Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/amenia/Makefile.inc | 2 ++ src/mainboard/intel/amenia/bootblock.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index f05e03b..8d4d5f7 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-y += bootblock.c + romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/amenia/bootblock.c b/src/mainboard/intel/amenia/bootblock.c new file mode 100644 index 0000000..c483d77 --- /dev/null +++ b/src/mainboard/intel/amenia/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/lpc.h> + +void bootblock_mainboard_init(void) +{ + /* Configure pads so that our signals make it out of the SOC. */ + lpc_configure_pads(); + + /* Ports 62/66, 60/64, and 200->208 are needed by ChromeEC */ + lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200); + + /* Ports 800 -> 9ff are used by ChromeEC. */ + lpc_open_pmio_window(0x800, 0x200); +}

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Patch set updated for coreboot: ec/google/chromeec/ec_commands.h: Include stdint.h
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14589 -gerrit commit 96fc8b4f4e49ca249f0897a4cd04b0772a437da0 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Apr 26 14:53:46 2016 -0700 ec/google/chromeec/ec_commands.h: Include stdint.h This file use stdint types, but does not include the appropriate header. This creates a parasitic dependency on including stdint.h before ec_commands.h. Fix that by including the necesarry header. Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/ec/google/chromeec/ec_commands.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index a90e22d..b562dd6 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -346,6 +346,8 @@ */ #ifndef __ACPI__ +#include <stdint.h> + /* * Define __packed if someone hasn't beat us to it. Linux kernel style * checking prefers __packed over __attribute__((packed)).

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New patch to review for coreboot: intel/amenia: Declare ChromeEC in devicetree.cb
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14591 -gerrit commit 7067f2e8f85b259027d025a8f7ed5facf086e896 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue May 3 11:25:03 2016 -0700 intel/amenia: Declare ChromeEC in devicetree.cb This allows the chomeec driver to declare its resources so that IO windows to LPC are opened up during resource allocation. Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..38a2de2 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -46,7 +46,11 @@ chip soc/intel/apollolake device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC device pci 1e.0 on end # - SDIO - device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end device pci 1f.1 on end # - SMBUS end end

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New patch to review for coreboot: intel/amenia: Check with EC if we should enter recovery mode
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14590 -gerrit commit 82b7648010acc18331d3ff9541d7d710a7a17d40 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Apr 26 15:01:01 2016 -0700 intel/amenia: Check with EC if we should enter recovery mode Change-Id: Id35a74e3968315659b323e0ba348ad38ca11981b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/amenia/chromeos.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c index dabb899..b6669bf 100644 --- a/src/mainboard/intel/amenia/chromeos.c +++ b/src/mainboard/intel/amenia/chromeos.c @@ -15,6 +15,9 @@ * GNU General Public License for more details. */ +#include "ec.h" + +#include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> int get_lid_switch(void) @@ -31,6 +34,13 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { + uint32_t ec_events; + + /* Recovery mode via ESC + Refresh + PWR ? */ + ec_events = google_chromeec_get_events_b(); + if (ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)) + return 1; + return 0; }

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New patch to review for coreboot: ec/google/chromeec/ec_commands.h: Include stdint.h
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14589 -gerrit commit 8395da99351bb180ea1faa1cbb3e5e9c475858f7 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Apr 26 14:53:46 2016 -0700 ec/google/chromeec/ec_commands.h: Include stdint.h This file use stdint types, but does not include the appropriate header. This creates a parasitic dependency on including stdint.h before ec_commands.h. Fix that by including the necesarry header. Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/ec/google/chromeec/ec_commands.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index a90e22d..b562dd6 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -346,6 +346,8 @@ */ #ifndef __ACPI__ +#include <stdint.h> + /* * Define __packed if someone hasn't beat us to it. Linux kernel style * checking prefers __packed over __attribute__((packed)).

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New patch to review for coreboot: intel/amenia: Configure the bridge to ChromeEC in the bootblock
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14588 -gerrit commit 74ea101b948326d18cd5ae4a5072773b9be7726d Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue May 3 11:02:14 2016 -0700 intel/amenia: Configure the bridge to ChromeEC in the bootblock Communication with ChromeEC, which is on the LPC bus, is needed early on for vboot purposes. I'm not sure if Google wants to have the interface available in bootblock or romstage, so we're confguring it in the bootblock. The bridge is automatically reconfigured during ramstage in a way in which we don't get duplicate windows opened upt to LPC. Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/amenia/Makefile.inc | 2 ++ src/mainboard/intel/amenia/bootblock.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index f05e03b..8d4d5f7 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-y += bootblock.c + romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/amenia/bootblock.c b/src/mainboard/intel/amenia/bootblock.c new file mode 100644 index 0000000..c483d77 --- /dev/null +++ b/src/mainboard/intel/amenia/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/lpc.h> + +void bootblock_mainboard_init(void) +{ + /* Configure pads so that our signals make it out of the SOC. */ + lpc_configure_pads(); + + /* Ports 62/66, 60/64, and 200->208 are needed by ChromeEC */ + lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200); + + /* Ports 800 -> 9ff are used by ChromeEC. */ + lpc_open_pmio_window(0x800, 0x200); +}

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New patch to review for coreboot: soc/apollolake/lpc_lib: Add utility to configure LPC pads
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14587 -gerrit commit 06744dc77baffa2594bcaa2ddaef860ba5fedb96 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Apr 28 10:38:05 2016 -0700 soc/apollolake/lpc_lib: Add utility to configure LPC pads Change-Id: Iaf325863681ad9b8b5d7662a9d267488b8fdf008 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/include/soc/lpc.h | 2 ++ src/soc/intel/apollolake/lpc_lib.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h index c24f6c1..b37db06 100644 --- a/src/soc/intel/apollolake/include/soc/lpc.h +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -53,6 +53,8 @@ #define LGMR_EN (1 << 0) #define LGMR_WINDOW_SIZE (64 * KiB) +/* Configure the SOC's LPC pads and mux them to the LPC function. */ +void lpc_configure_pads(void); /* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. */ void lpc_enable_fixed_io_ranges(uint16_t io_enables); /* Open a generic IO window to the LPC bus. Four windows are available. */ diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c index c3d7aae..d99b58f 100644 --- a/src/soc/intel/apollolake/lpc_lib.c +++ b/src/soc/intel/apollolake/lpc_lib.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <device/pci.h> #include <lib.h> +#include <soc/gpio.h> #include <soc/lpc.h> #include <soc/pci_devs.h> @@ -40,6 +41,21 @@ static const struct lpc_mmio_range { { 0, 0 } }; +static const struct pad_config lpc_gpios[] = { + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) +}; + +void lpc_configure_pads(void) +{ + gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios)); +} + void lpc_enable_fixed_io_ranges(uint16_t io_enables) { uint16_t reg_io_enables;

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New patch to review for coreboot: soc/apollolake/lpc: Allow configuring SERIRQ in continuous mode
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14586 -gerrit commit 7f8fe994ee059de370574917113d5d7338bf189c Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Apr 4 10:47:49 2016 -0700 soc/apollolake/lpc: Allow configuring SERIRQ in continuous mode Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ continuous mode. Why they do that is beyond me, but the way we implement it on apollolake is via devicetree. Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/chip.h | 3 +++ src/soc/intel/apollolake/lpc.c | 23 +++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..05adef5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,9 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Enable continuous mode for LPC SERIRQ line. */ + bool serirq_continuous_mode; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 58a3cdb..e97f76a 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -22,6 +23,8 @@ #include <soc/lpc.h> #include <soc/pci_ids.h> +#include "chip.h" + /* * SCOPE: * The purpose of this driver is to eliminate manual resource allocation for @@ -40,6 +43,25 @@ * opens up IO and memory windows as needed. */ +static void lpc_init(struct device *dev) +{ + uint8_t scnt; + struct soc_intel_apollolake_config *cfg; + + cfg = dev->chip_info; + if (!cfg) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + if (cfg->serirq_continuous_mode) { + scnt = pci_read_config8(dev, REG_SERIRQ_CTL); + scnt |= SCNT_EN | SCNT_MODE; + pci_write_config8(dev, REG_SERIRQ_CTL, scnt); + } + +} + static void soc_lpc_add_io_resources(device_t dev) { struct resource *res; @@ -115,6 +137,7 @@ static struct device_operations device_ops = { .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .init = lpc_init, .scan_bus = scan_lpc_bus, };

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New patch to review for coreboot: ec/google/chromeec/ec_lpc: Declare used IO ports as a resource
by Alexandru Gagniuc 03 May '16

03 May '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14585 -gerrit commit 0f4efda6cf51c17b36206da9cbd6aa3243078d02 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Mar 30 14:38:44 2016 -0700 ec/google/chromeec/ec_lpc: Declare used IO ports as a resource Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/ec/google/chromeec/ec_lpc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 021735e..d70d782 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -409,7 +409,15 @@ static void lpc_ec_init(struct device *dev) static void lpc_ec_read_resources(struct device *dev) { - /* Nothing, but this function avoids an error on serial console. */ + unsigned int idx = 0; + struct resource * res; + + /* Declare the IO ports that we are using. */ + res = new_resource(dev, idx++); + res->base = MEC_EMI_RANGE_START; + res->size = MEC_EMI_RANGE_END - MEC_EMI_RANGE_START + 1; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void lpc_ec_enable_resources(struct device *dev)

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coreboot-gerrit May 2016