coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/amenia: Remove PEIM GFX from normal mode and S3 resume.
by Abhay Kumar 03 May '16

03 May '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14575 -gerrit commit c98419a429b15a051a8457bb181edcaac285c01e Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Sat Apr 30 13:57:47 2016 -0700 intel/amenia: Remove PEIM GFX from normal mode and S3 resume. Change-Id: I9da58eb17111e8c47fffcf7fec96f02c111bdb16 Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6e0a90f..177949c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -29,6 +29,7 @@ #include <soc/cpu.h> #include <soc/nvs.h> #include <soc/pci_devs.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -83,8 +84,12 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; - /* Load VBT before devicetree-specific config. */ - silconfig->GraphicsConfigPtr = fsp_load_vbt(); + /* Load VBT before devicetree-specific config but not in Normal mode + and S3 resume */ + if (developer_mode_enabled() || recovery_mode_enabled()) { + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + }else + silconfig->GraphicsConfigPtr = (uintptr_t)NULL; struct device *dev = NB_DEV_ROOT; if (!dev || !dev->chip_info) {

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Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Abhay Kumar 03 May '16

03 May '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 21812798614c1475ae1351fd6429bf2e649b3976 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 4 + src/drivers/intel/fsp2_0/graphics.c | 36 ++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/silicon_init.c | 2 +- src/soc/intel/apollolake/acpi.c | 85 +++++++++++- src/soc/intel/apollolake/include/soc/pci_ids.h | 5 + src/soc/intel/common/gma.h | 179 +++++++++++++++++++++++++ 7 files changed, 304 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 19e04f7..70fbcbd 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -3,4 +3,8 @@ config PLATFORM_USES_FSP2_0 help Include FSP 2.0 wrappers and functionality +config DISPLAY_VBT + bool "Display Video BIOS Table (VBT)" + default n + diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..cd0149d 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -13,6 +13,7 @@ #include <cbfs.h> #include <console/console.h> #include <fsp/util.h> +#include <lib.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -93,13 +94,36 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) return CB_SUCCESS; } -uintptr_t fsp_load_vbt(void) +uintptr_t fsp_load_vbt() { - void *vbt; + size_t vbt_size; + struct cbfsf file_desc; + union { + optionrom_vbt_t *data; + uint32_t *signature; + } vbt; - vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); - if (!vbt) - printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + if (cbfs_boot_locate(&file_desc,"vbt.bin", NULL)) + printk(BIOS_NOTICE, "Could not locate a VBT file in in CBFS\n"); - return (uintptr_t)vbt; + vbt_size = region_device_sz(&file_desc.data); + vbt.data = malloc(vbt_size); + cbfs_file_data((void *)vbt.data, &file_desc); + vbt.data = rdev_mmap(&file_desc.data, 0, vbt_size); + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return (uintptr_t)NULL; + } + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + hexdump(vbt.data,*vbt_size ); + printk(BIOS_DEBUG, "\n"); +#endif + + rdev_munmap(&file_desc.data, vbt.data); + return (uintptr_t)vbt.data; } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..0497ceb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,7 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 66043c8..21a3570 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -44,7 +44,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) hdr->silicon_init_entry_offset); status = silicon_init(&upd); - printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + free((void *)&upd.FspsConfig.GraphicsConfigPtr); return status; } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a5d1dfa..bbf2595 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,12 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +41,74 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + optionrom_vbt_t *vbt; + vbt = (optionrom_vbt_t *)fsp_load_vbt(); + + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); + free(vbt); +} + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8KiB */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (uintptr_t)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,7 +200,16 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); + current = acpi_write_hpet(device, current, rsdp); + + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); + } static void acpi_create_gnvs(struct global_nvs_t *gnvs) diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 0790c6e..9b4b518 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -42,4 +42,9 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..cf259b0 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,179 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Abhay Kumar <abhay.kumar(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

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Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Abhay Kumar 03 May '16

03 May '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 03cf38de866d474c99bbe52ff45f0c609bfc6ca6 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 4 + src/drivers/intel/fsp2_0/graphics.c | 36 ++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/silicon_init.c | 2 +- src/soc/intel/apollolake/acpi.c | 85 +++++++++++- src/soc/intel/apollolake/include/soc/pci_ids.h | 5 + src/soc/intel/common/gma.h | 182 +++++++++++++++++++++++++ 7 files changed, 307 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 19e04f7..70fbcbd 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -3,4 +3,8 @@ config PLATFORM_USES_FSP2_0 help Include FSP 2.0 wrappers and functionality +config DISPLAY_VBT + bool "Display Video BIOS Table (VBT)" + default n + diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..cd0149d 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -13,6 +13,7 @@ #include <cbfs.h> #include <console/console.h> #include <fsp/util.h> +#include <lib.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -93,13 +94,36 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) return CB_SUCCESS; } -uintptr_t fsp_load_vbt(void) +uintptr_t fsp_load_vbt() { - void *vbt; + size_t vbt_size; + struct cbfsf file_desc; + union { + optionrom_vbt_t *data; + uint32_t *signature; + } vbt; - vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); - if (!vbt) - printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + if (cbfs_boot_locate(&file_desc,"vbt.bin", NULL)) + printk(BIOS_NOTICE, "Could not locate a VBT file in in CBFS\n"); - return (uintptr_t)vbt; + vbt_size = region_device_sz(&file_desc.data); + vbt.data = malloc(vbt_size); + cbfs_file_data((void *)vbt.data, &file_desc); + vbt.data = rdev_mmap(&file_desc.data, 0, vbt_size); + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return (uintptr_t)NULL; + } + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + hexdump(vbt.data,*vbt_size ); + printk(BIOS_DEBUG, "\n"); +#endif + + rdev_munmap(&file_desc.data, vbt.data); + return (uintptr_t)vbt.data; } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..0497ceb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,7 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 66043c8..21a3570 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -44,7 +44,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) hdr->silicon_init_entry_offset); status = silicon_init(&upd); - printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + free((void *)&upd.FspsConfig.GraphicsConfigPtr); return status; } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a5d1dfa..bbf2595 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,12 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +41,74 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + optionrom_vbt_t *vbt; + vbt = (optionrom_vbt_t *)fsp_load_vbt(); + + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); + free(vbt); +} + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8KiB */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (uintptr_t)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,7 +200,16 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); + current = acpi_write_hpet(device, current, rsdp); + + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); + } static void acpi_create_gnvs(struct global_nvs_t *gnvs) diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 0790c6e..9b4b518 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -42,4 +42,9 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..519aad1 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

1 0

Patch set updated for filo: Add flashupdate command
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5988 -gerrit commit 2952fcef3ca2c8019b1df7fc411d9223af41b59a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 19 16:40:06 2011 +0200 Add flashupdate command This command allows the user to load a coreboot image, configure its cmos.default file and write it to flash, all from FILO. Change-Id: Ia011deb64bcf75aebe8b67554ad9d9738d90fe59 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- Kconfig | 18 ++- Makefile | 1 + flashupdate/Makefile.inc | 29 +++++ flashupdate/flashrom-bridge.c | 73 +++++++++++ flashupdate/flashupdate.c | 277 ++++++++++++++++++++++++++++++++++++++++++ main/grub/builtins.c | 19 ++- 6 files changed, 413 insertions(+), 4 deletions(-) diff --git a/Kconfig b/Kconfig index 21a718d..90fa2f4 100644 --- a/Kconfig +++ b/Kconfig @@ -200,8 +200,7 @@ config FLASHROM_LOCKDOWN default n help Enable system flash memory write protections and lock them down prior - starting the kernel. Flash memory lockdown can be disabled per boot - entry with the new command 'flashrom_unlock'. + starting the kernel. NOTE: Only supported on selected hardware: @@ -210,6 +209,21 @@ config FLASHROM_LOCKDOWN o Intel Cougar Point / Panther Point PCH (FWH + SPI) o AMD SB600 (SPI by locking the flash chip itself) +config FLASHROM_UNLOCK + bool "Provide flashrom_unlock command" + default n + depends on FLASHROM_LOCKDOWN + help + Flashrom lockdown can be disabled per boot entry with the new + command 'flashrom_unlock'. + +config FLASHUPDATE + bool "Provide flashupdate command" + default n + help + Add "flashupdate" command based on http://www.flashrom.org/ to + FILO. + endmenu menu "Filesystems" diff --git a/Makefile b/Makefile index 1a9430d..7426395 100644 --- a/Makefile +++ b/Makefile @@ -119,6 +119,7 @@ CFLAGS += $(call cc-option, -fno-stack-protector,) LIBS := $(LIBPAYLOAD) $(LIBGCC) +SUBDIRS-$(CONFIG_USE_GRUB) += flashupdate SUBDIRS-y += main fs drivers $(ARCHDIR-y) $(foreach subdir,$(SUBDIRS-y),$(eval include $(subdir)/Makefile.inc)) diff --git a/flashupdate/Makefile.inc b/flashupdate/Makefile.inc new file mode 100644 index 0000000..319add3 --- /dev/null +++ b/flashupdate/Makefile.inc @@ -0,0 +1,29 @@ +# +# Copyright (C) 2011 secunet AG +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +LIBFLASHROM_PREFIX ?= $(obj)/libflashrom +LIBFLASHROM = $(LIBFLASHROM_PREFIX)/lib/libflashrom.a +INCFLASHROM = $(LIBFLASHROM_PREFIX)/include + +ifeq ($(CONFIG_FLASHUPDATE),y) +CPPFLAGS += -I$(INCFLASHROM) +LIBS += $(LIBFLASHROM) +endif + +TARGETS-$(CONFIG_FLASHUPDATE) += flashupdate/flashupdate.o +TARGETS-$(CONFIG_FLASHUPDATE) += flashupdate/flashrom-bridge.o diff --git a/flashupdate/flashrom-bridge.c b/flashupdate/flashrom-bridge.c new file mode 100644 index 0000000..0940389 --- /dev/null +++ b/flashupdate/flashrom-bridge.c @@ -0,0 +1,73 @@ +#include <stdarg.h> +#include <string.h> + +#include "flashchips.h" +#include "flash.h" +#include "programmer.h" + +int new_rom_size; +void *new_rom_data; + +int old_rom_size; +void *old_rom_data; + +// for flashrom +int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int print(int type, const char *fmt, ...) +{ +#ifdef DEBUG + if (type > MSG_INFO) return 0; + int ret; + va_list args; + va_start(args, fmt); + ret = vprintf(fmt, args); + va_end(args); + return ret; +#else + return 0; +#endif +} + +/* returned memory must be freed by caller */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + return strdup("Unknown"); +} + +int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename) +{ + // we need at least enough space for our image. + if (size < new_rom_size) + return 1; + + // top-align our image into the chip + memcpy(buf + size - new_rom_size, new_rom_data, new_rom_size); + + return 0; +} + +int read_flash_to_file(struct flashctx *flash, const char *filename) +{ + int ret = 0; + unsigned long size = flash->total_size * 1024; + if (size > old_rom_size) { + msg_cerr("old rom buffer not large enough for flash\n"); + ret = 1; + goto out_free; + } + + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + ret = 1; + goto out_free; + } + if (flash->read(flash, old_rom_data, 0, size)) { + msg_cerr("Read operation failed!\n"); + ret = 1; + goto out_free; + } + +out_free: + return ret; +} + diff --git a/flashupdate/flashupdate.c b/flashupdate/flashupdate.c new file mode 100644 index 0000000..c0f337d --- /dev/null +++ b/flashupdate/flashupdate.c @@ -0,0 +1,277 @@ +#include <stdlib.h> +#include <getopt.h> +#include <libpayload.h> +#include <coreboot_tables.h> +#include <cbfs.h> +#include <grub/shared.h> +#include <fs.h> +#include <pci/pci.h> + +/* flashrom defines */ +#define CONFIG_INTERNAL 1 +#include "flashchips.h" +#include "flash.h" +#include "programmer.h" + +extern int new_rom_size; +extern void *new_rom_data; + +struct flashctx flashchip; + +static void beep_success() +{ + int i; + for (i = 0; i < 5; i++) { + speaker_tone(440, 200); mdelay(300); + speaker_tone(660, 200); mdelay(300); + speaker_tone(880, 200); mdelay(300); + mdelay(3*1000); + } +} + +static void beep_fail() +{ + int i; + for (i = 0; i < 5; i++) { + speaker_tone(1200, 200); mdelay(300); + speaker_tone( 660, 200); mdelay(300); + mdelay(3*1000); + } +} + +static int init_flash(const char* flashtype) +{ + int j; + verbose++; + if (programmer_init(PROGRAMMER_INTERNAL, NULL)) { + grub_printf("Could not initialize programmer\n"); + return -1; + } + for (j = 0; j < registered_programmer_count; j++) { + int current_chip = -1; + do { + current_chip = probe_flash(&registered_programmers[j], ++current_chip, &flashchip, 0); + if ((current_chip != -1) && ((flashtype == NULL) || (strcasecmp(flashchip.name, flashtype) == 0))) { + return 0; + } + } while (current_chip != -1); + } + + grub_printf("Could not find flash chip\n"); + return -1; +} + +static int write_flash(void *imgdata, int size) +{ + return doit(&flashchip, 1, imgdata, 0, 1, 0, 1); +} + +static int test_id_section(void *romarea, unsigned int romsize, int offset, char **vendor, char **model, char **version) +{ + /* data[-1]: romsize + data[-2]: offset top-of-rom to board model + data[-3]: offset top-of-rom to board vendor + data[-4]: offset top-of-rom to build version */ + unsigned int *data = romarea+romsize-offset; + *version = romarea+romsize-data[-4]; + *vendor = romarea+romsize-data[-3]; + *model = romarea+romsize-data[-2]; + /* Assume that data[-1] matches filesize, and that vendor and model are laid out without extra space. + DO NOT assume that model aligns to the offsets, there may be future additions. */ + return ((data[-1] == romsize) && (*vendor+strnlen(*vendor, data[-2])+1 == *model)); +} + +int flashupdate_func(char *arg, int flags) +{ + int result = -1; + int force = 0; + char *chiptype = NULL; + char *vendor = NULL; + char *board = NULL; + char *region = NULL; + + char **argv; + int argc = to_argc_argv(arg, &argv); + + new_rom_data = NULL; + + char opt; + optreset = optind = 1; + while ((opt = getopt(argc, argv, "fc:v:b:i:")) != -1) { + switch (opt) { + case 'f': + force = 1; + break; + case 'c': + chiptype = optarg; + break; + case 'v': + vendor = optarg; + break; + case 'b': + board = optarg; + break; + case 'i': + region = optarg; + break; + default: + grub_printf("unsupported option -%c.\n", opt); + goto out; + break; + } + } + + if (optind >= argc) { + grub_printf("No filename specified.\n"); + goto out; + } + const char *filename = argv[optind]; + + if (vendor && board && + ((strcmp(vendor, cb_mb_vendor_string(lib_sysinfo.mainboard)) != 0) || + (strcmp(board, cb_mb_part_string(lib_sysinfo.mainboard)) != 0))) { + /* since flashupdate semantics is: iff board matches, write flash; + it's a success not to flash on another board. */ + result = 0; + goto out; + } + + if (region) { + register_include_arg(region); + layout_use_ifd(); + } + + /* Step 0: Init programmer/flash to find out if we _can_ flash (we should) */ + if (init_flash(chiptype) == -1) { + grub_printf("Could not initialize flash programmer.\n"); + goto out; + } + + /* Step 1: read requested image file */ + if (!file_open(filename)) { + grub_printf("Could not open file '%s'\n", filename); + goto out; + } + + /* 16K of extra space, since we don't have feof() */ + new_rom_size = flashchip.total_size * 1024 + 16384; + new_rom_data = malloc(new_rom_size); + if (new_rom_data == NULL) { + grub_printf("Could not allocate memory.\n"); + goto out; + } + void *readbuf = new_rom_data; + int len; + grub_printf("Loading image file... "); + while ((len = file_read(readbuf, 16384)) != 0) { + readbuf += len; + /* We can abort if we cut into the last 16K: + * it's more than the flash is able to carry + */ + if (readbuf - new_rom_data > new_rom_size - 16384) { + file_close(); + grub_printf("File too large for flash\n"); + goto out; + } + } + new_rom_size = readbuf - new_rom_data; + file_close(); + grub_printf("done\n"); + + /* retarget all CBFS accesses to new image */ + setup_cbfs_from_ram(new_rom_data, new_rom_size); + + /* Step 2: Check Board IDs (that we work on the right image) */ + const char *cur_version = lib_sysinfo.cb_version; + const char *cur_vendor = cb_mb_vendor_string(lib_sysinfo.mainboard); + const char *cur_board = cb_mb_part_string(lib_sysinfo.mainboard); + + /* Step 2a: check if this is a coreboot image by looking for a CBFS master header */ + if (get_cbfs_header() != 0xffffffff) { + /* Step 2b: look for .id section in new ROM */ + /* There are currently two locations where .id can reside: top-0x10 and top-0x80. There's + no indicator which one is used in any given image, though it should be stable on any given + board. As a heuristic, we can check if the data is sane at each location. */ + char *new_vendor; + char *new_board; + char *new_version; + if (!test_id_section(new_rom_data, new_rom_size, 0x10, &new_vendor, &new_board, &new_version)) + if (!test_id_section(new_rom_data, new_rom_size, 0x80, &new_vendor, &new_board, &new_version)) { + grub_printf("Could not detect if file supports this system.\n"); + goto out; + } + if ((strcmp(cur_vendor, new_vendor) != 0) || (strcmp(cur_board, new_board) != 0)) { + grub_printf("File (%s %s) seems to be incompatible with current system (%s %s).\n", + new_vendor, new_board, cur_vendor, cur_board); + goto out; + } + + /* Step 3: Check image version (so that we don't reflash the same image again and again) */ + if (strcmp(cur_version, new_version) == 0) { + grub_printf("No need to update to the same version '%s'.\n", cur_version); + /* TODO: exit successfully. right? */ + result = 0; + goto out; + } + + /* Step 4: Merge current CMOS data with cmos.defaults */ + /* Step 4a: Load new CMOS data */ + void *cmos_defaults = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT); + void *cmos_layout = cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT); + /* Step 4a1: Point use_mem to cmos.default. */ + mem_accessor_base = cmos_defaults; + if (cmos_defaults && cmos_layout) { + /* Step 4b: Check if current CMOS data is valid. */ + if (options_checksum_valid(use_nvram)) { + /* Step 4c: Iterate over current CMOS data */ + struct cb_cmos_entries *cmos_entry = first_cmos_entry(get_system_option_table()); + do { + /* Step 4c1: Attempt to update new CMOS data with current values. Ignore failures */ + char *val = NULL; + get_option_as_string(use_nvram, get_system_option_table(), &val, cmos_entry->name); + if (val) { + set_option_from_string(use_mem, cmos_layout, val, cmos_entry->name); + } + } while (cmos_entry = next_cmos_entry(cmos_entry)); + } + + /* Step 5: Write merged CMOS image to CMOS */ + /* TODO: do we need to skip 0x32 (RTC century)? */ + int i; + for (i = 14; i < 256; i++) + nvram_write(((u8*)cmos_defaults)[i], i); + + /* Step 6: Set cmos_defaults_loaded=no in CMOS data using new layout */ + set_option_from_string(use_nvram, cmos_layout, "No", "cmos_defaults_loaded"); + + /* Step 6a: Set cmos_defaults_loaded=Yes in cmos.default in ROM image. */ + set_option_from_string(use_mem, cmos_layout, "Yes", "cmos_defaults_loaded"); + } + } else { + if (!force) { + grub_printf("This is a not a coreboot image. Aborting.\n"); + goto out; + } + } + + grub_printf("Writing image to flash, please wait.\n"); + /* Step 7: Flash image */ + if (write_flash(new_rom_data, new_rom_size) == 0) { + grub_printf("Flash was updated successfully.\n"); + result = 0; + beep_success(); + } else { + grub_printf("WARNING: Error while updating flash!!\n"); + beep_fail(); + } + + /* success */ + programmer_shutdown(); + +out: + if (new_rom_data) free(new_rom_data); + new_rom_data = NULL; + if (argv) free(argv); + return result; +} + diff --git a/main/grub/builtins.c b/main/grub/builtins.c index f53fe79..e6651d5 100644 --- a/main/grub/builtins.c +++ b/main/grub/builtins.c @@ -551,7 +551,7 @@ static struct builtin builtin_find = { }; #endif -#ifdef CONFIG_FLASHROM_LOCKDOWN +#ifdef CONFIG_FLASHROM_UNLOCK /* flashrom_unlock */ /* Disable lockdown of flash memory on boot */ static int flashrom_unlock_func(char *arg, int flags) @@ -570,6 +570,18 @@ static struct builtin builtin_flashrom_unlock = { }; #endif +#ifdef CONFIG_FLASHUPDATE +int flashupdate_func(char *arg, int flags); + +static struct builtin builtin_flashupdate = { + "flashupdate", + flashupdate_func, + BUILTIN_CMDLINE | BUILTIN_HELP_LIST, + "flashupdate DEVICE", + "Update flash ROM from a file loaded from DEVICE (selected by the user)." +}; +#endif + /* help */ #define MAX_SHORT_DOC_LEN 39 #define MAX_LONG_DOC_LEN 66 @@ -1936,9 +1948,12 @@ struct builtin *builtin_table[] = { #ifdef CONFIG_EXPERIMENTAL &builtin_find, #endif -#ifdef CONFIG_FLASHROM_LOCKDOWN +#ifdef CONFIG_FLASHROM_UNLOCK &builtin_flashrom_unlock, #endif +#ifdef CONFIG_FLASHUPDATE + &builtin_flashupdate, +#endif &builtin_help, &builtin_hiddenmenu, &builtin_initrd,

1 0

Patch set updated for filo: fs: Don't reimplement log2
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14374 -gerrit commit 3bced897ad2b05b7054db1f2b5e137e24e932255 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 18:04:29 2016 -0700 fs: Don't reimplement log2 libpayload already provides an implementation, that is available for all platforms. Use that one instead of this incomplete version. Change-Id: Idcfc09ddc008ccb2eeb46081e25c2b7c1c1cce15 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- fs/filesys.h | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/fs/filesys.h b/fs/filesys.h index 168413b..2fe61a4 100644 --- a/fs/filesys.h +++ b/fs/filesys.h @@ -23,38 +23,6 @@ #include <config.h> #include <fs.h> -#if defined(__i386__) -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz (unsigned long word) -{ - __asm__ ("bsfl %1,%0" - : "=r" (word) - : "r" (~word)); - return word; -} -#elif defined(__ppc__) -static inline unsigned long __ilog2(unsigned long x) -{ - unsigned long lz; - asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); - return 31 - lz; -} - -static inline unsigned long ffz(unsigned long x) -{ - if ((x = ~x) == 0) - return 32; - - return __ilog2(x & -x); -} -#endif - -#define log2(n) ffz(~(n)) - - static inline int substring (const char *s1, const char *s2) {

1 0

Patch set updated for filo: Add ARM support
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14370 -gerrit commit 8828bc32481fcbab84fd061184c03c4764e9f2a1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 15:48:17 2016 -0700 Add ARM support Change-Id: I9325f6df06cf85ecd77abef5c0a7b4d2742466f4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Kconfig | 19 +++++++++++++++---- Makefile | 6 ++++-- arm/Makefile.inc | 20 ++++++++++++++++++++ arm/elf.c | 29 +++++++++++++++++++++++++++++ arm/include/arch/elf.h | 5 +++++ arm/sys_info.c | 35 +++++++++++++++++++++++++++++++++++ main/grub/builtins.c | 12 ++++++++++++ main/grub/grub.c | 6 ++++++ 8 files changed, 126 insertions(+), 6 deletions(-) diff --git a/Kconfig b/Kconfig index cc48bd3..21a718d 100644 --- a/Kconfig +++ b/Kconfig @@ -4,13 +4,21 @@ mainmenu "FILO Configuration" -# When (if) we support multiple architectures, this will become an option. +choice + prompt "Build for architecture" + default TARGET_I386 + config TARGET_I386 - bool - default y + bool "x86" + +config TARGET_ARM + bool "ARM" + +endchoice config MULTIBOOT_IMAGE bool "Include a MultiBoot header" + depends on TARGET_I386 default y help Including a MultiBoot header makes FILO chainloadable by MultiBoot @@ -103,6 +111,7 @@ menu "Drivers" config IDE_DISK bool "IDE DISK support" + depends on TARGET_I386 default y help Driver for hard disk, CompactFlash, and CD-ROM on IDE bus @@ -138,6 +147,7 @@ config PCMCIA_CF config IDE_NEW_DISK bool "New IDE driver" + depends on TARGET_I386 default n depends on !IDE_DISK help @@ -165,6 +175,7 @@ config FLASH_DISK config SUPPORT_PCI bool "PCI support" default y + depends on TARGET_I386 config PCI_BRUTE_SCAN bool "Scan all PCI busses" @@ -234,7 +245,7 @@ config FSYS_ISO9660 config ELTORITO bool "El Torito bootable CDROMs" default y - depends on FSYS_ISO9660 + depends on FSYS_ISO9660 && TARGET_I386 help Support for boot disk image in bootable CD-ROM (El Torito) diff --git a/Makefile b/Makefile index 39e477b..1a9430d 100644 --- a/Makefile +++ b/Makefile @@ -81,6 +81,8 @@ $(if $(wildcard .xcompile),,$(shell bash util/xcompile/xcompile > .xcompile)) include .xcompile ARCH-$(CONFIG_TARGET_I386) := x86_32 +ARCH-$(CONFIG_TARGET_ARM) := arm + CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) @@ -104,6 +106,7 @@ LPGCC = $(LIBPAYLOAD_PREFIX)/bin/lpgcc LPAS = $(LIBPAYLOAD_PREFIX)/bin/lpas ARCHDIR-$(CONFIG_TARGET_I386) := x86 +ARCHDIR-$(CONFIG_TARGET_ARM) := arm CPPFLAGS := -nostdinc -imacros $(obj)/config.h CPPFLAGS += -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y) @@ -116,8 +119,7 @@ CFLAGS += $(call cc-option, -fno-stack-protector,) LIBS := $(LIBPAYLOAD) $(LIBGCC) -SUBDIRS-y += main/ fs/ drivers/ -SUBDIRS-$(CONFIG_TARGET_I386) += x86/ +SUBDIRS-y += main fs drivers $(ARCHDIR-y) $(foreach subdir,$(SUBDIRS-y),$(eval include $(subdir)/Makefile.inc)) diff --git a/arm/Makefile.inc b/arm/Makefile.inc new file mode 100644 index 0000000..8009ec2 --- /dev/null +++ b/arm/Makefile.inc @@ -0,0 +1,20 @@ +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +TARGETS-$(CONFIG_TARGET_ARM) += arm/sys_info.o arm/elf.o + diff --git a/arm/elf.c b/arm/elf.c new file mode 100644 index 0000000..5db5227 --- /dev/null +++ b/arm/elf.c @@ -0,0 +1,29 @@ +/* + * This file is part of FILO. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +void relocate(void) +{ + // Not supported +} + +u32 start_elf(u32 entry_point, u32 param) +{ + // Not supported + return 0; +} diff --git a/arm/include/arch/elf.h b/arm/include/arch/elf.h new file mode 100644 index 0000000..2a5bbbf --- /dev/null +++ b/arm/include/arch/elf.h @@ -0,0 +1,5 @@ +#define ARCH_ELF_CLASS ELFCLASS32 +#define ARCH_ELF_DATA ELFDATA2LSB +#define ARCH_ELF_MACHINE_OK(x) ((x)==EM_ARM) +typedef Elf32_Ehdr Elf_ehdr; +typedef Elf32_Phdr Elf_phdr; diff --git a/arm/sys_info.c b/arm/sys_info.c new file mode 100644 index 0000000..45dd44f --- /dev/null +++ b/arm/sys_info.c @@ -0,0 +1,35 @@ +/* + * This file is part of FILO. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <libpayload.h> +#include <config.h> +#include <sys_info.h> +#define DEBUG_THIS CONFIG_DEBUG_SYS_INFO +#include <debug.h> + +void collect_sys_info(struct sys_info *info) +{ + // Nothing yet +} + +const char *get_cb_version() +{ + const char *cb_version = lib_sysinfo.cb_version ? + lib_sysinfo.cb_version : "<unknown version>"; + + return cb_version; +} diff --git a/main/grub/builtins.c b/main/grub/builtins.c index 58d6855..f53fe79 100644 --- a/main/grub/builtins.c +++ b/main/grub/builtins.c @@ -1030,6 +1030,7 @@ static struct builtin builtin_lock = { }; #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI static int lspci_indent = 0; static void lspci_scan_bus(int bus) { @@ -1139,6 +1140,7 @@ static struct builtin builtin_lspci = { "Show PCI devices or dump PCI config space" }; #endif +#endif #ifdef CONFIG_USE_MD5_PASSWORDS /* md5crypt */ @@ -1194,6 +1196,7 @@ static struct builtin builtin_md5crypt = { #endif /* CONFIG_USE_MD5_PASSWORDS */ #if CONFIG_DEVELOPER_TOOLS +#if CONFIG_TARGET_I386 /* nvram */ static int nvram_func(char *arg, int flags) { @@ -1256,6 +1259,7 @@ static struct builtin builtin_nvram = { "image on the next boot." }; #endif +#endif /* password */ static int password_func(char *arg, int flags) @@ -1561,6 +1565,7 @@ static struct builtin builtin_serial = { }; #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI static int setpci_func(char *arg, int flags) { char *walk = arg; @@ -1716,6 +1721,7 @@ static struct builtin builtin_setpci = { "Show/change PCI config space values" }; #endif +#endif /* terminal */ static int terminal_func(char *arg, int flags) @@ -1945,14 +1951,18 @@ struct builtin *builtin_table[] = { &builtin_keymap, &builtin_lock, #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI &builtin_lspci, #endif +#endif #ifdef CONFIG_USE_MD5_PASSWORDS &builtin_md5crypt, #endif #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_TARGET_I386 &builtin_nvram, #endif +#endif &builtin_password, &builtin_pause, &builtin_poweroff, @@ -1963,8 +1973,10 @@ struct builtin *builtin_table[] = { &builtin_root, &builtin_serial, #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI &builtin_setpci, #endif +#endif &builtin_terminal, &builtin_timeout, &builtin_title, diff --git a/main/grub/grub.c b/main/grub/grub.c index 2c8595b..67efdb6 100644 --- a/main/grub/grub.c +++ b/main/grub/grub.c @@ -47,6 +47,12 @@ static char configs[16384]; int flashrom_lockdown = 1; #endif +/* get_option() is currently only implemented on x86 */ +int __attribute__((weak)) get_option(void *dest, const char *name) +{ + return 1; +} + int using_grub_interface = 0; #define ENTER '\r'

1 0

Patch set updated for filo: Point to the correct libpayload path
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14355 -gerrit commit 7f23a5adda199812a4f35c51a054bb019a85afd0 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 13 16:23:48 2016 -0700 Point to the correct libpayload path libpayload is not standalone, so assume it lives under coreboot to make out of the box builds easier. Change-Id: Ib6240e7459a7e56f911c01e1ebe9f535cc0e50ad Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2b7edb6..39e477b 100644 --- a/Makefile +++ b/Makefile @@ -26,7 +26,7 @@ export obj := $(src)/build export objk := $(src)/build/util/kconfig ifndef LIBCONFIG_PATH - LIBCONFIG_PATH := $(src)/../libpayload +LIBCONFIG_PATH := $(src)/../coreboot/payloads/libpayload endif export LIBCONFIG_PATH

1 0

Patch set updated for coreboot: lib/cbfs: Use fmap derived information about the COREBOOT region
by Patrick Georgi 03 May '16

03 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14572 -gerrit commit d6e410bb22339c5d3cc324086a1437b2e00c0ab1 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 17:22:29 2016 +0800 lib/cbfs: Use fmap derived information about the COREBOOT region It used to use CONFIG_CBFS_SIZE. The plan is that CBFS_SIZE only informs default*.fmd generation, while everything else derives its information from there. Also document the existing assumption that boot media should access the COREBOOT region (and not any other potentially existing fmap region containing a CBFS). Change-Id: I08254e4510f71edf99c2c8b56ac8f92008727c4a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/lib/Makefile.inc | 7 +++++++ src/lib/cbfs.c | 9 +++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 3352a30..4c6a395 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -179,6 +179,13 @@ $(call src-to-obj,smm,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h +$(call src-to-obj,bootblock,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,romstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,ramstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,smm,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,verstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h +$(call src-to-obj,postcar,$(dir)/cbfs.c) : $(obj)/fmap_config.h + romstage-y += bootmode.c ramstage-y += bootmode.c verstage-y += bootmode.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index e1626d7..764a6f7 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -25,6 +25,8 @@ #include <symbols.h> #include <timestamp.h> +#include "fmap_config.h" + #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) #if IS_ENABLED(CONFIG_DEBUG_CBFS) @@ -215,6 +217,7 @@ out: return 0; } +/* This only supports the "COREBOOT" fmap region. */ static int cbfs_master_header_props(struct cbfs_props *props) { struct cbfs_header header; @@ -227,13 +230,15 @@ static int cbfs_master_header_props(struct cbfs_props *props) if (bdev == NULL) return -1; + size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; + /* Find location of header using signed 32-bit offset from * end of CBFS region. */ - offset = CONFIG_CBFS_SIZE - sizeof(int32_t); + offset = fmap_top - sizeof(int32_t); if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) return -1; - offset = CONFIG_CBFS_SIZE + rel_offset; + offset = fmap_top + rel_offset; if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) return -1;

1 0

Patch set updated for filo: Add ARM support
by Stefan Reinauer 03 May '16

03 May '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14370 -gerrit commit 421451f7cd8af3c374daa8d870eb1e8c88240235 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 14 15:48:17 2016 -0700 Add ARM support Change-Id: I9325f6df06cf85ecd77abef5c0a7b4d2742466f4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Kconfig | 19 +++++++++++++++---- Makefile | 6 ++++-- arm/Makefile.inc | 20 ++++++++++++++++++++ arm/elf.c | 29 +++++++++++++++++++++++++++++ arm/include/arch/elf.h | 5 +++++ arm/sys_info.c | 35 +++++++++++++++++++++++++++++++++++ main/grub/builtins.c | 12 ++++++++++++ main/grub/grub.c | 6 ++++++ 8 files changed, 126 insertions(+), 6 deletions(-) diff --git a/Kconfig b/Kconfig index cc48bd3..21a718d 100644 --- a/Kconfig +++ b/Kconfig @@ -4,13 +4,21 @@ mainmenu "FILO Configuration" -# When (if) we support multiple architectures, this will become an option. +choice + prompt "Build for architecture" + default TARGET_I386 + config TARGET_I386 - bool - default y + bool "x86" + +config TARGET_ARM + bool "ARM" + +endchoice config MULTIBOOT_IMAGE bool "Include a MultiBoot header" + depends on TARGET_I386 default y help Including a MultiBoot header makes FILO chainloadable by MultiBoot @@ -103,6 +111,7 @@ menu "Drivers" config IDE_DISK bool "IDE DISK support" + depends on TARGET_I386 default y help Driver for hard disk, CompactFlash, and CD-ROM on IDE bus @@ -138,6 +147,7 @@ config PCMCIA_CF config IDE_NEW_DISK bool "New IDE driver" + depends on TARGET_I386 default n depends on !IDE_DISK help @@ -165,6 +175,7 @@ config FLASH_DISK config SUPPORT_PCI bool "PCI support" default y + depends on TARGET_I386 config PCI_BRUTE_SCAN bool "Scan all PCI busses" @@ -234,7 +245,7 @@ config FSYS_ISO9660 config ELTORITO bool "El Torito bootable CDROMs" default y - depends on FSYS_ISO9660 + depends on FSYS_ISO9660 && TARGET_I386 help Support for boot disk image in bootable CD-ROM (El Torito) diff --git a/Makefile b/Makefile index 39e477b..1a9430d 100644 --- a/Makefile +++ b/Makefile @@ -81,6 +81,8 @@ $(if $(wildcard .xcompile),,$(shell bash util/xcompile/xcompile > .xcompile)) include .xcompile ARCH-$(CONFIG_TARGET_I386) := x86_32 +ARCH-$(CONFIG_TARGET_ARM) := arm + CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) @@ -104,6 +106,7 @@ LPGCC = $(LIBPAYLOAD_PREFIX)/bin/lpgcc LPAS = $(LIBPAYLOAD_PREFIX)/bin/lpas ARCHDIR-$(CONFIG_TARGET_I386) := x86 +ARCHDIR-$(CONFIG_TARGET_ARM) := arm CPPFLAGS := -nostdinc -imacros $(obj)/config.h CPPFLAGS += -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y) @@ -116,8 +119,7 @@ CFLAGS += $(call cc-option, -fno-stack-protector,) LIBS := $(LIBPAYLOAD) $(LIBGCC) -SUBDIRS-y += main/ fs/ drivers/ -SUBDIRS-$(CONFIG_TARGET_I386) += x86/ +SUBDIRS-y += main fs drivers $(ARCHDIR-y) $(foreach subdir,$(SUBDIRS-y),$(eval include $(subdir)/Makefile.inc)) diff --git a/arm/Makefile.inc b/arm/Makefile.inc new file mode 100644 index 0000000..8009ec2 --- /dev/null +++ b/arm/Makefile.inc @@ -0,0 +1,20 @@ +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +TARGETS-$(CONFIG_TARGET_ARM) += arm/sys_info.o arm/elf.o + diff --git a/arm/elf.c b/arm/elf.c new file mode 100644 index 0000000..5db5227 --- /dev/null +++ b/arm/elf.c @@ -0,0 +1,29 @@ +/* + * This file is part of FILO. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +void relocate(void) +{ + // Not supported +} + +u32 start_elf(u32 entry_point, u32 param) +{ + // Not supported + return 0; +} diff --git a/arm/include/arch/elf.h b/arm/include/arch/elf.h new file mode 100644 index 0000000..2a5bbbf --- /dev/null +++ b/arm/include/arch/elf.h @@ -0,0 +1,5 @@ +#define ARCH_ELF_CLASS ELFCLASS32 +#define ARCH_ELF_DATA ELFDATA2LSB +#define ARCH_ELF_MACHINE_OK(x) ((x)==EM_ARM) +typedef Elf32_Ehdr Elf_ehdr; +typedef Elf32_Phdr Elf_phdr; diff --git a/arm/sys_info.c b/arm/sys_info.c new file mode 100644 index 0000000..45dd44f --- /dev/null +++ b/arm/sys_info.c @@ -0,0 +1,35 @@ +/* + * This file is part of FILO. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <libpayload.h> +#include <config.h> +#include <sys_info.h> +#define DEBUG_THIS CONFIG_DEBUG_SYS_INFO +#include <debug.h> + +void collect_sys_info(struct sys_info *info) +{ + // Nothing yet +} + +const char *get_cb_version() +{ + const char *cb_version = lib_sysinfo.cb_version ? + lib_sysinfo.cb_version : "<unknown version>"; + + return cb_version; +} diff --git a/main/grub/builtins.c b/main/grub/builtins.c index 58d6855..f53fe79 100644 --- a/main/grub/builtins.c +++ b/main/grub/builtins.c @@ -1030,6 +1030,7 @@ static struct builtin builtin_lock = { }; #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI static int lspci_indent = 0; static void lspci_scan_bus(int bus) { @@ -1139,6 +1140,7 @@ static struct builtin builtin_lspci = { "Show PCI devices or dump PCI config space" }; #endif +#endif #ifdef CONFIG_USE_MD5_PASSWORDS /* md5crypt */ @@ -1194,6 +1196,7 @@ static struct builtin builtin_md5crypt = { #endif /* CONFIG_USE_MD5_PASSWORDS */ #if CONFIG_DEVELOPER_TOOLS +#if CONFIG_TARGET_I386 /* nvram */ static int nvram_func(char *arg, int flags) { @@ -1256,6 +1259,7 @@ static struct builtin builtin_nvram = { "image on the next boot." }; #endif +#endif /* password */ static int password_func(char *arg, int flags) @@ -1561,6 +1565,7 @@ static struct builtin builtin_serial = { }; #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI static int setpci_func(char *arg, int flags) { char *walk = arg; @@ -1716,6 +1721,7 @@ static struct builtin builtin_setpci = { "Show/change PCI config space values" }; #endif +#endif /* terminal */ static int terminal_func(char *arg, int flags) @@ -1945,14 +1951,18 @@ struct builtin *builtin_table[] = { &builtin_keymap, &builtin_lock, #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI &builtin_lspci, #endif +#endif #ifdef CONFIG_USE_MD5_PASSWORDS &builtin_md5crypt, #endif #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_TARGET_I386 &builtin_nvram, #endif +#endif &builtin_password, &builtin_pause, &builtin_poweroff, @@ -1963,8 +1973,10 @@ struct builtin *builtin_table[] = { &builtin_root, &builtin_serial, #ifdef CONFIG_DEVELOPER_TOOLS +#ifdef CONFIG_SUPPORT_PCI &builtin_setpci, #endif +#endif &builtin_terminal, &builtin_timeout, &builtin_title, diff --git a/main/grub/grub.c b/main/grub/grub.c index 2c8595b..5e2364d 100644 --- a/main/grub/grub.c +++ b/main/grub/grub.c @@ -47,6 +47,12 @@ static char configs[16384]; int flashrom_lockdown = 1; #endif +/* get_option() is currently only implemented on x86 */ +int __attribute__((weak)) get_option(void *dest, const char *name) +{ + return 1; +} + int using_grub_interface = 0; #define ENTER '\r'

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Abhay Kumar 03 May '16

03 May '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 34839b2ef9bccf91d67128389aa79862ee0c4801 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 4 + src/drivers/intel/fsp2_0/graphics.c | 36 ++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/silicon_init.c | 2 +- src/soc/intel/apollolake/acpi.c | 85 +++++++++++- src/soc/intel/apollolake/include/soc/pci_ids.h | 10 ++ src/soc/intel/common/gma.h | 182 +++++++++++++++++++++++++ 7 files changed, 312 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 19e04f7..d1325bf 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -3,4 +3,8 @@ config PLATFORM_USES_FSP2_0 help Include FSP 2.0 wrappers and functionality +config DISPLAY_VBT + bool "Display Video BIOS Table (VBT)" + default n + diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..db20222 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -13,6 +13,7 @@ #include <cbfs.h> #include <console/console.h> #include <fsp/util.h> +#include <lib.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -93,13 +94,36 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) return CB_SUCCESS; } -uintptr_t fsp_load_vbt(void) +uintptr_t fsp_load_vbt() { - void *vbt; + size_t vbt_size; + struct cbfsf file_desc; + union { + optionrom_vbt_t *data; + uint32_t *signature; + } vbt; - vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); - if (!vbt) - printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + if (cbfs_boot_locate(&file_desc,"vbt.bin", NULL)) + printk(BIOS_NOTICE, "Could not locate a VBT file in in CBFS\n"); - return (uintptr_t)vbt; + vbt_size = region_device_sz(&file_desc.data); + vbt.data = malloc(vbt_size); + cbfs_file_data((void *)vbt.data, &file_desc); + vbt.data = rdev_mmap(&file_desc.data, 0, vbt_size); + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return (uintptr_t)NULL; + } + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + hexdump(vbt.data,*vbt_size ); + printk(BIOS_DEBUG, "\n"); +#endif + + rdev_munmap(&file_desc.data, vbt.data); + return (uintptr_t)vbt.data; } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..0497ceb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,7 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 66043c8..21a3570 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -44,7 +44,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) hdr->silicon_init_entry_offset); status = silicon_init(&upd); - printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + free((void *)&upd.FspsConfig.GraphicsConfigPtr); return status; } diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a5d1dfa..bbf2595 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,12 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +41,74 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + optionrom_vbt_t *vbt; + vbt = (optionrom_vbt_t *)fsp_load_vbt(); + + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); + free(vbt); +} + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8KiB */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (uintptr_t)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,7 +200,16 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); + current = acpi_write_hpet(device, current, rsdp); + + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); + } static void acpi_create_gnvs(struct global_nvs_t *gnvs) diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 0790c6e..2c5ad4c 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -42,4 +42,14 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + +/* System Agent Devices */ +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD) + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..3a1ebd7 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

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coreboot-gerrit May 2016