coreboot-gerrit May 2016

coreboot-gerrit@coreboot.org

1 participants
1843 discussions

New patch to review for coreboot: fmaptool: Export some fmap knowledge to the build environment
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14571 -gerrit commit d1d90185fa05de08273153199def7da189d4aa50 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 17:02:53 2016 +0800 fmaptool: Export some fmap knowledge to the build environment By exporting base and offset of CBFS-formatted fmap regions, the code can use these when it's not prudent to do a runtime lookup. Change-Id: I20523b5cea68880af4cb1fcea4b37bb8ac2a23db Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/fmaptool.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/util/cbfstool/fmaptool.c b/util/cbfstool/fmaptool.c index 1eda822..5aafffd 100644 --- a/util/cbfstool/fmaptool.c +++ b/util/cbfstool/fmaptool.c @@ -101,6 +101,20 @@ static bool write_header(const char *out_fname, fputs("#ifndef FMAPTOOL_GENERATED_HEADER_H_\n", header); fputs("#define FMAPTOOL_GENERATED_HEADER_H_\n\n", header); fprintf(header, "#define %s %#x\n\n", HEADER_FMAP_OFFSET, fmap_offset); + + /* also add defines for each CBFS-carrying fmap region: base and size */ + cbfs_section_iterator_t cbfs_it = cbfs_sections_iterator(); + while (cbfs_it) { + const struct flashmap_descriptor *item = + cbfs_sections_iterator_deref(cbfs_it); + assert(item->offset_known && item->size_known); + fprintf(header, "#define ___FMAP__%s_BASE 0x%x\n", + item->name, item->offset); + fprintf(header, "#define ___FMAP__%s_SIZE 0x%x\n", + item->name, item->size); + cbfs_sections_iterator_advance(&cbfs_it); + } + fputs("#endif\n", header); fclose(header);

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New patch to review for coreboot: build system: rename fmap.h to fmap_config.h
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14570 -gerrit commit d5f1b21b1090682d74b7036f6aa3b6b0152a5ac7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 16:50:31 2016 +0800 build system: rename fmap.h to fmap_config.h There's an in-tree fmap.h, and the file generated by fmaptool is likely used in tandem with it. To avoid problems, rename the generated file (which so far isn't used). Change-Id: I95dfde513a7f78677cf18ecd7ce8745e40af316b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0fb7a3d..812f998 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -700,12 +700,12 @@ $(obj)/fmap.fmd: $(CONFIG_FMDFILE) $(obj)/config.h endif # ifeq ($(CONFIG_FMDFILE),) # generated at the same time as fmap.fmap -$(obj)/fmap.h: $(obj)/fmap.fmap +$(obj)/fmap_config.h: $(obj)/fmap.fmap $(obj)/fmap.desc: $(obj)/fmap.fmap $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) - echo " FMAP $(FMAPTOOL) -h $(obj)/fmap.h $< $@" - $(FMAPTOOL) -h $(obj)/fmap.h -R $(obj)/fmap.desc $< $@ + echo " FMAP $(FMAPTOOL) -h $(obj)/fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/fmap_config.h -R $(obj)/fmap.desc $< $@ $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)

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New patch to review for coreboot: arch/x86: Drop CBFS_BASE_ADDRESS
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14569 -gerrit commit a4d63b150048133d099dde12e39022b5c7ce8018 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 16:32:02 2016 +0800 arch/x86: Drop CBFS_BASE_ADDRESS It's unused. Change-Id: I50af2b50d2c5a7a24afe9099c5c01d17ce54a6c9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/x86/Makefile.inc | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 64d9892..a363430 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,9 +47,6 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE)) mbi.bin-type := mbi -## Calculate the base address of CBFS for later comparisons -CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_SIZE)) 1) - ############################################################################### # common support for early assembly includes ###############################################################################

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New patch to review for coreboot: southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFS
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14568 -gerrit commit 4203b229ad5564ce1c33888f1b22b7f716023349 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 16:31:31 2016 +0800 southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFS It's unused. Change-Id: I853702e40dcab9f193b2a3de7deeec80ab1d25f0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 - src/southbridge/amd/pi/hudson/Makefile.inc | 1 - 2 files changed, 2 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index a9b3bbf..77afc51 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -37,7 +37,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-multiply, $(CONFIG_COREBOOT_ROMSIZE_KB) 1024)) 0x20000 1) HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) -HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 5b5c851..291e25f 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -69,7 +69,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-multiply, $(CONFIG_COREBOOT_ROMSIZE_KB) 1024)) 0x20000 1) HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) -HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) ## ifeq ($(CONFIG_HUDSON_PSP), y)

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New patch to review for coreboot: build system: remove CBFSTOOL_PRE1_OPTS
by Patrick Georgi 02 May '16

02 May '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14567 -gerrit commit 47c0d9aa7a1b2c4fa177631eae15683211558222 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon May 2 16:28:18 2016 +0800 build system: remove CBFSTOOL_PRE1_OPTS It isn't used anymore. Change-Id: Ie554d1dd87ae3f55547466e484c0864e55c9d102 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm/Makefile.inc | 4 ---- src/arch/arm64/Makefile.inc | 4 ---- src/arch/mips/Makefile.inc | 4 ---- src/arch/power8/Makefile.inc | 2 -- src/arch/riscv/Makefile.inc | 2 -- src/arch/x86/Makefile.inc | 5 ----- 6 files changed, 21 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index d9c88c0..2742414 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -21,10 +21,6 @@ # ARM specific options ############################################################################### -ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) -CBFSTOOL_PRE1_OPTS = -m arm -s $(CONFIG_CBFS_SIZE) -endif - ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y) check-ramstage-overlap-regions += postram_cbfs_cache stack ttb endif diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index dffdd9c..ece35a6 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -29,10 +29,6 @@ subdirs-y += armv8/ # ARM specific options ################################################################################ -ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) -CBFSTOOL_PRE1_OPTS = -m arm64 -s $(CONFIG_CBFS_SIZE) -endif - ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) check-ramstage-overlap-regions += postram_cbfs_cache stack ttb endif diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 0901388..cd474ee 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -18,10 +18,6 @@ # MIPS specific options ############################################################################### -ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) -CBFSTOOL_PRE1_OPTS = -m mips -s $(CONFIG_CBFS_SIZE) -endif - ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) check-ramstage-overlap-regions += stack endif diff --git a/src/arch/power8/Makefile.inc b/src/arch/power8/Makefile.inc index 55c5470..98f9db1 100644 --- a/src/arch/power8/Makefile.inc +++ b/src/arch/power8/Makefile.inc @@ -71,8 +71,6 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) romstage-c-ccopts += $(power8_flags) romstage-S-ccopts += $(power8_asm_flags) -CBFSTOOL_PRE1_OPTS = -v -m power8 -s $(CONFIG_CBFS_SIZE) - endif ################################################################################ diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4abaf58..6784d9b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -75,8 +75,6 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) -CBFSTOOL_PRE1_OPTS = -v -m riscv -s $(CONFIG_CBFS_SIZE) - endif ################################################################################ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 10664c3..64d9892 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,11 +47,6 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE)) mbi.bin-type := mbi -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -CBFSTOOL_PRE1_OPTS = -m x86 -s $(CONFIG_ROM_SIZE) \ - -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) -endif - ## Calculate the base address of CBFS for later comparisons CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_SIZE)) 1)

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Patch merged into coreboot/master: x86/memlayout.h: Do not include data/bss sections in C_ENVIRONMENT_BOOTBLOCK
by gerrit＠coreboot.org 02 May '16

02 May '16

the following patch was just integrated into master: commit 4c76ab678ab892f30c047881c77e64cc3308f85b Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Apr 27 22:06:47 2016 -0700 x86/memlayout.h: Do not include data/bss sections in C_ENVIRONMENT_BOOTBLOCK C_ENVIRONMENT_BOOTBLOCK on x86 is like romstage and uses cache-as-ram separately. It does not use any data/bss sections. Change-Id: I8957f467f01e754fa2d95783466a01daa6c4e51a Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/14533 for details. -gerrit

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Patch set updated for coreboot: xcompile: test if gcc is really available
by Stefan Tauner 01 May '16

01 May '16

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14563 -gerrit commit 190144ce5aec97ade557fde2de3d8002e1e3ba93 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun May 1 19:41:28 2016 +0200 xcompile: test if gcc is really available Just because an 'as' with a certain prefix is available does not guarantee that a 'gcc' with the same prefix is available as well. Without a check detect_compiler_runtime() would try to execute an unavailable binary and print something like this: .../xcompile: line 218: arm-linux-gnueabi-gcc: command not found Change-Id: Icbadfeb2860152f7cf7696a9122521d0d881f3aa Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/xcompile/xcompile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 8e1cd10..13a0e8f 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -149,9 +149,6 @@ testas() { local obj_arch="$(expr "$obj_type" : '.*format $.[a-z0-9-]*$')" [ "$obj_arch" = "$full_arch" ] || return 1 - # Architecture matched. - GCCPREFIX="$gccprefix" - unset ASFLAGS LDFLAGS unset CFLAGS_GCC CFLAGS_CLANG @@ -414,10 +411,13 @@ test_architecture() { for gccprefix in $search ""; do program_exists "${gccprefix}as" || continue for endian in $TENDIAN ""; do + { testas "$gccprefix" "$TWIDTH" "$TBFDARCH" \ + "" "$endian" || testas "$gccprefix" "$TWIDTH" "$TBFDARCH" \ - "" "$endian" && break 3 - testas "$gccprefix" "$TWIDTH" "$TBFDARCH" \ - "TRUE" "$endian" && break 3 + "TRUE" "$endian" ; } && \ + testcc "${gccprefix}gcc" "$CFLAGS_GCC" && \ + GCCPREFIX="$gccprefix" && \ + break 3 done done done

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Patch set updated for coreboot: soc/intel/quark: Add script time delay support
by Leroy P Leahy 01 May '16

01 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14555 -gerrit commit 45635e50b2eb9659477e18908272aff8f5b61878 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 16:36:02 2016 -0700 soc/intel/quark: Add script time delay support Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 6 ++++++ src/soc/intel/quark/reg_access.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index ddca668..63624a3 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,7 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#include <delay.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> @@ -25,6 +26,7 @@ enum { USB_PHY_REGS = 1, SOC_UNIT_REGS, RMU_TEMP_REGS, + TIME_DELAY, }; enum { @@ -78,6 +80,10 @@ enum { #define REG_SOC_UNIT_XOR(reg_, value_) \ REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) +/* Time delays */ +#define TIME_DELAY_USEC(value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, TIME_DELAY) + /* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 230858a..1bcbb5e 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -157,6 +157,15 @@ static void reg_write(struct reg_script_context *ctx) reg_soc_unit_write(step->reg, (uint32_t)step->value); break; + case TIME_DELAY: + if (display) { + printk(BIOS_INFO, "Delay %lld uSec\n", step->value); + reg_script_set_display_features( + REG_SCRIPT_DISPLAY_NOTHING); + } + udelay(step->value); + break; + case USB_PHY_REGS: if (display) printk(BIOS_INFO, "USB PHY: ");

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Patch set updated for coreboot: soc/intel/quark: Add temperature sensor support
by Leroy P Leahy 01 May '16

01 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14565 -gerrit commit cd85b51a2f2b09131616269626e333ac9c25b50c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 08:48:52 2016 -0700 soc/intel/quark: Add temperature sensor support Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 93 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 48 ++++++++++++++ src/soc/intel/quark/reg_access.c | 58 +++++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index eb326d7..4219ccd 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -17,9 +17,102 @@ #include <console/console.h> #include <device/device.h> #include <soc/ramstage.h> +#include <soc/reg_access.h> + +/* Cat Trip Clear value must be less than Cat Trip Set value */ +#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 +#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 + +static const struct reg_script init_script[] = { + + /* Setup RMU Thermal sensor registers for Ratiometric mode. */ + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, + ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK + | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK + | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN + | B_TSCGF1_CONFIG_IBGEN + | B_TSCGF1_CONFIG_IBGCHOPEN), + ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) + | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) + | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) + | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGEN_BP) + | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, + ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK + | B_TSCGF2_CONFIG2_ISPARECTRL_MASK + | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), + ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) + | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE + << B_TSCGF2_CONFIG2_ISPARECTRL_BP) + | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, + ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK + | B_TSCGF2_CONFIG_IDSTIMING_MASK), + ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE + << B_TSCGF2_CONFIG_IDSCONTROL_BP) + | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE + << B_TSCGF2_CONFIG_IDSTIMING_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, + V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE + << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), + + /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ + + /* Setup Catastrophic Trip point. + * + * Trip Register fields are 8-bit temperature values of granularity 1 + * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds + * to 205 degrees C. + * + * Add 50 to values to Celsius values to get values for register fields. + */ + REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, + ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), + (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) + << TS_CAT_TRIP_SET_THOLD_BP) + | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) + << TS_CAT_TRIP_CLEAR_THOLD_BP))), + + /* To enable the TS do the following: + * 1) Take the TS out of reset by setting itsrst to 0x0. + * 2) Enable the TS using RMU Thermal sensor mode register. + */ + REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSRST), + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), + + /* Lock all RMU Thermal sensor control & trip point registers. */ + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), + REG_SCRIPT_END +}; static void chip_init(void *chip_info) { + /* Validate the temperature settings */ + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + + /* Set the temperature settings */ + reg_script_run(init_script); + ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + & (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + == (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 934c75d..ddca668 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -18,10 +18,13 @@ #include <fsp/util.h> #include <reg_script.h> +#include <soc/IntelQNCConfig.h> #include <soc/QuarkNcSocId.h> enum { USB_PHY_REGS = 1, + SOC_UNIT_REGS, + RMU_TEMP_REGS, }; enum { @@ -32,6 +35,50 @@ enum { #define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) + +/* RMU temperature register access macros */ +#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + RMU_TEMP_REGS) +#define REG_RMU_TEMP_READ(reg_) \ + REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0) +#define REG_RMU_TEMP_WRITE(reg_, value_) \ + REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_RMU_TEMP_AND(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, value_, 0) +#define REG_RMU_TEMP_RMW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_RXW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_OR(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_) +#define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \ + REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_RMU_TEMP_XOR(reg_, value_) \ + REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_) + +/* Temperature sensor access macros */ +#define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + SOC_UNIT_REGS) +#define REG_SOC_UNIT_READ(reg_) \ + REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0) +#define REG_SOC_UNIT_WRITE(reg_, value_) \ + REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_SOC_UNIT_AND(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, value_, 0) +#define REG_SOC_UNIT_RMW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_RXW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_OR(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_) +#define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \ + REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_SOC_UNIT_XOR(reg_, value_) \ + REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) + +/* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ USB_PHY_REGS) @@ -56,5 +103,6 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_rmu_temp_read(uint32_t reg_address); #endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index c5f040f..230858a 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -45,6 +45,40 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } +uint32_t reg_rmu_temp_read(uint32_t reg_address) +{ + /* Read the RMU temperature register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address); + return mdr_read(); +} + +static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value) +{ + /* Write the RMU temperature register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address); +} + +static uint32_t reg_soc_unit_read(uint32_t reg_address) +{ + /* Read the temperature sensor register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_soc_unit_write(uint32_t reg_address, uint32_t value) +{ + /* Write the temperature sensor register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); +} + static uint32_t reg_usb_read(uint32_t reg_address) { /* Read the USB register */ @@ -77,6 +111,18 @@ static uint64_t reg_read(struct reg_script_context *ctx) reg_script_set_display_features(REG_SCRIPT_DISPLAY_NOTHING); return 0; + case RMU_TEMP_REGS: + if (display) + printk(BIOS_INFO, "RMU TEMP: "); + value = reg_rmu_temp_read(step->reg); + break; + + case SOC_UNIT_REGS: + if (display) + printk(BIOS_INFO, "SOC Unit: "); + value = reg_soc_unit_read(step->reg); + break; + case USB_PHY_REGS: if (display) printk(BIOS_INFO, "USB PHY: "); @@ -99,6 +145,18 @@ static void reg_write(struct reg_script_context *ctx) reg_script_set_display_features(REG_SCRIPT_DISPLAY_NOTHING); return; + case RMU_TEMP_REGS: + if (display) + printk(BIOS_INFO, "RMU TEMP: "); + reg_rmu_temp_write(step->reg, (uint32_t)step->value); + break; + + case SOC_UNIT_REGS: + if (display) + printk(BIOS_INFO, "SOC Unit: "); + reg_soc_unit_write(step->reg, (uint32_t)step->value); + break; + case USB_PHY_REGS: if (display) printk(BIOS_INFO, "USB PHY: ");

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Patch set updated for coreboot: soc/intel/quark: Add IntelQNCConfig.h from EDK-II
by Leroy P Leahy 01 May '16

01 May '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14497 -gerrit commit e29c1b15fef0c54907bd30cd5f95fb2852713def Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 17:27:44 2016 -0700 soc/intel/quark: Add IntelQNCConfig.h from EDK-II Add the EDK-II Quark file IntelQNCConfig.h. This adds the definitions for the temperature sensor. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/IntelQNCConfig.h | 73 ++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/src/soc/intel/quark/include/soc/IntelQNCConfig.h b/src/soc/intel/quark/include/soc/IntelQNCConfig.h new file mode 100644 index 0000000..0375397 --- /dev/null +++ b/src/soc/intel/quark/include/soc/IntelQNCConfig.h @@ -0,0 +1,73 @@ +/** @file +Some configuration of QNC Package + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __INTEL_QNC_CONFIG_H__ +#define __INTEL_QNC_CONFIG_H__ + +// +// QNC Fixed configurations. +// + +// +// Memory arbiter fixed config values. +// +#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\ + (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \ + (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \ + (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \ + (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \ + )) + +// +// Memory Manager fixed config values. +// +#define V_DRAM_NON_HOST_RQ_LIMIT 2 + +// +// RMU Thermal config fixed config values for TS in Vref Mode. +// +#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04 +#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01 +#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1 +#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b +#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34 + +// +// RMU Thermal config fixed config values for TS in Ratiometric mode. +// +#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04 +#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02 +#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1 +#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f +#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001 +#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01 +#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00 +#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0 +#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0 +#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8 +#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17 + +// +// iCLK fixed config values. +// +#define V_MUXTOP_FLEX2 3 +#define V_MUXTOP_FLEX1 1 + +// +// PCIe Root Port fixed config values. +// +#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER) + +#endif

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coreboot-gerrit May 2016