coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

1 participants
1270 discussions

Patch set updated for coreboot: mb/samsung/lumpy/romstage: read SPD data of removable DIMM
by Patrick Rudolph 08 Apr '16

08 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14278 -gerrit commit 8c88c6f25d5914c6223b39656b01f52686f2f3b5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Apr 7 18:51:12 2016 +0200 mb/samsung/lumpy/romstage: read SPD data of removable DIMM The removable DIMM SPD data wasn't read. As a result the system only uses the 2GB onboard memory and the GNU Linux kernel paniced in acpi_ds_build_internal_package_obj. Read the SPD and allow native raminit and MRC blob to use the removable DIMM. The system is able to use the removable dimm and the kernel panic is gone. Change-Id: I30eed747f924cb0029de55d2ab85c5a94075dc1b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/samsung/lumpy/romstage.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 650c8d7..8a37356 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -216,6 +216,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data->spd_data[0], locate_spd(), 256); + /* read removable dimm spd */ + read_spd(&pei_data->spd_data[2], 0x50); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -238,7 +240,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd) { - memcpy(&spd[0], locate_spd(), 128); + /* get onbard dimm spd */ + memcpy(&spd[0], locate_spd(), 256); + /* read removable dimm spd */ + read_spd(&spd[2], 0x50); } void mainboard_early_init(int s3resume)

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Patch set updated for coreboot: mb/samsung/lumpy/romstage: read SPD data of removable DIMM
by Patrick Rudolph 08 Apr '16

08 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14278 -gerrit commit 03b1ac8bbdb6d2f62c6fccbab3998644b0e61e4f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Apr 7 18:51:12 2016 +0200 mb/samsung/lumpy/romstage: read SPD data of removable DIMM The removable DIMM SPD data wasn't read. As a result the system only uses the 2GB onboard memory and showed strange behaviour when booting into GNU Linux. Read the SPD and allow native raminit and MRC blob to use the removable DIMM, too. Change-Id: I30eed747f924cb0029de55d2ab85c5a94075dc1b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/samsung/lumpy/romstage.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 650c8d7..8a37356 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -216,6 +216,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data->spd_data[0], locate_spd(), 256); + /* read removable dimm spd */ + read_spd(&pei_data->spd_data[2], 0x50); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -238,7 +240,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd) { - memcpy(&spd[0], locate_spd(), 128); + /* get onbard dimm spd */ + memcpy(&spd[0], locate_spd(), 256); + /* read removable dimm spd */ + read_spd(&spd[2], 0x50); } void mainboard_early_init(int s3resume)

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Patch set updated for coreboot: [Fixup]soc/intel/apollolake: Fix northbridge _CRS
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14288 -gerrit commit e9d5cae3670700134d7ebd271f11371c9a83f342 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Thu Apr 7 15:50:03 2016 -0700 [Fixup]soc/intel/apollolake: Fix northbridge _CRS Fix build break on current _CRS method with correct scope. Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 96 +++++++++++++-------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1349c6a..6ad96ec 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -19,18 +19,18 @@ Device (MCHC) { Name (_ADR, 0x00000000) /*Dev0 Func0 */ - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x60), - MCNF, 32, /* PCI MMCONF base */ - Offset (0xA8), - TUUD, 64, /* Top of Upper Used Memory */ - Offset(0xB4), - BGSM, 32, /* Base of Graphics Stolen Memory */ - Offset(0xBC), - TLUD, 32, /* Top of Low Useable DRAM */ - } + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } Name (MCRS, ResourceTemplate() { /* Bus Numbers */ @@ -76,51 +76,51 @@ Device (MCHC) NonCacheable, ReadWrite, 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02) -}) + }) -/* Current Resource Settings */ -Method (_CRS, 0, Serialized) -{ + /* Current Resource Settings */ + Method (_CRS, 0, Serialized) + { - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, ^PM01._MIN, PMIN) - CreateDwordField (MCRS, ^PM01._MAX, PMAX) - CreateDwordField (MCRS, ^PM01._LEN, PLEN) + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) - /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^MCHC.TLUD, 0xFFF00000, PMIN) - /* Read MMCONF base */ - And(^MCHC.MCNF, 0xF0000000, PMAX) + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCNF, 0xF0000000, PMAX) - /* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) - /* Find GFX resource area in GCRS */ - CreateDwordField(MCRS, ^STOM._MIN, GMIN) - CreateDwordField(MCRS, ^STOM._MAX, GMAX) - CreateDwordField(MCRS, ^STOM._LEN, GLEN) + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN) - /* Read BGSM */ - And(^MCHC.BGSM, 0xFFF00000, GMIN) + /* Read BGSM */ + And(^BGSM, 0xFFF00000, GMIN) - /* Read TOLUD */ - And(^MCHC.TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + /* Read TOLUD */ + And(^TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (^TUUD, Local0) - If (LLessEqual (Local0, 0x1000000000)) { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) + If (LLessEqual (Local0, 0x1000000000)) { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) - Return (MCRS) + Return (MCRS) + } } -} \ No newline at end of file

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New patch to review for coreboot: Makefile.inc: Don't run submodule init every build
by Martin Roth 07 Apr '16

07 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14259 -gerrit commit c8cdc6fbee38e5b3df657b04a71cc742b1d228c6 Author: Martin Roth <martinroth(a)google.com> Date: Tue Apr 5 11:09:22 2016 -0600 Makefile.inc: Don't run submodule init every build Currently the build tries to init the submodules with every build which leads to a lot of overhead. This turns the update into a target function which will only try to init the submodules if the submodule directory doesn't exist. Change-Id: I5c4a40d28f613b752751e3fc75bb55a60b6a802f Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 38 ++++++++++++++++++++++++++++---------- src/arch/arm64/Makefile.inc | 2 +- src/commonlib/Makefile.inc | 8 ++++++++ util/cbfstool/Makefile.inc | 2 +- util/nvidia/Makefile.inc | 4 ++-- util/nvramtool/Makefile.inc | 2 +- 6 files changed, 41 insertions(+), 15 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6be9d52..e3db0a8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -174,14 +174,6 @@ ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts += -fprofile-arcs -ftest-coverage endif -# try to fetch non-optional submodules if the source is under git -forgetthis:=$(if $(GIT),$(shell git submodule update --init)) -ifeq ($(CONFIG_USE_BLOBS),y) -# this is necessary because 3rdparty/blobs is update=none, and so is ignored -# unless explicitly requested and enabled through --checkout -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) -endif - ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) libverstage-c-deps:=$$(OPTION_TABLE_H) @@ -373,12 +365,38 @@ build-dirs: mkdir -p $(objcbfs) $(objgenerated) ####################################################################### +# try to fetch non-optional submodules if the source is under git + +SUBMODULES := \ + 3rdparty/vboot/.git \ + 3rdparty/arm-trusted-firmware/.git \ + 3rdparty/chromeec/.git \ + 3rdparty/blobs/.git \ + util/nvidia/cbootimage/.git + +submodules: $(SUBMODULES) + +3rdparty/vboot/.git 3rdparty/arm-trusted-firmware/.git 3rdparty/chromeec/.git util/nvidia/cbootimage/.git: +ifneq ($(GIT),) + git submodule update --init --checkout $(subst /.git,,$@) +endif + +3rdparty/blobs/.git: +ifeq ($(CONFIG_USE_BLOBS),y) +ifneq ($(GIT),) + git submodule update --init --checkout $(subst /.git,,$@) +endif +endif + +.PHONY: submodules + +####################################################################### # Build the tools CBFSTOOL:=$(objutil)/cbfstool/cbfstool FMAPTOOL:=$(objutil)/cbfstool/fmaptool RMODTOOL:=$(objutil)/cbfstool/rmodtool -$(obj)/cbfstool: $(CBFSTOOL) +$(obj)/cbfstool: $(CBFSTOOL) | submodules cp $< $@ $(obj)/fmaptool: $(FMAPTOOL) @@ -541,7 +559,7 @@ $(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.elf $(objcbfs)/%.bin: $(objcbfs)/%.raw.bin cp $< $@ -$(objcbfs)/%.elf: $(objcbfs)/%.debug +$(objcbfs)/%.elf: $(objcbfs)/%.debug | submodules $(eval class := $(call find-class,$(@F))) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cp $< $@.tmp diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index dffdd9c..32fbfa5 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -170,7 +170,7 @@ BL31_LDFLAGS := --emit-relocs BL31 := $(obj)/bl31.elf -$(BL31): $(obj)/build.h +$(BL31): $(obj)/build.h | submodules @printf " MAKE $(subst $(obj)/,,$(@))\n" CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ CFLAGS="$(BL31_CFLAGS)" \ diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 7c14f7c..fec86d9 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -25,3 +25,11 @@ verstage-y += lz4_wrapper.c romstage-y += lz4_wrapper.c ramstage-y += lz4_wrapper.c postcar-y += lz4_wrapper.c + +# cbfs.c needs the vboot submodule to be downloaded before it will compile +$(call src-to-obj,bootblock,$(dir)/cbfs.c) : submodules +$(call src-to-obj,romstage,$(dir)/cbfs.c) : submodules +$(call src-to-obj,ramstage,$(dir)/cbfs.c) : submodules +$(call src-to-obj,smm,$(dir)/cbfs.c) : submodules +$(call src-to-obj,verstage,$(dir)/cbfs.c) : submodules +$(call src-to-obj,postcar,$(dir)/cbfs.c) : submodules diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index f480616..e097d8e 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -109,7 +109,7 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/C/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< -$(objutil)/cbfstool/%.o: $(top)/3rdparty/vboot/firmware/2lib/%.c +$(objutil)/cbfstool/%.o: $$(top)/3rdparty/vboot/firmware/2lib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< diff --git a/util/nvidia/Makefile.inc b/util/nvidia/Makefile.inc index 133778f..db569d7 100644 --- a/util/nvidia/Makefile.inc +++ b/util/nvidia/Makefile.inc @@ -45,11 +45,11 @@ CBOOTIMAGE_FLAGS:=-Wall -std=c99 -O2 additional-dirs += $(sort $(dir $(CBOOTIMAGE_OBJS))) -$(objutil)/nvidia/cbootimage/%.o: util/nvidia/cbootimage/src/%.c +$(objutil)/nvidia/cbootimage/%.o: $$(top)/util/nvidia/cbootimage/src/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(CBOOTIMAGE_FLAGS) -c -o $@ $< -$(CBOOTIMAGE): $(CBOOTIMAGE_OBJS) +$(CBOOTIMAGE): $(CBOOTIMAGE_OBJS) | submodules printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(CBOOTIMAGE_FLAGS) -o $@.tmp $^ -lm mv $@.tmp $@ diff --git a/util/nvramtool/Makefile.inc b/util/nvramtool/Makefile.inc index 48f6d86..d78ec11 100644 --- a/util/nvramtool/Makefile.inc +++ b/util/nvramtool/Makefile.inc @@ -36,7 +36,7 @@ NVRAMTOOLLDFLAGS += -lregex -lwsock32 nvramtoolobj += win32mmap.o endif -$(objutil)/nvramtool $(objutil)/nvramtool/accessors $(objutil)/nvramtool/cli: +$(objutil)/nvramtool $(objutil)/nvramtool/accessors $(objutil)/nvramtool/cli: submodules mkdir -p $@ $(objutil)/nvramtool/%.o: $(top)/util/nvramtool/%.c

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Patch set updated for coreboot: soc/intel/apollolake: Override default to_flash_offset implementation
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14248 -gerrit commit a283efb01beff3d09a1eb4c38546375603fa70ad Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 3 13:16:36 2016 -0800 soc/intel/apollolake: Override default to_flash_offset implementation The default nvm_mmio_to_flash_offset() implementation used by NVM code in intel/common does not work on apollolake. As a result, provide the correct override. Change-Id: I01a94f90dfdd33586a4aac5c05dd8c73e8804437 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/mmap_boot.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 3625924..a618d4a 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -16,6 +16,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/intel/common/nvm.h> /* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */ #define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 128 * KiB) @@ -72,3 +73,10 @@ const struct cbfs_locator cbfs_master_header_locator = { .name = "IAFW Locator", .locate = iafw_boot_region_properties, }; + +uint32_t nvm_mmio_to_flash_offset(void *p) +{ + uintptr_t xlate_base; + xlate_base = VIRTUAL_ROM_BASE; + return (uintptr_t)p - xlate_base + CONFIG_IFD_BIOS_START; +}

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Patch set updated for coreboot: soc/intel/apollolake: Enabling using of MRC data when available
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14253 -gerrit commit 6419c4e12fedf256e45e1e80e9b15db53de7379d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Apr 4 16:38:46 2016 -0700 soc/intel/apollolake: Enabling using of MRC data when available Change-Id: Iee30a6efb8dcdd04affd5d1105a254781287e9e4 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index d24cdf8..4e800f7 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -23,6 +23,7 @@ #include <device/resource.h> #include <string.h> #include <soc/iomap.h> +#include <soc/intel/common/mrc_cache.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/romstage.h> @@ -78,10 +79,10 @@ static void disable_watchdog(void) asmlinkage void car_stage_entry(void) { - void *hob_list_ptr; - struct range_entry fsp_mem; - struct range_entry reg_car; + void *hob_list_ptr, *mrc_data; + struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; + size_t mrc_data_size; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -111,6 +112,15 @@ asmlinkage void car_stage_entry(void) /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); + /* Save MRC Data to CBMEM */ + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + { + /* TODO: treat MRC data as const */ + mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); + if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) + printk(BIOS_ERR, "Failed to stash MRC data\n"); + } + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -134,6 +144,9 @@ static void fill_console_params(struct FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { + const struct mrc_saved_data *mrc_cache; + struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -154,6 +167,18 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) */ mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; + + arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { + if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { + /* MRC cache found */ + arch_upd->NvsBufferPtr = (void *)mrc_cache->data; + arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + } else + printk(BIOS_DEBUG, "MRC cache was not found\n"); + } } __attribute__ ((weak))

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Patch set updated for coreboot: soc/intel/apollolake: Enable CACHE_MRC_SETTINGS
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14252 -gerrit commit 7625de1986b225d38b75888de4481d9967d8f568 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Mar 14 17:38:51 2016 -0700 soc/intel/apollolake: Enable CACHE_MRC_SETTINGS Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 30ee7e5..c911338 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -100,4 +100,8 @@ config ROMSTAGE_ADDR help The base address (in CAR) where romstage should be linked +config CACHE_MRC_SETTINGS + bool + default y + endif

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Patch set updated for coreboot: soc/intel/common/nvm: Allow overriding to_flash_offset() function
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14247 -gerrit commit e51ec14b711c0e32a8555d88b5d4539369c89772 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 3 10:58:30 2016 -0800 soc/intel/common/nvm: Allow overriding to_flash_offset() function On apollolake, the flash is memory-mapped differently, and the default MMIO to flash calculation does not produce correct results. While the long-term solution is to rewrite the NVM functionality to keep the flash offset as part of its context, as a temporary measure, allow overriding the to_flash_offset() function by declaring it weak. Change-Id: Ic54baeba2441a08cfe1a47e235747797f6efb59b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/common/nvm.c | 22 +++++++++++++++++----- src/soc/intel/common/nvm.h | 3 +++ 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index fe73408..e55638a 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -46,8 +46,20 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) +/* + * Convert memory mapped pointer to flash offset. + * + * This is weak because not every platforms memory-maps the NVM media in the + * same manner. This is a stop-gap solution. + * + * The root of the problem is that users of this API work in memory space for + * both reads and writes, but erase and write must be done in flash space. This + * also only works when the media is memory-mapped, which is no longer + * universally true. The long-term approach should be to rewrite this and its + * users to work in flash space, while using rdev_read() instead of rdev_mmap(). + */ +__attribute__((weak)) +uint32_t nvm_mmio_to_flash_offset(void *p) { return CONFIG_ROM_SIZE + (uintptr_t)p; } @@ -70,7 +82,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - return flash->erase(flash, to_flash_offset(start), size); + return flash->erase(flash, nvm_mmio_to_flash_offset(start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ @@ -78,7 +90,7 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - return flash->write(flash, to_flash_offset(start), size, data); + return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data); } /* Read flash status register to determine if write protect is active */ @@ -115,7 +127,7 @@ int nvm_protect(void *start, size_t size) #if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) if (nvm_init() < 0) return -1; - return spi_flash_protect(to_flash_offset(start), size); + return spi_flash_protect(nvm_mmio_to_flash_offset(start), size); #else return -1; #endif diff --git a/src/soc/intel/common/nvm.h b/src/soc/intel/common/nvm.h index feae5c3..074a2ce 100644 --- a/src/soc/intel/common/nvm.h +++ b/src/soc/intel/common/nvm.h @@ -33,4 +33,7 @@ int nvm_is_write_protected(void); /* Apply protection to a range of flash */ int nvm_protect(void *start, size_t size); +/* Map MMIO address to actual address in flash */ +uint32_t nvm_mmio_to_flash_offset(void *p); + #endif /* _COMMON_NVM_H_ */

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Patch set updated for coreboot: soc/intel/apollolake: Override default to_flash_offset implementation
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14248 -gerrit commit 680565150c7cfd853fb83a4f56e29ffd5c05a7d4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 3 13:16:36 2016 -0800 soc/intel/apollolake: Override default to_flash_offset implementation The default nvm_mmio_to_flash_offset() implementation used by NVM code in intel/common does not work on apollolake. As a result, provide the correct override. Change-Id: I01a94f90dfdd33586a4aac5c05dd8c73e8804437 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/mmap_boot.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 3625924..a618d4a 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -16,6 +16,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/intel/common/nvm.h> /* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */ #define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 128 * KiB) @@ -72,3 +73,10 @@ const struct cbfs_locator cbfs_master_header_locator = { .name = "IAFW Locator", .locate = iafw_boot_region_properties, }; + +uint32_t nvm_mmio_to_flash_offset(void *p) +{ + uintptr_t xlate_base; + xlate_base = VIRTUAL_ROM_BASE; + return (uintptr_t)p - xlate_base + CONFIG_IFD_BIOS_START; +}

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Patch set updated for coreboot: soc/intel/apollolake: Enabling using of MRC data when available
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14253 -gerrit commit 7a4963594a6ff5969716c3c7218041fc471f1936 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Apr 4 16:38:46 2016 -0700 soc/intel/apollolake: Enabling using of MRC data when available Change-Id: Iee30a6efb8dcdd04affd5d1105a254781287e9e4 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index d24cdf8..4e800f7 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -23,6 +23,7 @@ #include <device/resource.h> #include <string.h> #include <soc/iomap.h> +#include <soc/intel/common/mrc_cache.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/romstage.h> @@ -78,10 +79,10 @@ static void disable_watchdog(void) asmlinkage void car_stage_entry(void) { - void *hob_list_ptr; - struct range_entry fsp_mem; - struct range_entry reg_car; + void *hob_list_ptr, *mrc_data; + struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; + size_t mrc_data_size; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -111,6 +112,15 @@ asmlinkage void car_stage_entry(void) /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); + /* Save MRC Data to CBMEM */ + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + { + /* TODO: treat MRC data as const */ + mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); + if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) + printk(BIOS_ERR, "Failed to stash MRC data\n"); + } + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -134,6 +144,9 @@ static void fill_console_params(struct FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { + const struct mrc_saved_data *mrc_cache; + struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -154,6 +167,18 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) */ mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; + + arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { + if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { + /* MRC cache found */ + arch_upd->NvsBufferPtr = (void *)mrc_cache->data; + arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + } else + printk(BIOS_DEBUG, "MRC cache was not found\n"); + } } __attribute__ ((weak))

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coreboot-gerrit April 2016