coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

1 participants
1270 discussions

Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Include SOC ASL
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13372 -gerrit commit e2bd766741bcd0d685738c03a778afb94d8a2778 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 17:06:54 2015 -0800 mainboard/intel/apollolake_rvp: Include SOC ASL Include northbridge ASL file into board DSDT table. Change-Id: I33903a9c281e4981bd0f226c22553e22f98075bc Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/dsdt.asl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 7b9fe29..16d09a4 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -22,7 +22,8 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> } }

1 0

New patch to review for coreboot: intel/apollolake_rvp: Add sleepstates.asl to dsdt
by Hannah Williams 07 Apr '16

07 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14285 -gerrit commit 297847fc32e9bb313981bcf02d4cf220bed3fdd1 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Feb 5 23:51:54 2016 -0800 intel/apollolake_rvp: Add sleepstates.asl to dsdt Change-Id: Ia72aaf6642dcdc9106c1992af3cf6cb21a8fff4a Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/apollolake_rvp/dsdt.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 7b9fe29..9c3d8ab 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -25,5 +25,7 @@ DefinitionBlock( Name (_HID, EISAID ("PNP0A08")) /* PCIe */ } } + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> }

1 0

Patch merged into coreboot/master: drivers/intel/fsp2_0: Add utility to recover MRC NV Storage data
by gerrit＠coreboot.org 07 Apr '16

07 Apr '16

the following patch was just integrated into master: commit 3503b3f73052e8a0bc069995d16c30aab3782d9a Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Mar 4 12:14:52 2016 -0800 drivers/intel/fsp2_0: Add utility to recover MRC NV Storage data Change-Id: I08d3ba8b64459b1f84a5f1318e37c31010d7ae0f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/14251 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14251 for details. -gerrit

1 0

New patch to review for coreboot: soc/apollolake: Add ACPI platform sleep capability
by Hannah Williams 07 Apr '16

07 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14282 -gerrit commit 9d7e6d8616c51f637dc30e4d4825332aff6b06e5 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Feb 5 23:43:03 2016 -0800 soc/apollolake: Add ACPI platform sleep capability Change-Id: I6854f410b4d3847238f0253b7fbb9bbe8f9da395 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/acpi/sleepstates.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/sleepstates.asl b/src/soc/intel/apollolake/acpi/sleepstates.asl new file mode 100644 index 0000000..3037232 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/sleepstates.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) +Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) +Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 })

1 0

Patch merged into coreboot/master: drivers/intel/fsp2_0: Add boot mode constants
by gerrit＠coreboot.org 07 Apr '16

07 Apr '16

the following patch was just integrated into master: commit a6dd53535410f552809501d613de127a7b4b8d90 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Mar 17 16:42:41 2016 -0700 drivers/intel/fsp2_0: Add boot mode constants This adds boot mode constants. They match EDK2 found in PiBootMode.h constants but are part of FSP2.0 spec. Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14249 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14249 for details. -gerrit

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI HPET table
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13374 -gerrit commit df9ca3e94a0eb0c600eb307107fa288597b2978e Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Dec 1 09:14:20 2015 -0800 soc/apollolake/acpi: Fill ACPI HPET table HPET table is required to report integrated HPET timer to kernel. Without HPET table added,Linux kernel will panic when loading timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 7 +++++ src/soc/intel/apollolake/include/soc/acpi.h | 3 ++ src/soc/intel/apollolake/lpc.c | 49 +++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 5fd2b74..bf630a9 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -86,3 +86,10 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt) fadt->x_gpe1_blk.space_id = 1; } + +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index f21b379..6546662 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -17,4 +17,7 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c new file mode 100644 index 0000000..c4aca69 --- /dev/null +++ b/src/soc/intel/apollolake/lpc.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> + +static void soc_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + + /* Add the default claimed legacy IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_lpc_read_resources(device_t dev) +{ + /* Get the PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add IO resources to LPC. */ + soc_lpc_add_io_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &soc_lpc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, +}; + +static const struct pci_driver soc_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = PCI_DEV_ID_APOLLOLAKE_LPC, +};

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add utility to recover MRC NV Storage data
by Aaron Durbin 07 Apr '16

07 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14251 -gerrit commit d5cb13a3552839792250e2b8bbcc14e00bf656f4 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Mar 4 12:14:52 2016 -0800 drivers/intel/fsp2_0: Add utility to recover MRC NV Storage data Change-Id: I08d3ba8b64459b1f84a5f1318e37c31010d7ae0f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 12 ++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + 2 files changed, 13 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index c1f8f10..00c5d26 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -86,6 +86,11 @@ static const uint8_t uuid_owner_tseg[16] = { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 }; +static const uint8_t uuid_fsp_nv_storage[16] = { + 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c, + 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 +}; + static const uint8_t empty_uuid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; @@ -97,6 +102,7 @@ static const struct uuid_name_map { { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, { uuid_owner_tseg, "TSEG" }, + { uuid_fsp_nv_storage, "FSP_NV_STORAGE" }, }; static const char *resource_name(enum resource_type type) @@ -291,3 +297,9 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) return NULL; } + + +const void *fsp_find_nv_storage_data(size_t *size) +{ + return fsp_find_extension_hob_by_uuid(uuid_fsp_nv_storage, size); +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 0bdcd79..d9d9539 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -24,6 +24,7 @@ void fsp_save_hob_list(void *hob_list_ptr); const void *fsp_get_hob_list(void); const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); +const void *fsp_find_nv_storage_data(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); /* * Hand-off-block utilities which do not depend on CBMEM, but need to be passed

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add boot mode constants
by Aaron Durbin 07 Apr '16

07 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14249 -gerrit commit a7272595fd09128fc1e0f24cca4c8a95174ce02c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Mar 17 16:42:41 2016 -0700 drivers/intel/fsp2_0: Add boot mode constants This adds boot mode constants. They match EDK2 found in PiBootMode.h constants but are part of FSP2.0 spec. Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index c098a5b..d49fc42 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -35,6 +35,16 @@ enum fsp_status { FSP_CRC_ERROR = 0x8000001b, }; +enum fsp_boot_mode { + FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00, + FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01, + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02, + FSP_BOOT_ON_S4_RESUME = 0x05, + FSP_BOOT_ON_S3_RESUME = 0x11, + FSP_BOOT_ON_FLASH_UPDATE = 0x12, + FSP_BOOT_IN_RECOVERY_MODE = 0x20 +}; + enum fsp_notify_phase { AFTER_PCI_ENUM = 0x20, READY_TO_BOOT = 0x40

1 0

New patch to review for coreboot: util/crossgcc/buildgcc: correct clang test
by Aaron Durbin 07 Apr '16

07 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14281 -gerrit commit abf4ca3eb9dd2c31cdf1bbbbf466523be4a3c15e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 7 16:58:10 2016 -0500 util/crossgcc/buildgcc: correct clang test On certain versions of /bin/sh the following sequence causes problems. '$CC --version | grep clang &>/dev/null && ...' I'm not sure how bash handles that case, but it's effectively forking grep off into the background and always evaluating an empty statement to /dev/null while unconditionally running whatever follows &&. Change-Id: Ie3a2ebb12226434d50a7b2a7e254c8b80ae4c46b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e2a30d8..049c3e1 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -455,7 +455,7 @@ build_BINUTILS() { build_GCC() { # Work around crazy code generator in GCC that confuses CLANG. - $CC --version | grep clang &>/dev/null && + $CC --version | grep clang >/dev/null && HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" # GCC does not honor HOSTCFLAGS at all. CFLAGS are used for

1 0

New patch to review for coreboot: util/crossgcc/buildgcc: quote parameters that may have spaces
by Aaron Durbin 07 Apr '16

07 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14280 -gerrit commit e36e6671c9344d7597833acf4c3dadf47dfa43fe Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 7 16:56:25 2016 -0500 util/crossgcc/buildgcc: quote parameters that may have spaces On certain versions of /bin/sh assigning variables with spaces unquoted leads to failures. Therefore, quote variables that are known to be passed in that have spaces. Change-Id: I007c56c3bfb8183bb4b16cf0591f6aa508fd105d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4641ae9..e2a30d8 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -191,7 +191,7 @@ searchtool() # Run a compile check of the specified library option to see if it's installed check_for_library() { local LIBRARY_FLAGS=$1 - local LIBRARY_PACKAGES=$2 + local LIBRARY_PACKAGES="$2" local LIBTEST_FILE=.libtest echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" > "${LIBTEST_FILE}.c"

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2016