coreboot-gerrit April 2016

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New patch to review for coreboot: soc/intel/common: Add SMM support
by Hannah Williams 07 Apr '16

07 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14290 -gerrit commit b4abe85697ae56b9408b9fe3d9b3538a46b28760 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Mon Apr 4 17:04:11 2016 -0700 soc/intel/common: Add SMM support Add SoC agnostic SMM feature support components. Change-Id: I3188481e175936ff1f9f0a35ed5b123bb0fe8397 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/soc/intel/common/Makefile.inc | 6 + src/soc/intel/common/smi.c | 90 ++++++++ src/soc/intel/common/smihandler.c | 412 +++++++++++++++++++++++++++++++++++ src/soc/intel/common/smmrelocate.c | 431 +++++++++++++++++++++++++++++++++++++ 4 files changed, 939 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index a7218b7..c9bbfd5 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +subdirs-y += ../../../cpu/x86/smm + verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c @@ -14,6 +16,10 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +ramstage-y += smi.c +ramstage-y += smmrelocate.c + +smm-y += smihandler.c # Create and add the MRC cache to the cbfs image ifneq ($(CONFIG_CHROMEOS),y) diff --git a/src/soc/intel/common/smi.c b/src/soc/intel/common/smi.c new file mode 100644 index 0000000..3eaf408 --- /dev/null +++ b/src/soc/intel/common/smi.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/io.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <string.h> +#include <soc/pm.h> +#include <soc/smm.h> + +void southbridge_smm_clear_state(void) +{ + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); + + if (get_smi_en() & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + printk(BIOS_DEBUG, "Done\n"); + + /* Dump and clear status registers */ + clear_smi_status(); + clear_pm1_status(); + clear_tco_status(); + clear_gpe_status(); +} + +void southbridge_smm_enable_smi(void) +{ + printk(BIOS_DEBUG, "Enabling SMIs.\n"); + /* Configure events */ + enable_pm1(PWRBTN_EN | GBL_EN); + disable_gpe(PME_B0_EN); + + /* Enable SMI generation */ + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); +} + +void southbridge_trigger_smi(void) +{ + /* raise an SMI interrupt */ + printk(BIOS_SPEW, " ... raise SMI#\n"); + outb(0x00, APM_CNT); +} + +void southbridge_clear_smi_status(void) +{ + /* Clear SMI status */ + clear_smi_status(); + + /* Clear PM1 status */ + clear_pm1_status(); + + /* Set EOS bit so other SMIs can occur. */ + enable_smi(EOS); +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + /* + * Issue SMI to set the gnvs pointer in SMM. + * tcg and smi1 are unused. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT + */ + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" ((u32)gnvs), + "d" (APM_CNT) + ); +} diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c new file mode 100644 index 0000000..6da76c7 --- /dev/null +++ b/src/soc/intel/common/smihandler.c @@ -0,0 +1,412 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <device/pci_def.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> + +/* GNVS needs to be set by coreboot initiating a software SMI. */ +static struct global_nvs_t *gnvs; +static int smm_initialized; + + +void southbridge_smi_set_eos(void) +{ + enable_smi(EOS); +} + +struct global_nvs_t *smm_get_gnvs(void) +{ + return gnvs; +} + +static void busmaster_disable_on_bus(int bus) +{ + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } +} + + +static void southbridge_smi_sleep(void) +{ + uint32_t reg32; + uint8_t slp_typ; + + /* First, disable further SMIs */ + disable_smi(SLP_SMI_EN); + + /* Figure out SLP_TYP */ + reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); + slp_typ = (reg32 >> 10) & 7; + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ-2); + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log S3, S4, and S5 entry */ + if (slp_typ >= 5) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); +#endif + /* Clear pending GPE events */ + clear_gpe_status(); + + /* Next, do the deed. */ + + switch (slp_typ) { + case SLP_TYP_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case SLP_TYP_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + + /* Invalidate the cache before going to S3 */ + wbinvd(); + break; + case SLP_TYP_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case SLP_TYP_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + + /* Disable all GPE */ + disable_all_gpe(); + + /* also iterates over all bridges on bus 0 */ + busmaster_disable_on_bus(0); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + /* Clear pending wake status bit to avoid immediate wake */ + + /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ + + /* + * Write back to the SLP register to cause the originally intended + * event again. We need to set BIT13 (SLP_EN) though to make the + * sleep happen. + */ + enable_pm1_control(SLP_EN); + + /* Make sure to stop executing code here for S3/S4/S5 */ + if (slp_typ > 1) + hlt(); + + /* + * In most sleep states, the code flow of this function ends at + * the line above. However, if we entered sleep state S1 and wake + * up again, we will continue to execute code in this function. + */ + reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); + if (reg32 & SCI_EN) { + /* The OS is not an ACPI OS, so we set the state to S0 */ + disable_pm1_control(SLP_EN | SLP_TYP); + } +} +/* + * Look for Synchronous IO SMI and use save state from that + * core in case we are not running on the same core that + * initiated the IO transaction. + */ +static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +{ + em64t100_smm_state_save_area_t *state; + int node; + + /* Check all nodes looking for the one that issued the IO */ + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0==1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4==0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return state; + } + + return NULL; +} + +#if IS_ENABLED(CONFIG_ELOG_GSMI) +static void southbridge_smi_gsmi(void) +{ + u32 *ret, *param; + uint8_t sub_command; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); + + if (!io_smi) + return; + + /* Command and return value in EAX */ + ret = (u32 *)&io_smi->rax; + sub_command = (uint8_t)(*ret >> 8); + + /* Parameter buffer in EBX */ + param = (u32 *)&io_smi->rbx; + + /* drivers/elog/gsmi.c */ + *ret = gsmi_exec(sub_command, param); +} +#endif + +static void finalize(void) +{ + static int finalize_done; + + if (finalize_done) { + printk(BIOS_DEBUG, "SMM already finalized.\n"); + return; + } + finalize_done = 1; + +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) + /* Re-init SPI driver to handle locked BAR */ +// spi_init(); TODO +#endif +} + +static void southbridge_smi_apmc(void) +{ + uint8_t reg8; + em64t100_smm_state_save_area_t *state; + + /* Emulate B2 register as the FADT / Linux expects it */ + + reg8 = inb(APM_CNT); + switch (reg8) { + case APM_CNT_CST_CONTROL: + /* + * Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "C-state control\n"); + break; + case APM_CNT_PST_CONTROL: + /* + * Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "P-state control\n"); + break; + case APM_CNT_ACPI_DISABLE: + disable_pm1_control(SCI_EN); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); + break; + case APM_CNT_ACPI_ENABLE: + enable_pm1_control(SCI_EN); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); + break; + case APM_CNT_GNVS_UPDATE: + if (smm_initialized) { + printk(BIOS_DEBUG, + "SMI#: SMM structures already initialized!\n"); + return; + } + state = smi_apmc_find_state_save(reg8); + if (state) { + /* EBX in the state save contains the GNVS pointer */ + gnvs = (struct global_nvs_t *)((uint32_t)state->rbx); + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } + break; +#if IS_ENABLED(CONFIG_ELOG_GSMI) + case ELOG_GSMI_APM_CNT: + southbridge_smi_gsmi(); + break; +#endif + case APM_CNT_FINALIZE: + finalize(); + break; + } + + mainboard_smi_apmc(reg8); +} + +static void southbridge_smi_pm1(void) +{ + uint16_t pm1_sts = clear_pm1_status(); + + /* + * While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + /* power button pressed */ +#if IS_ENABLED(CONFIG_ELOG_GSMI) + elog_add_event(ELOG_TYPE_POWER_BUTTON); +#endif + disable_pm1_control(-1UL); + enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + } +} + +static void southbridge_smi_gpe0(void) +{ + clear_gpe_status(); +} + +static void southbridge_smi_tco(void) +{ + uint32_t tco_sts = clear_tco_status(); + + /* Any TCO event? */ + if (!tco_sts) + return; + + if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ + /* Handle TCO timeout */ + printk(BIOS_DEBUG, "TCO Timeout.\n"); + } +} + +static void southbridge_smi_periodic(void) +{ + uint32_t reg32; + + reg32 = inl(ACPI_PMIO_BASE + SMI_EN); + + /* Are periodic SMIs enabled? */ + if ((reg32 & PERIODIC_EN) == 0) + return; + printk(BIOS_DEBUG, "Periodic SMI.\n"); +} + +typedef void (*smi_handler_t)(void); + +static const smi_handler_t southbridge_smi[32] = { + NULL, /* [0] reserved */ + NULL, /* [1] reserved */ + NULL, /* [2] BIOS_STS */ + NULL, /* [3] LEGACY_USB_STS */ + southbridge_smi_sleep, /* [4] SLP_SMI_STS */ + southbridge_smi_apmc, /* [5] APM_STS */ + NULL, /* [6] SWSMI_TMR_STS */ + NULL, /* [7] reserved */ + southbridge_smi_pm1, /* [8] PM1_STS */ + southbridge_smi_gpe0, /* [9] GPE0_STS */ + NULL, /* [10] reserved */ + NULL, /* [11] reserved */ + NULL, /* [12] reserved */ + southbridge_smi_tco, /* [13] TCO_STS */ + southbridge_smi_periodic, /* [14] PERIODIC_STS */ + NULL, /* [15] SERIRQ_SMI_STS */ + NULL, /* [16] SMBUS_SMI_STS */ + NULL, /* [17] LEGACY_USB2_STS */ + NULL, /* [18] INTEL_USB2_STS */ + NULL, /* [19] reserved */ + NULL, /* [20] PCI_EXP_SMI_STS */ + NULL, /* [21] reserved */ + NULL, /* [22] reserved */ + NULL, /* [23] reserved */ + NULL, /* [24] reserved */ + NULL, /* [25] reserved */ + NULL, /* [26] SPI_STS */ + NULL, /* [27] reserved */ + NULL, /* [28] PUNIT */ + NULL, /* [29] GUNIT */ + NULL, /* [30] reserved */ + NULL /* [31] reserved */ +}; + +void southbridge_smi_handler(void) +{ + int i; + uint32_t smi_sts; + + /* + * We need to clear the SMI status registers, or we won't see what's + * happening in the following calls. + */ + smi_sts = clear_smi_status(); + + /* Call SMI sub handler for each of the status bits */ + for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { + if (!(smi_sts & (1 << i))) + continue; + + if (southbridge_smi[i] != NULL) { + southbridge_smi[i](); + } else { + printk(BIOS_DEBUG, + "SMI_STS[%d] occurred, but no " + "handler available.\n", i); + } + } + + /* + * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, + * these events need to be cleared and checked unconditionally. + */ + mainboard_smi_gpi(clear_alt_status()); //TODO +} diff --git a/src/soc/intel/common/smmrelocate.c b/src/soc/intel/common/smmrelocate.c new file mode 100644 index 0000000..f7ffab6 --- /dev/null +++ b/src/soc/intel/common/smmrelocate.c @@ -0,0 +1,431 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <soc/cpu.h> +#include <soc/smm.h> + +/* This gets filled in and used during relocation. */ +static struct smm_relocation_params smm_reloc_params; + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_emrr_base.lo, + relo_params->uncore_emrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); +} + +static void update_save_state(int cpu, + struct smm_relocation_params *relo_params, + const struct smm_runtime *runtime) +{ + u32 smbase; + u32 iedbase; + + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = relo_params->smram_base - cpu * runtime->save_state_size; + iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", + smbase, iedbase); + + /* + * All threads need to set IEDBASE and SMBASE to the relocated + * handler region. However, the save state location depends on the + * smm_save_state_in_msrs field in the relocation parameters. If + * smm_save_state_in_msrs is non-zero then the CPUs are relocating + * the SMM handler in parallel, and each CPUs save state area is + * located in their respective MSR space. If smm_save_state_in_msrs + * is zero then the SMM relocation is happening serially so the + * save state is at the same default location for all CPUs. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smbase_msr; + msr_t iedbase_msr; + + smbase_msr.lo = smbase; + smbase_msr.hi = 0; + + /* + * According the BWG the IEDBASE MSR is in bits 63:32. It's + * not clear why it differs from the SMBASE MSR. + */ + iedbase_msr.lo = 0; + iedbase_msr.hi = iedbase; + + wrmsr(MSR_SMBASE, smbase_msr); + wrmsr(MSR_IEDBASE, iedbase_msr); + } else { + em64t101_smm_state_save_area_t *save_state; + + save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - + runtime->save_state_size); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; + } +} + +/* Returns 1 if SMM MSR save state was set. */ +static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) +{ + msr_t smm_mca_cap; + + smm_mca_cap = rdmsr(MSR_SMM_MCA_CAP); + if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(MSR_SMM_FEATURE_CONTROL); + smm_feature_control.hi = 0; + smm_feature_control.lo |= SMM_CPU_SAVE_EN; + wrmsr(MSR_SMM_FEATURE_CONTROL, smm_feature_control); + relo_params->smm_save_state_in_msrs = 1; + } + return relo_params->smm_save_state_in_msrs; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +static void asmlinkage cpu_smm_do_relocation(void *arg) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + relo_params = p->arg; + cpu = p->cpu; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + + /* + * Determine if the processor supports saving state in MSRs. If so, + * enable it before the non-BSPs run so that SMM relocation can occur + * in parallel in the non-BSP CPUs. + */ + if (cpu == 0) { + /* + * If smm_save_state_in_msrs is 1 then that means this is the + * 2nd time through the relocation handler for the BSP. + * Parallel SMM handler relocation is taking place. However, + * it is desired to access other CPUs save state in the real + * SMM handler. Therefore, disable the SMM save state in MSRs + * feature. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(MSR_SMM_FEATURE_CONTROL); + smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; + wrmsr(MSR_SMM_FEATURE_CONTROL, smm_feature_control); + } else if (bsp_setup_msr_save_state(relo_params)) + /* + * Just return from relocation handler if MSR save + * state is enabled. In that case the BSP will come + * back into the relocation handler to setup the new + * SMBASE as well disabling SMM save state in MSRs. + */ + return; + } + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, relo_params, runtime); + + /* Write EMRR and SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + void *handler_base; + size_t handler_size; + void *ied_base; + size_t ied_size; + void *tseg_base; + size_t tseg_size; + u32 emrr_base; + u32 emrr_size; + int phys_bits; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + /* + * Some of the range registers are dependent on the number of physical + * address bits supported. + */ + phys_bits = cpuid_eax(0x80000008) & 0xff; + + smm_region(&tseg_base, &tseg_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); + + params->smram_size = handler_size; + params->smram_base = (uintptr_t)handler_base; + + params->ied_base = (uintptr_t)ied_base; + params->ied_size = ied_size; + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; + + /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ + emrr_base = (params->ied_base + (2 << 20)) & rmask; + emrr_size = params->ied_size - (2 << 20); + + /* + * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + * on the number of physical address bits supported. + */ + params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; + params->emrr_base.hi = 0; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + + /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_emrr_base.lo = emrr_base; + params->uncore_emrr_base.hi = 0; + params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + MTRR_PHYS_MASK_VALID; + params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; +} + +static void adjust_apic_id_map(struct smm_loader_params *smm_params) +{ + struct smm_runtime *runtime; + int i; + + /* Adjust the APIC id map if HT is disabled. */ + if (!ht_disabled) + return; + + runtime = smm_params->runtime; + + /* The APIC ids increment by 2 when HT is disabled. */ + for (i = 0; i < CONFIG_MAX_CPUS; i++) + runtime->apic_id_to_cpu[i] = runtime->apic_id_to_cpu[i] * 2; +} + +static int install_relocation_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* + * The default SMM entry can happen in parallel or serially. If the + * default SMM entry is done in parallel the BSP has already setup + * the saving state to each CPU's MSRs. At least one save state size + * is required for the initial SMM entry for the BSP to determine if + * parallel SMM relocation is even feasible. Set the stack size to + * the save state size, and call into the do_relocation handler. + */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = (smm_handler_t)&cpu_smm_do_relocation, + .handler_arg = (void *)relo_params, + }; + + if (smm_setup_relocation_handler(&smm_params)) + return -1; + + adjust_apic_id_map(&smm_params); + + return 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + (1 << 20), 0, (32 << 10)); +} + +static int install_permanent_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* + * There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. + */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_params->smram_base); + if (smm_load_module((void *)relo_params->smram_base, + relo_params->smram_size, &smm_params)) + return -1; + + adjust_apic_id_map(&smm_params); + + return 0; +} + +static int cpu_smm_setup(void) +{ + int num_cpus; + msr_t msr; + + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + msr = rdmsr(MSR_CORE_THREAD_COUNT); + num_cpus = msr.lo & 0xffff; + if (num_cpus > CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + num_cpus, CONFIG_MAX_CPUS); + } + + if (install_relocation_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); + return -1; + } + + if (install_permanent_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + wbinvd(); + + return 0; +} + +int smm_initialize(void) +{ + /* Return early if CPU SMM setup failed. */ + if (cpu_smm_setup()) + return -1; + + /* Clear the SMM state in the southbridge. */ + southbridge_smm_clear_state(); + + /* Run the relocation handler. */ + smm_initiate_relocation(); + + if (smm_reloc_params.smm_save_state_in_msrs) + printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); + + return 0; +} + +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do * the final move. For APs, a relocation handler always + * needs to be run. + */ + if (smm_reloc_params.smm_save_state_in_msrs) + smm_initiate_relocation_parallel(); + else if (!boot_cpu()) + smm_initiate_relocation(); +} + +void smm_init(void) +{ + /* + * smm_init() is normally called from initialize_cpus() in + * lapic_cpu_init.c. However, that path is no longer used. Don't reuse + * the function name because that would cause confusion. + * The smm_initialize() function above is used to setup SMM at the + * appropriate time. + */ +} + +void smm_lock(void) +{ + /* + * LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); +#if ENV_RAMSTAGE + write32((void *)(CONFIG_MMCONF_BASE_ADDRESS + SMRAM), + D_LCK | G_SMRAME | C_BASE_SEG); +#else + pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, D_LCK | G_SMRAME + | C_BASE_SEG); +#endif +}

1 0

Patch set updated for coreboot: soc/intel/apollolake: Fix northbridge _CRS
by Andrey Petrov 07 Apr '16

07 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14288 -gerrit commit bb0f57a4bb24c610562bd4e620dd60c0725243fc Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Thu Apr 7 15:50:03 2016 -0700 soc/intel/apollolake: Fix northbridge _CRS Build break on current _CRS defination: within CRS, point to correct parent as MCHC but not MCHC._CRS Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1349c6a..9f4be7c 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -88,9 +88,9 @@ Method (_CRS, 0, Serialized) CreateDwordField (MCRS, ^PM01._LEN, PLEN) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^MCHC.TLUD, 0xFFF00000, PMIN) + And(^^MCHC.TLUD, 0xFFF00000, PMIN) /* Read MMCONF base */ - And(^MCHC.MCNF, 0xF0000000, PMAX) + And(^^MCHC.MCNF, 0xF0000000, PMAX) /* Calculate PCI MMIO Length */ Add(Subtract(PMAX, PMIN), 1, PLEN) @@ -101,10 +101,10 @@ Method (_CRS, 0, Serialized) CreateDwordField(MCRS, ^STOM._LEN, GLEN) /* Read BGSM */ - And(^MCHC.BGSM, 0xFFF00000, GMIN) + And(^^MCHC.BGSM, 0xFFF00000, GMIN) /* Read TOLUD */ - And(^MCHC.TLUD, 0xFFF00000, GMAX) + And(^^MCHC.TLUD, 0xFFF00000, GMAX) Decrement(GMAX) Add(Subtract(GMAX, GMIN), 1, GLEN) @@ -113,7 +113,7 @@ Method (_CRS, 0, Serialized) CreateQwordField (MCRS, ^PM02._MAX, MMAX) CreateQwordField (MCRS, ^PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (^^MCHC.TUUD, Local0) If (LLessEqual (Local0, 0x1000000000)) { Store (0, MMIN) @@ -123,4 +123,4 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -} \ No newline at end of file +}

1 0

New patch to review for coreboot: soc/apollolake: Add Helper functions to access Power Management Registers
by Hannah Williams 07 Apr '16

07 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14289 -gerrit commit e31d338ddb953c4092804d7c9753019084ea6e32 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Feb 4 20:13:34 2016 -0800 soc/apollolake: Add Helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 66 ++++-- src/soc/intel/apollolake/include/soc/pm.h | 93 +++++++- src/soc/intel/apollolake/pmutil.c | 358 ++++++++++++++++++++++++++++++ 3 files changed, 492 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 70ab515..fce4da3 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -2,48 +2,74 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/bootblock_car.c bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c -bootblock-y += car.c +bootblock-y += bootblock/early_chipset_config.S bootblock-y += gpio.c bootblock-y += mmap_boot.c -bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +bootblock-y += uart_early.c -romstage-y += placeholders.c -romstage-y += car.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c - -smm-y += placeholders.c +romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c +romstage-y += pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += cpu.c +ramstage-y += car_teardown.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ramstage-y += graphics.c +ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c -ramstage-y += uart.c ramstage-y += northbridge.c +ramstage-y += spi.c +ramstage-y += tsc_freq.c +ramstage-y += uart.c +ramstage-y += pmutil.c -postcar-y += exit_car.S -postcar-y += memmap.c -postcar-y += mmap_boot.c -postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +smm-y += pmutil.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include +# This is a temporary workaround for properly linking romstage into CAR +# It works because: +# 1) .text is the first section of romstage, and all others follow after +# 2) We override default CBFS rule for romstage, so it doesn't get relocated +LDFLAGS_romstage += -Ttext=$(CONFIG_ROMSTAGE_CAR_ADDR) + +ifeq ($(CONFIG_USE_BLOBS),y) + +BLOB_DIR := 3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) +SPI_FILE := $(call strip_quotes,$(BLOB_DIR)/$(CONFIG_PREBUILT_SPI_IMAGE)) + +$(obj)/coreboot.pre: $(objcbfs)/romstage.elf $(CBFSTOOL) \ + $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf \ + $$(prebuilt-files) + @cp $(SPI_FILE) $@ + @echo injecting bootblock + @$(CBFSTOOL) $@ write -r IBBL -f $(objcbfs)/bootblock.bin -d + @printf " CBFS $(CONFIG_CBFS_PREFIX)/romstage\n" + mv $@ $@.tmp + $(prebuild-files) true + mv $@.tmp $@ + +endif + endif diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 286406b..1b68fc5 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -13,19 +13,102 @@ #ifndef _SOC_APOLLOLAKE_PM_H_ #define _SOC_APOLLOLAKE_PM_H_ -/* ACPI_BASE_ADDRESS / PMBASE */ +/* ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PWRBTN_STS (1 << 8) + #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) + #define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define SCI_EN (1 << 0) + #define PM1_TMR 0x08 #define SMI_EN 0x40 +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ + #define SMI_STS 0x44 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c +#define TCO_STS 0x64 +#define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 #define GPE0_REG_MAX 4 -#define GPE0_STS(x) (0x20 + (x * 4)) -#define GPE0_EN(x) (0x30 + (x * 4)) +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) +#define PME_B0_EN (1 << 13) + + + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x1000 +#define GEN_PMCON1 0x1020 +# define PWR_FLR (1 << 16) +# define SUS_PWR_FLR (1 << 14) +#define GEN_PMCON2 0x1024 +# define RPS (1 << 2) + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; + int prev_sleep_state; +} __attribute__((packed)); + +int fill_power_state(struct chipset_power_state *ps); +int chipset_prev_sleep_state(struct chipset_power_state *ps); + +/* Power Management Utility Functions. */ +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); -#endif /* _SOC_APOLLOLAKE_PM_H_ */ +#endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c new file mode 100644 index 0000000..f618b81 --- /dev/null +++ b/src/soc/intel/apollolake/pmutil.c @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your option) + * any later version. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <rules.h> +#include <device/pci_def.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> + + +static void print_num_status_bits(int num_bits, uint32_t status, + const char * const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static uint32_t print_smi_status(uint32_t smi_sts) +{ + static const char * const smi_sts_bits[] = { + [2] = "BIOS", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", + [10]= "GPIO_SMI", + [12] = "MCSMI", + [13] = "TCO", + [14] = "PERIODIC", + [15] = "SERIRQ", + [16] = "SMBUS_SMI", + [17] = "XHCI", + [18] = "HOST_SMBUS", + [19] = "SCS", + [20] = "PCI_EXP_SMI", + [26] = "SPI", + }; + + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_num_status_bits(27, smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; +} + +static uint32_t reset_smi_status(void) +{ + uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS); + outl(smi_sts, ACPI_PMIO_BASE + SMI_STS); + return smi_sts; +} + +uint32_t clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} + +void enable_smi(uint32_t mask) +{ + uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + smi_en |= mask; + outl(smi_en, ACPI_PMIO_BASE + SMI_EN); +} + +void disable_smi(uint32_t mask) +{ + uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + smi_en &= ~mask; + outl(smi_en, ACPI_PMIO_BASE + SMI_EN); +} + +void enable_pm1_control(uint32_t mask) +{ + uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + pm1_cnt |= mask; + outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); +} + +void disable_pm1_control(uint32_t mask) +{ + uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + pm1_cnt &= ~mask; + outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS); + return pm1_sts; +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char * const pm1_sts_bits[] = { + [0] = "TMROF", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [11] = "PRBTNOR", + [13] = "USB", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_num_status_bits(16, pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +uint16_t clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} + +void enable_pm1(uint16_t events) +{ + outw(events, ACPI_PMIO_BASE + PM1_EN); +} + +static uint32_t print_tco_status(uint32_t tco_sts) +{ + static const char * const tco_sts_bits[] = { + [3] = "TIMEOUT", + [17] = "SECOND_TO", + }; + + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_num_status_bits(18, tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; +} + +static uint32_t reset_tco_status(void) +{ + uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT); + + outl(tco_sts, ACPI_PMIO_BASE + TCO_STS); + return tco_sts & tco_en; +} + +uint32_t clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} + +void enable_gpe(uint32_t mask) +{ + uint32_t gpe0_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + gpe0_en |= mask; + outl(gpe0_en, ACPI_PMIO_BASE + GPE0_EN(0)); +} + +void disable_gpe(uint32_t mask) +{ + uint32_t gpe0_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + gpe0_en &= ~mask; + outl(gpe0_en, ACPI_PMIO_BASE + GPE0_EN(0)); +} + +void disable_all_gpe(void) +{ + disable_gpe(~0); +} + + +static uint32_t reset_gpe_status(void) +{ + uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); + outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0)); + return gpe_sts; +} + +static uint32_t print_gpe_sts(uint32_t gpe_sts) +{ + static const char * const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [3] = "PCIE_WAKE0", + [4] = "PUNIT", + [5] = "GUNIT", + [6] = "PCIE_WAKE1", + [7] = "PCIE_WAKE2", + [8] = "PCIE_WAKE3", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "CSE_PME", + [12] = "XDCI_PME", + [13] = "XHCI_PME", + [14] = "AVS_PME", + [15] = "GPIO_TIER1_SCI", + [16] = "SMB_WAK", + [17] = "SATA_PME", + }; + + if (!gpe_sts) + return gpe_sts; + + printk(BIOS_DEBUG, "GPE0a_STS: "); + print_num_status_bits(18, gpe_sts, gpe_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return gpe_sts; +} + +uint32_t clear_gpe_status(void) +{ + return print_gpe_sts(reset_gpe_status()); +} + +static uint32_t reset_alt_status(void) +{ + return 0; +} + +static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +{ + uint32_t alt_gpio_sts; + static const char * const alt_gpio_smi_sts_bits[] = { + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", + [10] = "CORE_GPIO_2", + [11] = "CORE_GPIO_3", + [12] = "CORE_GPIO_4", + [13] = "CORE_GPIO_5", + [14] = "CORE_GPIO_6", + [15] = "CORE_GPIO_7", + }; + + /* Status bits are in the upper 16 bits. */ + alt_gpio_sts = alt_gpio_smi >> 16; + if (!alt_gpio_sts) + return alt_gpio_smi; + + printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); + print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return alt_gpio_smi; +} + +uint32_t clear_alt_status(void) +{ + return print_alt_sts(reset_alt_status()); +} + +void clear_pmc_status(void) +{ + uint32_t prsts; + uint32_t gen_pmcon1; + + prsts = read32((void *)(PMC_BAR0 + PRSTS)); + gen_pmcon1 = read32((void *)(PMC_BAR0 + GEN_PMCON1)); + + /* Clear the status bits. The RPS field is cleared on a 0 write. */ + write32((void *)(PMC_BAR0 + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((void *)(PMC_BAR0 + PRSTS), prsts); +} + + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int chipset_prev_sleep_state(struct chipset_power_state *ps) +{ + /* Default to S0. */ + int prev_sleep_state = SLEEP_STATE_S0; + + if (ps->pm1_sts & WAK_STS) { + switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + case SLP_TYP_S3: + prev_sleep_state = SLEEP_STATE_S3; + break; + #endif + case SLP_TYP_S5: + prev_sleep_state = SLEEP_STATE_S5; + break; + } + + /* Clear SLP_TYP. */ + outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT); + } + + + return prev_sleep_state; +} + +/* returns prev_sleep_state */ +int fill_power_state(struct chipset_power_state *ps) +{ + ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN); + ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + ps->gpe0_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); + ps->gpe0_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + ps->prsts = read32((void *)(PMC_BAR0 + PRSTS)); + ps->gen_pmcon1 =read32((void *)(PMC_BAR0 + GEN_PMCON1)); + ps->gen_pmcon2 = read32((void *)(PMC_BAR0 + GEN_PMCON2)); + + ps->prev_sleep_state = chipset_prev_sleep_state(ps); + + printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", + ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", + ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", + inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); + return ps->prev_sleep_state; +}

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New patch to review for coreboot: soc/intel/apollolake: Fix northbridge _CRS
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14288 -gerrit commit 07110b1932fbfe0d5e6206465c829360c71b4cc6 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Thu Apr 7 15:50:03 2016 -0700 soc/intel/apollolake: Fix northbridge _CRS Build break on current _CRS defination: within CRS, point to correct parent as MCHC but not MCHC._CRS Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1349c6a..9f4be7c 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -88,9 +88,9 @@ Method (_CRS, 0, Serialized) CreateDwordField (MCRS, ^PM01._LEN, PLEN) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^MCHC.TLUD, 0xFFF00000, PMIN) + And(^^MCHC.TLUD, 0xFFF00000, PMIN) /* Read MMCONF base */ - And(^MCHC.MCNF, 0xF0000000, PMAX) + And(^^MCHC.MCNF, 0xF0000000, PMAX) /* Calculate PCI MMIO Length */ Add(Subtract(PMAX, PMIN), 1, PLEN) @@ -101,10 +101,10 @@ Method (_CRS, 0, Serialized) CreateDwordField(MCRS, ^STOM._LEN, GLEN) /* Read BGSM */ - And(^MCHC.BGSM, 0xFFF00000, GMIN) + And(^^MCHC.BGSM, 0xFFF00000, GMIN) /* Read TOLUD */ - And(^MCHC.TLUD, 0xFFF00000, GMAX) + And(^^MCHC.TLUD, 0xFFF00000, GMAX) Decrement(GMAX) Add(Subtract(GMAX, GMIN), 1, GLEN) @@ -113,7 +113,7 @@ Method (_CRS, 0, Serialized) CreateQwordField (MCRS, ^PM02._MAX, MMAX) CreateQwordField (MCRS, ^PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (^^MCHC.TUUD, Local0) If (LLessEqual (Local0, 0x1000000000)) { Store (0, MMIN) @@ -123,4 +123,4 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -} \ No newline at end of file +}

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Patch set updated for coreboot: soc/intel/apollolake: Add lpss dsdt entry
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14218 -gerrit commit 22be765d4b3ad571648575c4b30f406d7c6c503a Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Jan 20 13:02:38 2016 -0800 soc/intel/apollolake: Add lpss dsdt entry Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/lpss.asl | 111 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 14 ++++ 2 files changed, 125 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl new file mode 100644 index 0000000..d77eab0 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +scope (\_SB.PCI0) { + +/* LPIO1 PWM */ +Device(PWM) { + Name (_ADR, 0x001A0000) + Name (_DDN, "Intel(R) PWM Controller") +} + +/* LPIO1 HS-UART #1 */ +Device(URT1) { + Name (_ADR, 0x00180000) + Name (_DDN, "Intel(R) HS-UART Controller #1") +} + +/* LPIO1 HS-UART #2 */ +Device(URT2) { + Name (_ADR, 0x00180001) + Name (_DDN, "Intel(R) HS-UART Controller #2") +} + +/* LPIO1 HS-UART #3 */ +Device(URT3) { + Name (_ADR, 0x00180002) + Name (_DDN, "Intel(R) HS-UART Controller #3") +} + +/* LPIO1 HS-UART #4 */ +Device(URT4) { + Name (_ADR, 0x00180003) + Name (_DDN, "Intel(R) HS-UART Controller #4") +} + +/* LPIO1 SPI */ +Device(SPI1) { + Name (_ADR, 0x00190000) + Name (_DDN, "Intel(R) SPI Controller #1") +} + +/* LPIO1 SPI #2 */ +Device(SPI2) { + Name (_ADR, 0x00190001) + Name (_DDN, "Intel(R) SPI Controller #2") +} + +/* LPIO1 SPI #3 */ +Device(SPI3) { + Name (_ADR, 0x00190002) + Name (_DDN, "Intel(R) SPI Controller #3") +} + + +/* LPIO2 I2C #0 */ +Device(I2C0) { + Name (_ADR, 0x00160000) + Name (_DDN, "Intel(R) I2C Controller #0") +} + +/* LPIO2 I2C #1 */ +Device(I2C1) { + Name (_ADR, 0x00160001) + Name (_DDN, "Intel(R) I2C Controller #1") +} + +/* LPIO2 I2C #2 */ +Device(I2C2) { + Name (_ADR, 0x00160002) + Name (_DDN, "Intel(R) I2C Controller #2") +} + +/* LPIO2 I2C #3 */ +Device(I2C3) { + Name (_ADR, 0x00160003) + Name (_DDN, "Intel(R) I2C Controller #3") +} + +/* LPIO2 I2C #4 */ +Device(I2C4) { + Name (_ADR, 0x00170000) + Name (_DDN, "Intel(R) I2C Controller #4") +} + +/* LPIO2 I2C #5 */ +Device(I2C5) { + Name (_ADR, 0x00170001) + Name (_DDN, "Intel(R) I2C Controller #5") +} + +/* LPIO2 I2C #6 */ +Device(I2C6) { + Name (_ADR, 0x00170002) + Name (_DDN, "Intel(R) I2C Controller #6") +} + +/* LPIO2 I2C #7 */ +Device(I2C7) { + Name (_ADR, 0x00170003) + Name (_DDN, "Intel(R) I2C Controller #7") +} +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl new file mode 100644 index 0000000..4a7757b --- /dev/null +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/* LPSS device */ +#include "lpss.asl" \ No newline at end of file

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Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI MCFG table
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13375 -gerrit commit c17397b2144d9b0ee5e989566809a23e22d060b2 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:13:23 2015 -0800 soc/apollolake/acpi: Fill ACPI MCFG table ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 5fd2b74..3677477 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -18,6 +18,10 @@ unsigned long acpi_fill_mcfg(unsigned long current) { + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ + current += acpi_create_mcfg_mmconfig((void *) current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, + 255); return current; }

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI HPET table
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13374 -gerrit commit 01d12d270464f14f10c4a28d25f45363f3967398 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Dec 1 09:14:20 2015 -0800 soc/apollolake/acpi: Fill ACPI HPET table HPET table is required to report integrated HPET timer to kernel. Without HPET table added,Linux kernel will panic when loading timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 7 +++++++ src/soc/intel/apollolake/include/soc/acpi.h | 3 +++ src/soc/intel/apollolake/lpc.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d496d54..e8a184e 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -112,3 +112,10 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt) fadt->x_gpe1_blk.space_id = 1; } + +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index f21b379..6546662 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -17,4 +17,7 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index abc5245..d0cae3d 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -13,6 +13,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/acpi.h> #include <soc/pci_ids.h> static void soc_lpc_add_io_resources(device_t dev) @@ -39,6 +40,7 @@ static struct device_operations device_ops = { .read_resources = &soc_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, }; static const struct pci_driver soc_lpc __pci_driver = {

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Patch set updated for coreboot: soc/apollolake/acpi: Fill in ACPI MADT table
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13373 -gerrit commit 749b3011fb714cf21c1f4f01bf56227e620dd778 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:33:21 2015 -0800 soc/apollolake/acpi: Fill in ACPI MADT table ACPI MADT tables required to describe the multiprocess interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 3677477..d496d54 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,6 +11,8 @@ */ #include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -25,11 +27,31 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -unsigned long acpi_fill_madt(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { + uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, 9, 9, flags); + return current; } +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + static int acpi_sci_irq(void) { int sci_irq = 9;

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Patch set updated for coreboot: soc/apollolake: Add lpc device driver
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13356 -gerrit commit 1d403c7de2d661afd58e5264d22912dc3df2afea Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Thu Nov 12 18:19:41 2015 -0800 soc/apollolake: Add lpc device driver A dedicated pci device driver required for LPC devices as the legacy IO range need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver system will have assertion on load RTC DXE driver in UEFI payloads. Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/lpc.c | 48 +++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 70ab515..98db608 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += chip.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c new file mode 100644 index 0000000..abc5245 --- /dev/null +++ b/src/soc/intel/apollolake/lpc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_ids.h> + +static void soc_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + + /* Add the default claimed legacy IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_lpc_read_resources(device_t dev) +{ + /* Get the PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add IO resources to LPC. */ + soc_lpc_add_io_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &soc_lpc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, +}; + +static const struct pci_driver soc_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_LPC, +};

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Patch set updated for coreboot: soc/intel/apollolake: Fill _PRT entry in DSDT
by Lijian Zhao 07 Apr '16

07 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14243 -gerrit commit 3c8ae9331352cce25f613924642e42c7df652c8d Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 15:34:45 2015 -0800 soc/intel/apollolake: Fill _PRT entry in DSDT ACPI aware OS will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC gets fixed interrupt line. Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pci_irqs.asl | 59 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/soc_int.asl | 52 ++++++++++++++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..024282c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "soc_int.asl" + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, NPK_INT}, + Package(){0x0000FFFF, 1, 0, PUNIT_INT}, + Package(){0x0002FFFF, 0, 0, GEN_INT}, + Package(){0x0003FFFF, 0, 0, IUNIT_INT}, + Package(){0x000DFFFF, 1, 0, PMC_INT}, + Package(){0x000EFFFF, 0, 0, AUDIO_INT}, + Package(){0x000FFFFF, 0, 0, CSE_INT}, + Package(){0x0011FFFF, 0, 0, ISH_INT}, + Package(){0x0012FFFF, 0, 0, SATA_INT}, + Package(){0x0013FFFF, 0, 0, PIRQA_INT}, + Package(){0x0013FFFF, 1, 0, PIRQB_INT}, + Package(){0x0013FFFF, 2, 0, PIRQC_INT}, + Package(){0x0013FFFF, 3, 0, PIRQD_INT}, + Package(){0x0014FFFF, 0, 0, PIRQB_INT}, + Package(){0x0014FFFF, 1, 0, PIRQC_INT}, + Package(){0x0014FFFF, 2, 0, PIRQD_INT}, + Package(){0x0014FFFF, 3, 0, PIRQA_INT}, + Package(){0x0015FFFF, 0, 0, XHCI_INT}, + Package(){0x0015FFFF, 1, 0, XDCI_INT}, + Package(){0x0016FFFF, 0, 0, I2C0_INT}, + Package(){0x0016FFFF, 1, 0, I2C1_INT}, + Package(){0x0016FFFF, 2, 0, I2C2_INT}, + Package(){0x0016FFFF, 3, 0, I2C3_INT}, + Package(){0x0017FFFF, 0, 0, I2C4_INT}, + Package(){0x0017FFFF, 1, 0, I2C5_INT}, + Package(){0x0017FFFF, 2, 0, I2C6_INT}, + Package(){0x0017FFFF, 3, 0, I2C7_INT}, + Package(){0x0018FFFF, 0, 0, UART0_INT}, + Package(){0x0018FFFF, 1, 0, UART1_INT}, + Package(){0x0018FFFF, 2, 0, UART2_INT}, + Package(){0x0018FFFF, 3, 0, UART3_INT}, + Package(){0x0019FFFF, 0, 0, SPI0_INT}, + Package(){0x0019FFFF, 1, 0, SPI1_INT}, + Package(){0x0019FFFF, 2, 0, SPI2_INT}, + Package(){0x001BFFFF, 0, 0, SDCARD_INT}, + Package(){0x001CFFFF, 0, 0, EMMC_INT}, + Package(){0x001EFFFF, 0, 0, SDIO_INT}, + Package(){0x001FFFFF, 1, 0, SMBUS_INT}, + } + ) +} diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl new file mode 100644 index 0000000..22fcb49 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_INT_DEFINE_ASL_ +#define _SOC_INT_DEFINE_ASL_ + +#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/ +#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/ +#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/ +#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ +#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ +#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define NPK_INT 16 +#define PIRQA_INT 16 +#define PIRQB_INT 17 +#define PIRQC_INT 18 +#define SATA_INT 19 +#define GEN_INT 19 +#define PIRQD_INT 19 +#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/ +#define SMBUS_INT 20 /* PIRQE */ +#define CSE_INT 20 /* PIRQE */ +#define IUNIT_INT 21 /* PIRQF */ +#define PUNIT_INT 24 +#define AUDIO_INT 25 +#define ISH_INT 26 +#define I2C0_INT 27 +#define I2C1_INT 28 +#define I2C2_INT 29 +#define I2C3_INT 30 +#define I2C4_INT 31 +#define I2C5_INT 32 +#define I2C6_INT 33 +#define I2C7_INT 34 +#define SPI0_INT 35 +#define SPI1_INT 36 +#define SPI2_INT 37 +#define UFS_INT 38 +#define EMMC_INT 39 +#define SDIO_INT 42 + + +#endif /* _SOC_INT_DEFINE_ASL_ */ \ No newline at end of file

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coreboot-gerrit April 2016