coreboot-gerrit April 2016

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New patch to review for coreboot: move xdr interface from util/cbfstool to commonlib
by George Trudeau 08 Apr '16

08 Apr '16

George Trudeau (george.trudeau(a)usherbrooke.ca) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14294 -gerrit commit e2fa4d325893226da07031541455ce52204946f5 Author: George Trudeau <george.trudeau(a)usherbrooke.ca> Date: Mon Apr 4 00:19:02 2016 -0400 move xdr interface from util/cbfstool to commonlib First step to transform code sections endian-agnostic. The goal is to replace [nh]to[hn][sll] functions and remove any endianness checks. The xdr interface automatically orders bytes into native endianness, only needs to specify data representation. Change-Id: Icb3c6a7da2d253685a3bc157bc7f5a51183c9652 Signed-off-by: George Trudeau <george.trudeau(a)usherbrooke.ca> --- src/commonlib/Makefile.inc | 4 + src/commonlib/include/commonlib/xdr.h | 46 ++++++++++ src/commonlib/xdr.c | 165 ++++++++++++++++++++++++++++++++++ util/cbfstool/common.h | 24 +---- util/cbfstool/xdr.c | 152 ------------------------------- 5 files changed, 216 insertions(+), 175 deletions(-) diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 7c14f7c..7e0be9f 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -25,3 +25,7 @@ verstage-y += lz4_wrapper.c romstage-y += lz4_wrapper.c ramstage-y += lz4_wrapper.c postcar-y += lz4_wrapper.c + +bootblock-y += xdr.c +romstage-y += xdr.c +ramstage-y += xdr.c diff --git a/src/commonlib/include/commonlib/xdr.h b/src/commonlib/include/commonlib/xdr.h new file mode 100644 index 0000000..80d6671 --- /dev/null +++ b/src/commonlib/include/commonlib/xdr.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2009 coresystems GmbH + * written by Patrick Georgi <patrick.georgi(a)coresystems.de> + * Copyright (C) 2012 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XDR_H_ +#define _XDR_H_ + +#include <stddef.h> +#include <stdint.h> + +/* Buffer and file I/O */ +struct buffer { + char *name; + char *data; + size_t offset; + size_t size; +}; + +struct xdr { + uint8_t (*get8)(struct buffer *input); + uint16_t (*get16)(struct buffer *input); + uint32_t (*get32)(struct buffer *input); + uint64_t (*get64)(struct buffer *input); + void (*put8)(struct buffer *input, uint8_t val); + void (*put16)(struct buffer *input, uint16_t val); + void (*put32)(struct buffer *input, uint32_t val); + void (*put64)(struct buffer *input, uint64_t val); +}; + +extern struct xdr xdr_le, xdr_be; + +size_t bgets(struct buffer *input, void *output, size_t len); +size_t bputs(struct buffer *b, const void *data, size_t len); + +#endif diff --git a/src/commonlib/xdr.c b/src/commonlib/xdr.c new file mode 100644 index 0000000..03fa081 --- /dev/null +++ b/src/commonlib/xdr.c @@ -0,0 +1,165 @@ + /* + * cbfstool, CLI utility for CBFS file manipulation + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include <commonlib/xdr.h> + +size_t bgets(struct buffer *input, void *output, size_t len) +{ + len = input->size < len ? input->size : len; + memmove(output, input->data, len); + input->data += len; + input->size -= len; + + return len; +} + +size_t bputs(struct buffer *b, const void *data, size_t len) +{ + memmove(&b->data[b->size], data, len); + b->size += len; + + return len; +} + +/* The assumption in all this code is that we're given a pointer to enough data. + * Hence, we do not check for underflow. + */ +static uint8_t get8(struct buffer *input) +{ + uint8_t ret = *input->data++; + + input->size--; + + return ret; +} + +static uint16_t get16be(struct buffer *input) +{ + uint16_t ret; + + ret = get8(input) << 8; + ret |= get8(input); + + return ret; +} + +static uint32_t get32be(struct buffer *input) +{ + uint32_t ret; + + ret = get16be(input) << 16; + ret |= get16be(input); + + return ret; +} + +static uint64_t get64be(struct buffer *input) +{ + uint64_t ret; + + ret = get32be(input); + ret <<= 32; + ret |= get32be(input); + + return ret; +} + +static void put8(struct buffer *input, uint8_t val) +{ + input->data[input->size] = val; + input->size++; +} + +static void put16be(struct buffer *input, uint16_t val) +{ + put8(input, val >> 8); + put8(input, val); +} + +static void put32be(struct buffer *input, uint32_t val) +{ + put16be(input, val >> 16); + put16be(input, val); +} + +static void put64be(struct buffer *input, uint64_t val) +{ + put32be(input, val >> 32); + put32be(input, val); +} + +static uint16_t get16le(struct buffer *input) +{ + uint16_t ret; + + ret = get8(input); + ret |= get8(input) << 8; + + return ret; +} + +static uint32_t get32le(struct buffer *input) +{ + uint32_t ret; + + ret = get16le(input); + ret |= get16le(input) << 16; + + return ret; +} + +static uint64_t get64le(struct buffer *input) +{ + uint64_t ret; + uint32_t low; + + low = get32le(input); + ret = get32le(input); + ret <<= 32; + ret |= low; + + return ret; +} + +static void put16le(struct buffer *input, uint16_t val) +{ + put8(input, val); + put8(input, val >> 8); +} + +static void put32le(struct buffer *input, uint32_t val) +{ + put16le(input, val); + put16le(input, val >> 16); +} + +static void put64le(struct buffer *input, uint64_t val) +{ + put32le(input, val); + put32le(input, val >> 32); +} + +struct xdr xdr_be = { + get8, get16be, get32be, get64be, + put8, put16be, put32be, put64be +}; + +struct xdr xdr_le = { + get8, get16le, get32le, get64le, + put8, put16le, put32le, put64le +}; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index ea6f3cf..22e11fd 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -22,6 +22,7 @@ #include <string.h> #include <assert.h> +#include <commonlib/xdr.h> #include <console/console.h> /* Endianess */ @@ -44,14 +45,6 @@ static inline uint32_t align_up(uint32_t value, uint32_t align) return value; } -/* Buffer and file I/O */ -struct buffer { - char *name; - char *data; - size_t offset; - size_t size; -}; - static inline void *buffer_get(const struct buffer *b) { return b->data; @@ -204,21 +197,6 @@ int do_lzma_compress(char *in, int in_len, char *out, int *out_len); int do_lzma_uncompress(char *dst, int dst_len, char *src, int src_len, size_t *actual_size); -/* xdr.c */ -struct xdr { - uint8_t (*get8)(struct buffer *input); - uint16_t (*get16)(struct buffer *input); - uint32_t (*get32)(struct buffer *input); - uint64_t (*get64)(struct buffer *input); - void (*put8)(struct buffer *input, uint8_t val); - void (*put16)(struct buffer *input, uint16_t val); - void (*put32)(struct buffer *input, uint32_t val); - void (*put64)(struct buffer *input, uint64_t val); -}; - -extern struct xdr xdr_le, xdr_be; -size_t bgets(struct buffer *input, void *output, size_t len); -size_t bputs(struct buffer *b, const void *data, size_t len); /* Returns a 0-terminated string containing a hex representation of * len bytes starting at data. diff --git a/util/cbfstool/xdr.c b/util/cbfstool/xdr.c deleted file mode 100644 index 06cc91f..0000000 --- a/util/cbfstool/xdr.c +++ /dev/null @@ -1,152 +0,0 @@ - /* - * cbfstool, CLI utility for CBFS file manipulation - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <ctype.h> -#include <unistd.h> -#include <stdint.h> -#include "common.h" - -size_t bgets(struct buffer *input, void *output, size_t len) -{ - len = input->size < len ? input->size : len; - memmove(output, input->data, len); - input->data += len; - input->size -= len; - return len; -} - -size_t bputs(struct buffer *b, const void *data, size_t len) -{ - memmove(&b->data[b->size], data, len); - b->size += len; - return len; -} - -/* The assumption in all this code is that we're given a pointer to enough data. - * Hence, we do not check for underflow. - */ -static uint8_t get8(struct buffer *input) -{ - uint8_t ret = *input->data++; - input->size--; - return ret; -} - -static uint16_t get16be(struct buffer *input) -{ - uint16_t ret; - ret = get8(input) << 8; - ret |= get8(input); - return ret; -} - -static uint32_t get32be(struct buffer *input) -{ - uint32_t ret; - ret = get16be(input) << 16; - ret |= get16be(input); - return ret; -} - -static uint64_t get64be(struct buffer *input) -{ - uint64_t ret; - ret = get32be(input); - ret <<= 32; - ret |= get32be(input); - return ret; -} - -static void put8(struct buffer *input, uint8_t val) -{ - input->data[input->size] = val; - input->size++; -} - -static void put16be(struct buffer *input, uint16_t val) -{ - put8(input, val >> 8); - put8(input, val); -} - -static void put32be(struct buffer *input, uint32_t val) -{ - put16be(input, val >> 16); - put16be(input, val); -} - -static void put64be(struct buffer *input, uint64_t val) -{ - put32be(input, val >> 32); - put32be(input, val); -} - -static uint16_t get16le(struct buffer *input) -{ - uint16_t ret; - ret = get8(input); - ret |= get8(input) << 8; - return ret; -} - -static uint32_t get32le(struct buffer *input) -{ - uint32_t ret; - ret = get16le(input); - ret |= get16le(input) << 16; - return ret; -} - -static uint64_t get64le(struct buffer *input) -{ - uint64_t ret; - uint32_t low; - low = get32le(input); - ret = get32le(input); - ret <<= 32; - ret |= low; - return ret; -} - -static void put16le(struct buffer *input, uint16_t val) -{ - put8(input, val); - put8(input, val >> 8); -} - -static void put32le(struct buffer *input, uint32_t val) -{ - put16le(input, val); - put16le(input, val >> 16); -} - -static void put64le(struct buffer *input, uint64_t val) -{ - put32le(input, val); - put32le(input, val >> 32); -} - -struct xdr xdr_be = { - get8, get16be, get32be, get64be, - put8, put16be, put32be, put64be -}; - -struct xdr xdr_le = { - get8, get16le, get32le, get64le, - put8, put16le, put32le, put64le -};

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Patch set updated for coreboot: soc/apollolake: Add helper functions to access Power Management Registers
by Hannah Williams 08 Apr '16

08 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14289 -gerrit commit d7ddd2745b55cf12f783f1973199c0d62a8a25a2 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Feb 4 20:13:34 2016 -0800 soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/include/soc/pm.h | 95 +++++++- src/soc/intel/apollolake/pmutil.c | 362 ++++++++++++++++++++++++++++++ 3 files changed, 457 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 70ab515..8f2960d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,8 +25,10 @@ romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += pmutil.c smm-y += placeholders.c +smm-y += pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -38,6 +40,7 @@ ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += northbridge.c +ramstage-y += pmutil.c postcar-y += exit_car.S postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 286406b..37dcf76 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -13,19 +13,108 @@ #ifndef _SOC_APOLLOLAKE_PM_H_ #define _SOC_APOLLOLAKE_PM_H_ -/* ACPI_BASE_ADDRESS / PMBASE */ +/* ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PWRBTN_STS (1 << 8) + #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8 ) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) + #define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define SCI_EN (1 << 0) + #define PM1_TMR 0x08 + #define SMI_EN 0x40 +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* Global SMI Enable */ + #define SMI_STS 0x44 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c +#define TCO_STS 0x64 +#define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 #define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 #define GPE0_STS(x) (0x20 + (x * 4)) #define GPE0_EN(x) (0x30 + (x * 4)) +#define PME_B0_EN (1 << 13) + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x1000 +#define GEN_PMCON1 0x1020 +# define PWR_FLR (1 << 16) +# define SUS_PWR_FLR (1 << 14) +#define GEN_PMCON2 0x1024 +# define RPS (1 << 2) +#define GEN_PMCON3 0x1028 + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0a_sts; + uint32_t gpe0a_en; + uint32_t gpe0b_sts; + uint32_t gpe0b_en; + uint32_t gpe0c_sts; + uint32_t gpe0c_en; + uint32_t gpe0d_sts; + uint32_t gpe0d_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; + int prev_sleep_state; +} __attribute__((packed)); + +int fill_power_state(struct chipset_power_state *ps); +int chipset_prev_sleep_state(struct chipset_power_state *ps); + +/* Power Management Utility Functions. */ +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); -#endif /* _SOC_APOLLOLAKE_PM_H_ */ +#endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c new file mode 100644 index 0000000..30c9abb --- /dev/null +++ b/src/soc/intel/apollolake/pmutil.c @@ -0,0 +1,362 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your option) + * any later version. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <rules.h> +#include <device/pci_def.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> + + +static void print_num_status_bits(int num_bits, uint32_t status, + const char * const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static uint32_t print_smi_status(uint32_t smi_sts) +{ + static const char * const smi_sts_bits[] = { + [2] = "BIOS", + [3] = "LEGACY USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [10]= "GPIO_SMI", + [12] = "MCSMI", + [13] = "TCO", + [14] = "PERIODIC", + [15] = "SERIRQ", + [16] = "SMBUS_SMI", + [17] = "XHCI", + [18] = "HOST_SMBUS", + [19] = "SCS", + [20] = "PCI_EXP_SMI", + [21] = "SCC2", + [25] = "SPI_SSMI", + [26] = "SPI", + [27] = "OCP_CSE", + }; + + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; +} + +static uint32_t reset_smi_status(void) +{ + uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS); + outl(smi_sts, ACPI_PMIO_BASE + SMI_STS); + return smi_sts; +} + +uint32_t clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} + +void enable_smi(uint32_t mask) +{ + uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + smi_en |= mask; + outl(smi_en, ACPI_PMIO_BASE + SMI_EN); +} + +void disable_smi(uint32_t mask) +{ + uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + smi_en &= ~mask; + outl(smi_en, ACPI_PMIO_BASE + SMI_EN); +} + +void enable_pm1_control(uint32_t mask) +{ + uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + pm1_cnt |= mask; + outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); +} + +void disable_pm1_control(uint32_t mask) +{ + uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + pm1_cnt &= ~mask; + outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS); + return pm1_sts; +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char * const pm1_sts_bits[] = { + [0] = "TMROF", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [11] = "PRBTNOR", + [13] = "USB", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +uint16_t clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} + +void enable_pm1(uint16_t events) +{ + outw(events, ACPI_PMIO_BASE + PM1_EN); +} + +static uint32_t print_tco_status(uint32_t tco_sts) +{ + static const char * const tco_sts_bits[] = { + [3] = "TIMEOUT", + [17] = "SECOND_TO", + }; + + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; +} + +static uint32_t reset_tco_status(void) +{ + uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT); + + outl(tco_sts, ACPI_PMIO_BASE + TCO_STS); + return tco_sts & tco_en; +} + +uint32_t clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} + +void enable_gpe(uint32_t mask) +{ + uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + gpe0a_en |= mask; + outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); +} + +void disable_gpe(uint32_t mask) +{ + uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + gpe0a_en &= ~mask; + outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); +} + +void disable_all_gpe(void) +{ + disable_gpe(~0); +} + + +static uint32_t reset_gpe_status(void) +{ + uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); + outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0)); + return gpe_sts; +} + +static uint32_t print_gpe_sts(uint32_t gpe_sts) +{ + static const char * const gpe_sts_bits[] = { + [0] = "PCIE_SCI", + [2] = "SWGPE", + [3] = "PCIE_WAKE0", + [4] = "PUNIT", + [6] = "PCIE_WAKE1", + [7] = "PCIE_WAKE2", + [8] = "PCIE_WAKE3", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "CSE_PME", + [12] = "XDCI_PME", + [13] = "XHCI_PME", + [14] = "AVS_PME", + [15] = "GPIO_TIER1_SCI", + [16] = "SMB_WAK", + [17] = "SATA_PME", + }; + + if (!gpe_sts) + return gpe_sts; + + printk(BIOS_DEBUG, "GPE0a_STS: "); + print_num_status_bits(18, gpe_sts, gpe_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return gpe_sts; +} + +uint32_t clear_gpe_status(void) +{ + return print_gpe_sts(reset_gpe_status()); +} + +static uint32_t reset_alt_status(void) +{ + return 0; +} + +static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +{ + uint32_t alt_gpio_sts; + static const char * const alt_gpio_smi_sts_bits[] = { + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", + [10] = "CORE_GPIO_2", + [11] = "CORE_GPIO_3", + [12] = "CORE_GPIO_4", + [13] = "CORE_GPIO_5", + [14] = "CORE_GPIO_6", + [15] = "CORE_GPIO_7", + }; + + /* Status bits are in the upper 16 bits. */ + alt_gpio_sts = alt_gpio_smi >> 16; + if (!alt_gpio_sts) + return alt_gpio_smi; + + printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); + print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return alt_gpio_smi; +} + +uint32_t clear_alt_status(void) +{ + return print_alt_sts(reset_alt_status()); +} + +void clear_pmc_status(void) +{ + uint32_t prsts; + uint32_t gen_pmcon1; + + prsts = read32((void *)(PMC_BAR0 + PRSTS)); + gen_pmcon1 = read32((void *)(PMC_BAR0 + GEN_PMCON1)); + + /* Clear the status bits. The RPS field is cleared on a 0 write. */ + write32((void *)(PMC_BAR0 + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((void *)(PMC_BAR0 + PRSTS), prsts); +} + + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int chipset_prev_sleep_state(struct chipset_power_state *ps) +{ + /* Default to S0. */ + int prev_sleep_state = SLEEP_STATE_S0; + + if (ps->pm1_sts & WAK_STS) { + switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + case SLP_TYP_S3: + prev_sleep_state = SLEEP_STATE_S3; + break; +#endif + case SLP_TYP_S5: + prev_sleep_state = SLEEP_STATE_S5; + break; + } + /* Clear SLP_TYP. */ + outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT); + } + return prev_sleep_state; +} + +/* returns prev_sleep_state */ +int fill_power_state(struct chipset_power_state *ps) +{ + ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN); + ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + ps->gpe0a_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); + ps->gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + ps->prsts = read32((void *)(PMC_BAR0 + PRSTS)); + ps->gen_pmcon1 =read32((void *)(PMC_BAR0 + GEN_PMCON1)); + ps->gen_pmcon2 = read32((void *)(PMC_BAR0 + GEN_PMCON2)); + + ps->prev_sleep_state = chipset_prev_sleep_state(ps); + + printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + printk(BIOS_DEBUG, "gpe0a_sts: %08x gpe0a_en: %08x tco_sts: %08x\n", + ps->gpe0a_sts, ps->gpe0a_en, ps->tco_sts); + printk(BIOS_DEBUG, "gpe0b_sts: %08x gpe0b_en: %08x\n", + ps->gpe0b_sts, ps->gpe0b_en); + printk(BIOS_DEBUG, "gpe0c_sts: %08x gpe0c_en: %08x\n", + ps->gpe0c_sts, ps->gpe0c_en); + printk(BIOS_DEBUG, "gpe0d_sts: %08x gpe0d_en: %08x\n", + ps->gpe0d_sts, ps->gpe0d_en); + printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", + ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", + inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); + return ps->prev_sleep_state; +}

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill in ACPI MADT table
by Andrey Petrov 08 Apr '16

08 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13373 -gerrit commit 0adbbcfe60db064680dd1448da48df5b57ac8ec6 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:33:21 2015 -0800 soc/apollolake/acpi: Fill in ACPI MADT table ACPI MADT tables required to describe the multiprocessor interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 3677477..dda83b4 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,6 +11,8 @@ */ #include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -25,11 +27,32 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -unsigned long acpi_fill_madt(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { + int sci = acpi_sci_irq(); + uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + return current; } +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + static int acpi_sci_irq(void) { int sci_irq = 9;

1 0

Patch set updated for coreboot: soc/apollolake: Add Helper functions to access Power Management Registers
by Hannah Williams 08 Apr '16

08 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14289 -gerrit commit 9abde3a7f85bf42571483d1edb5b83498427b0ac Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Feb 4 20:13:34 2016 -0800 soc/apollolake: Add Helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/include/soc/pm.h | 93 +++++++- src/soc/intel/apollolake/pmutil.c | 358 ++++++++++++++++++++++++++++++ 3 files changed, 449 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 70ab515..8f2960d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,8 +25,10 @@ romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += pmutil.c smm-y += placeholders.c +smm-y += pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -38,6 +40,7 @@ ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += northbridge.c +ramstage-y += pmutil.c postcar-y += exit_car.S postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 286406b..1b68fc5 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -13,19 +13,102 @@ #ifndef _SOC_APOLLOLAKE_PM_H_ #define _SOC_APOLLOLAKE_PM_H_ -/* ACPI_BASE_ADDRESS / PMBASE */ +/* ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PWRBTN_STS (1 << 8) + #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) + #define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define SCI_EN (1 << 0) + #define PM1_TMR 0x08 #define SMI_EN 0x40 +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ + #define SMI_STS 0x44 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c +#define TCO_STS 0x64 +#define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 #define GPE0_REG_MAX 4 -#define GPE0_STS(x) (0x20 + (x * 4)) -#define GPE0_EN(x) (0x30 + (x * 4)) +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) +#define PME_B0_EN (1 << 13) + + + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x1000 +#define GEN_PMCON1 0x1020 +# define PWR_FLR (1 << 16) +# define SUS_PWR_FLR (1 << 14) +#define GEN_PMCON2 0x1024 +# define RPS (1 << 2) + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; + int prev_sleep_state; +} __attribute__((packed)); + +int fill_power_state(struct chipset_power_state *ps); +int chipset_prev_sleep_state(struct chipset_power_state *ps); + +/* Power Management Utility Functions. */ +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); -#endif /* _SOC_APOLLOLAKE_PM_H_ */ +#endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c new file mode 100644 index 0000000..f618b81 --- /dev/null +++ b/src/soc/intel/apollolake/pmutil.c @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your option) + * any later version. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <rules.h> +#include <device/pci_def.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> + + +static void print_num_status_bits(int num_bits, uint32_t status, + const char * const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static uint32_t print_smi_status(uint32_t smi_sts) +{ + static const char * const smi_sts_bits[] = { + [2] = "BIOS", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", + [10]= "GPIO_SMI", + [12] = "MCSMI", + [13] = "TCO", + [14] = "PERIODIC", + [15] = "SERIRQ", + [16] = "SMBUS_SMI", + [17] = "XHCI", + [18] = "HOST_SMBUS", + [19] = "SCS", + [20] = "PCI_EXP_SMI", + [26] = "SPI", + }; + + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_num_status_bits(27, smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; +} + +static uint32_t reset_smi_status(void) +{ + uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS); + outl(smi_sts, ACPI_PMIO_BASE + SMI_STS); + return smi_sts; +} + +uint32_t clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} + +void enable_smi(uint32_t mask) +{ + uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + smi_en |= mask; + outl(smi_en, ACPI_PMIO_BASE + SMI_EN); +} + +void disable_smi(uint32_t mask) +{ + uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + smi_en &= ~mask; + outl(smi_en, ACPI_PMIO_BASE + SMI_EN); +} + +void enable_pm1_control(uint32_t mask) +{ + uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + pm1_cnt |= mask; + outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); +} + +void disable_pm1_control(uint32_t mask) +{ + uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + pm1_cnt &= ~mask; + outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS); + return pm1_sts; +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char * const pm1_sts_bits[] = { + [0] = "TMROF", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [11] = "PRBTNOR", + [13] = "USB", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_num_status_bits(16, pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +uint16_t clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} + +void enable_pm1(uint16_t events) +{ + outw(events, ACPI_PMIO_BASE + PM1_EN); +} + +static uint32_t print_tco_status(uint32_t tco_sts) +{ + static const char * const tco_sts_bits[] = { + [3] = "TIMEOUT", + [17] = "SECOND_TO", + }; + + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_num_status_bits(18, tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; +} + +static uint32_t reset_tco_status(void) +{ + uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT); + + outl(tco_sts, ACPI_PMIO_BASE + TCO_STS); + return tco_sts & tco_en; +} + +uint32_t clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} + +void enable_gpe(uint32_t mask) +{ + uint32_t gpe0_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + gpe0_en |= mask; + outl(gpe0_en, ACPI_PMIO_BASE + GPE0_EN(0)); +} + +void disable_gpe(uint32_t mask) +{ + uint32_t gpe0_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + gpe0_en &= ~mask; + outl(gpe0_en, ACPI_PMIO_BASE + GPE0_EN(0)); +} + +void disable_all_gpe(void) +{ + disable_gpe(~0); +} + + +static uint32_t reset_gpe_status(void) +{ + uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); + outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0)); + return gpe_sts; +} + +static uint32_t print_gpe_sts(uint32_t gpe_sts) +{ + static const char * const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [3] = "PCIE_WAKE0", + [4] = "PUNIT", + [5] = "GUNIT", + [6] = "PCIE_WAKE1", + [7] = "PCIE_WAKE2", + [8] = "PCIE_WAKE3", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "CSE_PME", + [12] = "XDCI_PME", + [13] = "XHCI_PME", + [14] = "AVS_PME", + [15] = "GPIO_TIER1_SCI", + [16] = "SMB_WAK", + [17] = "SATA_PME", + }; + + if (!gpe_sts) + return gpe_sts; + + printk(BIOS_DEBUG, "GPE0a_STS: "); + print_num_status_bits(18, gpe_sts, gpe_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return gpe_sts; +} + +uint32_t clear_gpe_status(void) +{ + return print_gpe_sts(reset_gpe_status()); +} + +static uint32_t reset_alt_status(void) +{ + return 0; +} + +static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +{ + uint32_t alt_gpio_sts; + static const char * const alt_gpio_smi_sts_bits[] = { + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", + [10] = "CORE_GPIO_2", + [11] = "CORE_GPIO_3", + [12] = "CORE_GPIO_4", + [13] = "CORE_GPIO_5", + [14] = "CORE_GPIO_6", + [15] = "CORE_GPIO_7", + }; + + /* Status bits are in the upper 16 bits. */ + alt_gpio_sts = alt_gpio_smi >> 16; + if (!alt_gpio_sts) + return alt_gpio_smi; + + printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); + print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return alt_gpio_smi; +} + +uint32_t clear_alt_status(void) +{ + return print_alt_sts(reset_alt_status()); +} + +void clear_pmc_status(void) +{ + uint32_t prsts; + uint32_t gen_pmcon1; + + prsts = read32((void *)(PMC_BAR0 + PRSTS)); + gen_pmcon1 = read32((void *)(PMC_BAR0 + GEN_PMCON1)); + + /* Clear the status bits. The RPS field is cleared on a 0 write. */ + write32((void *)(PMC_BAR0 + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((void *)(PMC_BAR0 + PRSTS), prsts); +} + + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int chipset_prev_sleep_state(struct chipset_power_state *ps) +{ + /* Default to S0. */ + int prev_sleep_state = SLEEP_STATE_S0; + + if (ps->pm1_sts & WAK_STS) { + switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + case SLP_TYP_S3: + prev_sleep_state = SLEEP_STATE_S3; + break; + #endif + case SLP_TYP_S5: + prev_sleep_state = SLEEP_STATE_S5; + break; + } + + /* Clear SLP_TYP. */ + outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT); + } + + + return prev_sleep_state; +} + +/* returns prev_sleep_state */ +int fill_power_state(struct chipset_power_state *ps) +{ + ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN); + ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + ps->gpe0_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); + ps->gpe0_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + ps->prsts = read32((void *)(PMC_BAR0 + PRSTS)); + ps->gen_pmcon1 =read32((void *)(PMC_BAR0 + GEN_PMCON1)); + ps->gen_pmcon2 = read32((void *)(PMC_BAR0 + GEN_PMCON2)); + + ps->prev_sleep_state = chipset_prev_sleep_state(ps); + + printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", + ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", + ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", + inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); + return ps->prev_sleep_state; +}

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Patch merged into coreboot/master: superio/winbond/w83667hg-a: Set SPI device mask correctly
by gerrit＠coreboot.org 08 Apr '16

08 Apr '16

the following patch was just integrated into master: commit bdd9df76379243bee5b5ba39f2f7034e31b8a762 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 23:56:51 2016 -0500 superio/winbond/w83667hg-a: Set SPI device mask correctly This resolves error messages of the form: ERROR: device PNP: 002e.6 index 98 has no mask. Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14272 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/14272 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Override default to_flash_offset implementation
by gerrit＠coreboot.org 08 Apr '16

08 Apr '16

the following patch was just integrated into master: commit 0a4b47ee2d5fabec468aebbfbd0f27dc50ebf231 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 3 13:16:36 2016 -0800 soc/intel/apollolake: Override default to_flash_offset implementation The default nvm_mmio_to_flash_offset() implementation used by NVM code in intel/common does not work on apollolake. As a result, provide the correct override. Change-Id: I01a94f90dfdd33586a4aac5c05dd8c73e8804437 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14248 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14248 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/common/nvm: Allow overriding to_flash_offset() function
by gerrit＠coreboot.org 08 Apr '16

08 Apr '16

the following patch was just integrated into master: commit 922064162bb4695a276bd46ba0a928e94825ac8b Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 3 10:58:30 2016 -0800 soc/intel/common/nvm: Allow overriding to_flash_offset() function On apollolake, the flash is memory-mapped differently, and the default MMIO to flash calculation does not produce correct results. While the long-term solution is to rewrite the NVM functionality to keep the flash offset as part of its context, as a temporary measure, allow overriding the to_flash_offset() function by declaring it weak. Change-Id: Ic54baeba2441a08cfe1a47e235747797f6efb59b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14247 for details. -gerrit

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Patch set updated for coreboot: util/nvramtool/cli/nvramtool.c: Add newline to error message
by Martin Roth 08 Apr '16

08 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/6553 -gerrit commit 1a7563124d859e2c8ca046242152a9698727dbdf Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Aug 9 09:33:59 2014 +0200 util/nvramtool/cli/nvramtool.c: Add newline to error message "CMOS parameter touchpad not found" string needs '\n' termination. Change-Id: Ied431dbc9f94d82e1f4716cfb89ea3d6cf513703 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/nvramtool/cli/nvramtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 8183572..ac13acc 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -611,7 +611,7 @@ static void set_one_param(const char name[], const char value[]) unsigned long long n; if (is_checksum_name(name) || (e = find_cmos_entry(name)) == NULL) { - fprintf(stderr, "%s: CMOS parameter %s not found.", prog_name, + fprintf(stderr, "%s: CMOS parameter %s not found.\n", prog_name, name); exit(1); }

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Patch set updated for coreboot: util/nvramtool/cli/nvramtool.c: Add newline to error message
by Paul Menzel 08 Apr '16

08 Apr '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/6553 -gerrit commit a137ca52c5dee606a127ab9d99491fdb2286ed4f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Aug 9 09:33:59 2014 +0200 util/nvramtool/cli/nvramtool.c: Add newline to error message "CMOS parameter touchpad not found" string needs '\n' termination. Change-Id: Ied431dbc9f94d82e1f4716cfb89ea3d6cf513703 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/nvramtool/cli/nvramtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index d5acc58..f83825e 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -615,7 +615,7 @@ static void set_one_param(const char name[], const char value[]) unsigned long long n; if (is_checksum_name(name) || (e = find_cmos_entry(name)) == NULL) { - fprintf(stderr, "%s: CMOS parameter %s not found.", prog_name, + fprintf(stderr, "%s: CMOS parameter %s not found.\n", prog_name, name); exit(1); }

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Patch merged into coreboot/master: Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
by gerrit＠coreboot.org 08 Apr '16

08 Apr '16

the following patch was just integrated into master: commit 5a577251263369d259bee033e41584d7c562ca6d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 22:19:43 2016 -0500 Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed" This reverts commit f961becc433bf23fc8744fdfd757f0cdb75c2c62. On studying the BKDG more closely this is not the correct place to enable DIMM parity. Further patches to clarify the parity setup process on Family 15h are forthcoming. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebecd Reviewed-on: https://review.coreboot.org/14271 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14271 for details. -gerrit

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coreboot-gerrit April 2016