coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14447 -gerrit commit de83a6c499a02eb345aad53b5c07f7d326f770bc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:34:03 2016 -0500 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index b354d92..2dd7c15 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -358,9 +358,13 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, uint32_t dword; uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); + printk(BIOS_DEBUG, "%s: Start\n", __func__); + struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; + printk(BIOS_DEBUG, "%s: Node %s: New frequency code: \n", __func__, Node, pDCTstat->TargetFreq); + if (is_fam15h()) { /* Program F2x[1, 0]90[DisDllShutDownSR]=1. */ if (pDCTstat->DIMMValidDCT[0]) { @@ -448,6 +452,8 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, FreqChgCtrlWrd(pMCTstat, pDCTstat, 1); } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void Modify_OnDimmMirror(struct DCTStatStruc *pDCTstat, u8 dct, u8 set)

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Patch set updated for coreboot: nb/amd/mct_ddr3: Run fence training on each node after memory clock change
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14445 -gerrit commit 079626550a1235afab0ab6d934578c527bba2d15 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:08:01 2016 -0500 nb/amd/mct_ddr3: Run fence training on each node after memory clock change The BKDG requires phy fences to be re-trained after a memory clock change. Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked -- without actually following this requirement -- ! Fix the single typo that caused several weeks of delay in putting servers with Kingston RAM (and others) into production... Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 9aadb2c..c8c75e1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -2092,7 +2092,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, if (single_node_number >= 0) { start_node = single_node_number; - end_node = single_node_number; + end_node = single_node_number + 1; } /* FIXME: skip for Ax */

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New patch to review for coreboot: nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14447 -gerrit commit e1d28b8ba8c08b327cd0e682d6aeeb0e0b586498 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:34:03 2016 -0500 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index b354d92..2dd7c15 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -358,9 +358,13 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, uint32_t dword; uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); + printk(BIOS_DEBUG, "%s: Start\n", __func__); + struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; + printk(BIOS_DEBUG, "%s: Node %s: New frequency code: \n", __func__, Node, pDCTstat->TargetFreq); + if (is_fam15h()) { /* Program F2x[1, 0]90[DisDllShutDownSR]=1. */ if (pDCTstat->DIMMValidDCT[0]) { @@ -448,6 +452,8 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, FreqChgCtrlWrd(pMCTstat, pDCTstat, 1); } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void Modify_OnDimmMirror(struct DCTStatStruc *pDCTstat, u8 dct, u8 set)

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New patch to review for coreboot: Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14446 -gerrit commit 540e40e2820a3a5caec213dac15a41475e3c6e80 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:18:36 2016 -0500 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" After substantial testing it has been determined that it is neither required nor safe to disable the DRAM MCA during initial startup. This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32. Tested-On: ASUS KGPE-D16 w/ 1x Kingston 9965516-483.A00LF and 1x Opteron 6262HE Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ------------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 ------ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 20 +++++++++++--------- 3 files changed, 11 insertions(+), 28 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 3582efa..284e890 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8049,19 +8049,6 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); - /* Prevent lockups on parity errors during initial DCT startup */ - if (!pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; - pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; - pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - dword &= ~(0x1 << 2); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - pDCTstat->mca_config_backed_up = 1; - } - /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index aba39c1..a5a3d88 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -581,12 +581,6 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; - /* MCA backup variables */ - uint8_t mca_config_backed_up; - uint8_t sync_flood_on_dram_err; - uint8_t sync_flood_on_any_uc_err; - uint8_t sync_flood_on_uc_dram_ecc_err; - /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 203d112..cef28f4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -116,6 +116,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; + sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -264,15 +275,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore MCA settings */ - if (pDCTstat->mca_config_backed_up) { - val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); - val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); - } } } }

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New patch to review for coreboot: nb/amd/mct_ddr3: Run fence training on each node after memory clock change
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14445 -gerrit commit 98908b162be85d56342e3fdad364fd232f4b794d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:08:01 2016 -0500 nb/amd/mct_ddr3: Run fence training on each node after memory clock change The BKDG requires that phy fences to be re-trained after a memory clock chagne. Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked -- without actually following this requirement -- ! Fix the single typo that caused several weeks of delay putting servers with Kingston RAM (and others) into production... Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 9aadb2c..c8c75e1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -2092,7 +2092,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, if (single_node_number >= 0) { start_node = single_node_number; - end_node = single_node_number; + end_node = single_node_number + 1; } /* FIXME: skip for Ax */

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14441 -gerrit commit 190f7f05e1aeb34f6c4e22d249f9a9724c6464ec Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 20 14:00:39 2016 -0500 nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs Certain RDIMMs have inherently large write levelling delays, in some cases exceeding 1.5 MEMCLK. When these DIMMs are utilized, the phase recovery system requires special handling due to the resultant offset exceeding the phase recovery reporting capabilities. Fix an old error where delays > 1.5 MEMCLK were not being programmed (gross delay high bit was not in set range), and restore special delay handling for delays greater than 1.5 MEMCLK. Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 83 +++++++++++++-------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index f246d88..9702126 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -1366,27 +1366,20 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 EccValue = 0; while (ByteLane < lane_count) { - if (is_fam15h()) { - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - } else { - /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) - { - tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; - tempW -= 0xC; - pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); - pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); - } - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - /* Adjust seed gross delay overflow (greater than 3): - * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). - * - Keep original seed gross delay for later reference. - */ - if(grossDelayValue >= 3) - { - grossDelayValue = (grossDelayValue&1)? 1 : 2; - } + /* This subtract 0xC workaround might be temporary. */ + if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { + tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; + tempW -= 0xC; + pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); + pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); } + grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; + /* Adjust seed gross delay overflow (greater than 3): + * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). + * - Keep original seed gross delay for later reference. + */ + if(grossDelayValue >= 3) + grossDelayValue = (grossDelayValue&1)? 1 : 2; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; if (ByteLane < 4) ValueLow |= ((grossDelayValue << 5) | fineDelayValue) << 8*ByteLane; @@ -1405,7 +1398,9 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 } else { - /* Fam10h BKDG Rev. 3.62 2.8.9.9.1 (6) */ + /* Fam10h BKDG: Rev. 3.62 2.8.9.9.1 (6) + * Fam15h BKDG: Rev. 3.14 2.10.5.8.1 + */ index = (u8)(lane_count * dimm); grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; @@ -1433,7 +1428,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 fineStartLoc = (u8)(tempB % 32); fineEndLoc = (u8)(fineStartLoc + 4); grossStartLoc = (u8)(fineEndLoc + 1); - grossEndLoc = (u8)(grossStartLoc + 1); + grossEndLoc = (u8)(grossStartLoc + 2); set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, (u16)addr, fineStartLoc, fineEndLoc,(u32)fineDelayValue); @@ -1498,29 +1493,30 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 gross = get_ADD_DCT_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, (u16)addr, grossStartLoc, grossEndLoc); - printk(BIOS_SPEW, "\tLane %02x raw readback: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x nibble %01x raw readback: %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); - if (!is_fam15h()) { - /* Adjust seed gross delay overflow (greater than 3): - * - Adjust the trained gross delay to the original seed gross delay. + /* Adjust seed gross delay overflow (greater than 3): + * - Adjust the trained gross delay to the original seed gross delay. + */ + if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) + { + gross += pDCTData->WLGrossDelay[index+ByteLane]; + if(pDCTData->WLGrossDelay[index+ByteLane] & 1) + gross -= 1; + else + gross -= 2; + } + else if ((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) + { + /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. + * We will then round the negative number to 0. */ - if(pDCTData->WLGrossDelay[index+ByteLane] >= 3) - { - gross += pDCTData->WLGrossDelay[index+ByteLane]; - if(pDCTData->WLGrossDelay[index+ByteLane] & 1) - gross -= 1; - else - gross -= 2; - } - else if((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) - { - /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. - * We will then round the negative number to 0. - */ - gross = 0; - fine = 0; - } + gross = 0; + fine = 0; } + printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (pre nibble): %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); + + /* Nibble adjustments */ if (nibble == 0) { pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)fine; pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)gross; @@ -1531,6 +1527,5 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)(WLTotalDelay & 0x1f); pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)((WLTotalDelay >> 5) & 0x1f); } - - printk(BIOS_SPEW, "\tLane %02x adjusted value: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (post nibble): %04x\n", ByteLane, nibble, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); }

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Patch merged into coreboot/master: soc/intel/apollolake: Set default memory type to uncacheable
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit 581c42807d358a66c2a4b3680d465a7069feb2f4 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 19 15:49:23 2016 -0700 soc/intel/apollolake: Set default memory type to uncacheable Set the default memory type in MTRRCap register to 0. This ensures that even if the MTRR Enable bit is set in MTRRCap register, the default memory type is still uncacheable. Change-Id: I63e7993f8b65dabbab60e7c1bb8d6d89ef4da9ee Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14428 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/14428 for details. -gerrit

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Patch merged into coreboot/master: AGESA vendorcode: Fix type mismatch
by gerrit＠coreboot.org 20 Apr '16

20 Apr '16

the following patch was just integrated into master: commit defbdcf3e58a7148ecd3c448e4d1e6683d54bd22 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:17:50 2016 +0300 AGESA vendorcode: Fix type mismatch Fix is required to compile AGESA ramstage without raminit. Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14416 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui(a)gmail.com> See https://review.coreboot.org/14416 for details. -gerrit

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Patch merged into coreboot/master: xcompile: support being called from payloads/external/.../.../
by gerrit＠coreboot.org 20 Apr '16

20 Apr '16

the following patch was just integrated into master: commit e0383d2ce8b92b9efaa1e10f7234a7bb607a8a23 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 15 15:27:05 2016 -0700 xcompile: support being called from payloads/external/.../.../ Change-Id: Icc1361fdd3a8369c4b442ce5b8807c549519c93a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14387 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14387 for details. -gerrit

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Patch merged into coreboot/master: imgtec/pistachio: Fix memlayout ASSERT with new binutils
by gerrit＠coreboot.org 20 Apr '16

20 Apr '16

the following patch was just integrated into master: commit 479e31e0907e273b0ca4a8ad5326b1503144637a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 20 09:33:30 2016 -0700 imgtec/pistachio: Fix memlayout ASSERT with new binutils With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions gets confused due to the lack of parentheses grouping the expressions. This fixes the following issue: LINK cbfs/fallback/bootblock.debug mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match! mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match! Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14440 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/14440 for details. -gerrit

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coreboot-gerrit April 2016