coreboot-gerrit April 2016

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14441 -gerrit commit d86ffeb5f5bc0f7ef0d52d09158984af00a12ec1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 20 14:00:39 2016 -0500 nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs Certain RDIMMs have inherently large write levelling delays, in some cases exceeding 1.5 MEMCLK. When these DIMMs are utilized, the phase recovery system requires special handling due to the resultant offset exceeding the phase recovery reporting capabilities. Fix an old error where delays > 1.5 MEMCLK were not being programmed (gross delay high bit was not in set range), and restore special delay handling for delays greater than 1.5 MEMCLK. Also enhance debugging for x4 DIMMs around the affected code. Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 83 +++++++++++++-------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index f246d88..9702126 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -1366,27 +1366,20 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 EccValue = 0; while (ByteLane < lane_count) { - if (is_fam15h()) { - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - } else { - /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) - { - tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; - tempW -= 0xC; - pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); - pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); - } - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - /* Adjust seed gross delay overflow (greater than 3): - * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). - * - Keep original seed gross delay for later reference. - */ - if(grossDelayValue >= 3) - { - grossDelayValue = (grossDelayValue&1)? 1 : 2; - } + /* This subtract 0xC workaround might be temporary. */ + if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { + tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; + tempW -= 0xC; + pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); + pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); } + grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; + /* Adjust seed gross delay overflow (greater than 3): + * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). + * - Keep original seed gross delay for later reference. + */ + if(grossDelayValue >= 3) + grossDelayValue = (grossDelayValue&1)? 1 : 2; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; if (ByteLane < 4) ValueLow |= ((grossDelayValue << 5) | fineDelayValue) << 8*ByteLane; @@ -1405,7 +1398,9 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 } else { - /* Fam10h BKDG Rev. 3.62 2.8.9.9.1 (6) */ + /* Fam10h BKDG: Rev. 3.62 2.8.9.9.1 (6) + * Fam15h BKDG: Rev. 3.14 2.10.5.8.1 + */ index = (u8)(lane_count * dimm); grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; @@ -1433,7 +1428,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 fineStartLoc = (u8)(tempB % 32); fineEndLoc = (u8)(fineStartLoc + 4); grossStartLoc = (u8)(fineEndLoc + 1); - grossEndLoc = (u8)(grossStartLoc + 1); + grossEndLoc = (u8)(grossStartLoc + 2); set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, (u16)addr, fineStartLoc, fineEndLoc,(u32)fineDelayValue); @@ -1498,29 +1493,30 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 gross = get_ADD_DCT_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, (u16)addr, grossStartLoc, grossEndLoc); - printk(BIOS_SPEW, "\tLane %02x raw readback: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x nibble %01x raw readback: %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); - if (!is_fam15h()) { - /* Adjust seed gross delay overflow (greater than 3): - * - Adjust the trained gross delay to the original seed gross delay. + /* Adjust seed gross delay overflow (greater than 3): + * - Adjust the trained gross delay to the original seed gross delay. + */ + if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) + { + gross += pDCTData->WLGrossDelay[index+ByteLane]; + if(pDCTData->WLGrossDelay[index+ByteLane] & 1) + gross -= 1; + else + gross -= 2; + } + else if ((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) + { + /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. + * We will then round the negative number to 0. */ - if(pDCTData->WLGrossDelay[index+ByteLane] >= 3) - { - gross += pDCTData->WLGrossDelay[index+ByteLane]; - if(pDCTData->WLGrossDelay[index+ByteLane] & 1) - gross -= 1; - else - gross -= 2; - } - else if((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) - { - /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. - * We will then round the negative number to 0. - */ - gross = 0; - fine = 0; - } + gross = 0; + fine = 0; } + printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (pre nibble): %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); + + /* Nibble adjustments */ if (nibble == 0) { pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)fine; pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)gross; @@ -1531,6 +1527,5 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)(WLTotalDelay & 0x1f); pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)((WLTotalDelay >> 5) & 0x1f); } - - printk(BIOS_SPEW, "\tLane %02x adjusted value: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (post nibble): %04x\n", ByteLane, nibble, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); }

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Patch set updated for coreboot: xcompile: rename riscv to riscv64
by Stefan Reinauer 21 Apr '16

21 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14257 -gerrit commit 26d4957e3d717b949301f38960f60f8ef107e9f1 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Tue Apr 5 23:43:59 2016 +0800 xcompile: rename riscv to riscv64 In newer toolchain with binutils 2.26 and GCC 5.3.0, we build binutils and GCC with machine type riscv32 and riscv64 instead of riscv. We can see it in this riscv-gnu-toolchain commit: https://github.com/riscv/riscv-gnu-toolchain/commit/dedbf07 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Change-Id: Id552859ec256d80108e073d25cd51dd1fc3fbfac --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 2479c39..1b79ddc 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -329,7 +329,7 @@ arch_config_arm64() { arch_config_riscv() { TARCH="riscv" TBFDARCHS="littleriscv" - TCLIST="riscv" + TCLIST="riscv64" TWIDTH="64" TABI="elf" }

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Patch merged into coreboot/master: arch/riscv/tables: remove confusion over write_tables()
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit 0eb1f1cba9080f2ab11d5492842f4d3c3c09af17 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 13:42:27 2016 -0500 arch/riscv/tables: remove confusion over write_tables() Apparently the memo was missed about the write_tables() signature. Fix the confusion. Change-Id: I8ef367345dd54584c57e9d5cd8cc3d81ce109fef Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14421 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14421 for details. -gerrit

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Patch merged into coreboot/master: arch/power8/tables: remove confusion over write_tables()
by gerrit＠coreboot.org 21 Apr '16

21 Apr '16

the following patch was just integrated into master: commit f7dca0a27599ae05e4d7dad9fde8dd34f6d176fd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 13:41:16 2016 -0500 arch/power8/tables: remove confusion over write_tables() Apparently the memo was missed about the write_tables() signature. Fix the confusion. Change-Id: I63924be47d3507d2d7ed006a553414f4ac60d2f9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14420 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14420 for details. -gerrit

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Patch set updated for coreboot: buildgcc: Add option to bootstrap a host gcc
by Nico Huber 21 Apr '16

21 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit b5c0fb9503dc77a5d11d13db5b8bb02d982eb6f3 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 buildgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (building python (-S) works too) o current Arch Linux (x86_64) and with clang host compiler, thus C only: `make BUILDGCC_OPTIONS="-b"` on o Debian 8 "Jessie" (x86_64) o FreeBSD 10.3 (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fae8bd3..df5aa45 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="April 3rd, 2016" -CROSSGCC_VERSION="1.38" +CROSSGCC_DATE="April 20th, 2016" +CROSSGCC_VERSION="1.39" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -30,6 +30,7 @@ LANGUAGES=c DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -342,6 +343,9 @@ build_for_target() build() { if package_uses_targetarch $1; then + if [ $BOOTSTRAP -eq 1 -a ! -f "${TARGETDIR}/.GCC.success" ]; then + build_for_host GCC + fi build_for_target $1 else build_for_host $1 @@ -386,6 +390,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -498,8 +504,35 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } - -build_GCC() { +bootstrap_GCC() { + CC="$CC" \ + CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + CXXFLAGS="$HOSTCFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CXXFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-shared --disable-multilib \ + --disable-libssp --disable-libquadmath --disable-libcc1 \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ + --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ + $MAKE install-gcc \ + install-target-libgcc \ + maybe-install-target-libada \ + maybe-install-target-libstdc++-v3 \ + DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$TARGETDIR/bin/cc || touch .failed +} + +build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" @@ -537,6 +570,14 @@ build_GCC() { fi } +build_GCC() { + if [ "$1" = host ]; then + bootstrap_GCC + else + build_cross_GCC + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed @@ -642,11 +683,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:p:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:l:P:j:D:tSys: $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys: $*) set -- $args fi @@ -662,6 +703,7 @@ while true ; do -c|--clean) shift; clean=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;;

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Patch set updated for coreboot: buildgcc: Add option to bootstrap a host gcc
by Nico Huber 21 Apr '16

21 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit b07a023bc2b8a2b52eb5eff5e3d6a364b281c465 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 buildgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (building python (-S) works too) o current Arch Linux (x86_64) and with clang host compiler, thus C only: `make BUILDGCC_OPTIONS="-b"` on o Debian 8 "Jessie" (x86_64) o FreeBSD 10.3 (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fae8bd3..df5aa45 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="April 3rd, 2016" -CROSSGCC_VERSION="1.38" +CROSSGCC_DATE="April 20th, 2016" +CROSSGCC_VERSION="1.39" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -30,6 +30,7 @@ LANGUAGES=c DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -342,6 +343,9 @@ build_for_target() build() { if package_uses_targetarch $1; then + if [ $BOOTSTRAP -eq 1 -a ! -f "${TARGETDIR}/.GCC.success" ]; then + build_for_host GCC + fi build_for_target $1 else build_for_host $1 @@ -386,6 +390,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -498,8 +504,35 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } - -build_GCC() { +bootstrap_GCC() { + CC="$CC" \ + CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + CXXFLAGS="$HOSTCFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CXXFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-shared --disable-multilib \ + --disable-libssp --disable-libquadmath --disable-libcc1 \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ + --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ + $MAKE install-gcc \ + install-target-libgcc \ + maybe-install-target-libada \ + maybe-install-target-libstdc++-v3 \ + DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$TARGETDIR/bin/cc || touch .failed +} + +build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" @@ -537,6 +570,14 @@ build_GCC() { fi } +build_GCC() { + if [ "$1" = host ]; then + bootstrap_GCC + else + build_cross_GCC + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed @@ -642,11 +683,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:p:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:l:P:j:D:tSys: $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys: $*) set -- $args fi @@ -662,6 +703,7 @@ while true ; do -c|--clean) shift; clean=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;;

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Patch set updated for coreboot: mb/lenovo/T4xx: enable PEG device
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14448 -gerrit commit 3fad8422f834b4fd41917430811eb1428fccb89c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Apr 21 07:15:14 2016 +0200 mb/lenovo/T4xx: enable PEG device Enable the PEG device in devicetree to expose the device if any. This is already default behaviour for T5xx series. Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/devicetree.cb | 1 + src/mainboard/lenovo/t420/devicetree.cb | 2 +- src/mainboard/lenovo/t420s/devicetree.cb | 2 +- src/mainboard/lenovo/t430s/devicetree.cb | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index af92d30..7923046 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -27,6 +27,7 @@ chip northbridge/intel/gm45 device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # VGA subsystemid 0x17aa 0x20e4 ioapic_irq 2 INTA 0x10 diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 8041e5b..65c567c 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -40,7 +40,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on subsystemid 0x17aa 0x21ce end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on subsystemid 0x17aa 0x21ce end # Integrated Graphics Controller diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ca02455..2376d64 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on subsystemid 0x17aa 0x21d2 end # host bridge - device pci 01.0 off end # NVIDIA Corporation GF119M [NVS 4200M] + device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 7b83fbc..8c0f10f 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on subsystemid 0x17aa 0x21fb end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on subsystemid 0x17aa 0x21fb end # Integrated Graphics Controller

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Patch set updated for coreboot: mainboard/lenovo: add cmos layout for hybrid graphics
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12898 -gerrit commit ba2e740420d9d7f093933f5f218504c98211d58a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 14:03:15 2015 +0100 mainboard/lenovo: add cmos layout for hybrid graphics Add cmos layout vga_primary_is_peg and vga_secondary_powersave. vga_secondary_powersave defaults to true and must remain true ! Using two GPUs at the same time isn't supported at time by the hybrid graphics driver and will result in black screen. Toggling vga_primary_is_peg allow switching between integrated and dedicated GPU using nvramtool. Tested on Lenovo T520 using Nvidia NVS 5200m. Change-Id: I97418f421fb1e525752c32ba886c7c78e8d3aa24 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/cmos.default | 2 ++ src/mainboard/lenovo/t400/cmos.layout | 2 ++ src/mainboard/lenovo/t420/cmos.default | 2 ++ src/mainboard/lenovo/t420/cmos.layout | 4 +++- src/mainboard/lenovo/t420s/cmos.default | 2 ++ src/mainboard/lenovo/t420s/cmos.layout | 4 +++- src/mainboard/lenovo/t430s/cmos.default | 2 ++ src/mainboard/lenovo/t430s/cmos.layout | 4 +++- src/mainboard/lenovo/t520/cmos.default | 2 ++ src/mainboard/lenovo/t520/cmos.layout | 4 +++- src/mainboard/lenovo/t530/cmos.default | 2 ++ src/mainboard/lenovo/t530/cmos.layout | 4 +++- 12 files changed, 29 insertions(+), 5 deletions(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index ac9f96d..f757425 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,5 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 0c12458..f084e5b 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -78,6 +78,8 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size +944 1 e 1 vga_primary_is_peg +945 1 e 1 vga_secondary_powersave # coreboot config options: EC 952 8 h 0 volume diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 1b8e212..885183f 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -14,3 +14,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index bf0f195..915656c 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 1b8e212..885183f 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -14,3 +14,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 4362840..68b96cd 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 00e8863..1c4d076 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -15,3 +15,5 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 16b499a..b2e4246 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 00e8863..1c4d076 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -15,3 +15,5 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 2cf3629..40d211a 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 00e8863..1c4d076 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -15,3 +15,5 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index e21c197..c44427a 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume

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Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit 0858fbca3bee767a0f9ee68afebab92f48fc6819 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Depends on change id: I97418f421fb1e525752c32ba886c7c78e8d3aa24 Ie37ec4aeae8ab49fe8e26438c430911d1815551c Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 ++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 107 +++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + src/southbridge/intel/i82801ix/Kconfig | 1 + 9 files changed, 127 insertions(+) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..68a5952 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +static void hybrid_graphics_enable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Switching panel to discrete GPU\n"); + dev->enabled = 1; + + /* Enable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 1; +} + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Switching panel to integrated GPU\n"); + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + dev->vendor, dev->device, bus_path(dev->bus)); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; + diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index d74a813..a444bf8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 935e659..feacb51 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bb898cf..e7ed90b 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SANDYBRIDGE_IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c70581a..ee5dd81 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c1d0625..085711b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 2822774..b3e5069 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS + select SOUTHBRIDGE_INTEL_COMMON_GPIO if SOUTHBRIDGE_INTEL_I82801IX

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New patch to review for coreboot: mb/lenovo/T4xx: enable PEG device
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14448 -gerrit commit aa8c8ae009fd50a1ef6a4b16b3903bf108eb0e8d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Apr 21 07:15:14 2016 +0200 mb/lenovo/T4xx: enable PEG device Enable the PEG device in devicetree to expose the device if any. This is already default behaviour for T5xx series. Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/devicetree.cb | 1 + src/mainboard/lenovo/t420/devicetree.cb | 2 +- src/mainboard/lenovo/t420s/devicetree.cb | 2 +- src/mainboard/lenovo/t430s/devicetree.cb | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index af92d30..7923046 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -27,6 +27,7 @@ chip northbridge/intel/gm45 device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # VGA subsystemid 0x17aa 0x20e4 ioapic_irq 2 INTA 0x10 diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 8041e5b..65c567c 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -40,7 +40,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on subsystemid 0x17aa 0x21ce end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on subsystemid 0x17aa 0x21ce end # Integrated Graphics Controller diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ca02455..2376d64 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on subsystemid 0x17aa 0x21d2 end # host bridge - device pci 01.0 off end # NVIDIA Corporation GF119M [NVS 4200M] + device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 7b83fbc..8c0f10f 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on subsystemid 0x17aa 0x21fb end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on subsystemid 0x17aa 0x21fb end # Integrated Graphics Controller

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coreboot-gerrit April 2016