coreboot-gerrit April 2016

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Patch set updated for coreboot: Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12895 -gerrit commit 2feeb5b3854997118a2cdd0129554bbc7a761371 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 13:21:43 2015 +0100 Revert "mainboard/lenovo/t400: Add initial hybrid graphics support" This reverts commit 59597ead1f26d4c18997bda81b2ec33e52973b80. Will be replaced by lenovo common hybrid driver. Change-Id: I994114734fa931926c34ed04305cddfbeb429b62 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/cmos.default | 1 - src/mainboard/lenovo/t400/cmos.layout | 7 -- src/mainboard/lenovo/t400/romstage.c | 143 --------------------------------- 3 files changed, 151 deletions(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 98ce970..ac9f96d 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,4 +13,3 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI -hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 8e642f8..0c12458 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -79,10 +79,6 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size -# coreboot config options: graphics -944 2 e 12 hybrid_graphics_mode -#946 6 r 0 unused - # coreboot config options: EC 952 8 h 0 volume @@ -136,9 +132,6 @@ enumerations 11 3 128M 11 5 96M 11 6 160M -12 0 Integrated Only -12 1 Discrete Only -12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 147131f..486b738 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -34,118 +33,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) -#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 -#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 -#define HYBRID_GRAPHICS_SWITCHABLE 2 - -#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 -#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 - -#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 - -#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 -#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 - -static void hybrid_graphics_configure_switchable_graphics(bool enable) -{ - uint32_t tmp; - - if (enable) { - /* Disable integrated graphics legacy VGA cycles */ - tmp = pci_read_config16(MCH_DEV, D0F0_GGC); - pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); - - /* Enable secondary VGA controller */ - tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); - pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); - } - else { - /* Enable integrated graphics legacy VGA cycles */ - tmp = pci_read_config16(MCH_DEV, D0F0_GGC); - pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); - - /* Disable secondary VGA controller */ - tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); - pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); - } -} - -static void hybrid_graphics_set_up_gpio(void) -{ - uint32_t tmp; - - /* Enable hybrid graphics GPIO lines */ - tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); - - tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - - /* Set hybrid graphics control GPIO lines to output */ - tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); - - tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); - - /* Set hybrid graphics detect GPIO lines to input */ - tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); - tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); -} - -static bool hybrid_graphics_installed(void) -{ - if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) - return false; - else - return true; -} - -static void hybrid_graphics_switch_to_integrated_graphics(void) -{ - uint32_t tmp; - - /* Disable switchable graphics */ - hybrid_graphics_configure_switchable_graphics(false); - - /* Configure muxes */ - tmp = inl(DEFAULT_GPIOBASE + GP_LVL); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL); - - tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); - tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); -} - -static void hybrid_graphics_switch_to_discrete_graphics(void) -{ - uint32_t tmp; - - /* Disable switchable graphics */ - hybrid_graphics_configure_switchable_graphics(false); - - /* Configure muxes */ - tmp = inl(DEFAULT_GPIOBASE + GP_LVL); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL); - - tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); - tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; - outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); -} - -static void hybrid_graphics_switch_to_dual_graphics(void) -{ - /* Enable switchable graphics */ - hybrid_graphics_configure_switchable_graphics(true); -} - static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -207,31 +94,6 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); - uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; - get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); - - /* Set up hybrid graphics */ - hybrid_graphics_set_up_gpio(); - if (hybrid_graphics_installed()) { - /* Select appropriate hybrid graphics device */ - printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); - if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) - hybrid_graphics_switch_to_integrated_graphics(); - else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) - hybrid_graphics_switch_to_discrete_graphics(); - else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) - hybrid_graphics_switch_to_integrated_graphics(); - /* Switchable graphics are fully enabled after raminit */ - /* FIXME - * Enabling switchable graphics prevents bootup! - * Debug and fix appropriately... - */ - } - else { - printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); - hybrid_graphics_switch_to_integrated_graphics(); - } - /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); @@ -311,11 +173,6 @@ void main(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); - - if (hybrid_graphics_installed()) - if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) - hybrid_graphics_switch_to_dual_graphics(); - #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc.

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Patch set updated for coreboot: mainboard/lenovo: add cmos layout "dual_graphics_mode"
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12898 -gerrit commit f9b8ec55b76e7932f1dd4e6c5dca43239431f8d7 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 14:03:15 2015 +0100 mainboard/lenovo: add cmos layout "dual_graphics_mode" Add dual graphics cmos layout to allow switching between integrated and dedicated GPU using nvram. Tested on Lenovo T520 using Nvidia NVS 5200m. Change-Id: I97418f421fb1e525752c32ba886c7c78e8d3aa24 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/cmos.default | 2 ++ src/mainboard/lenovo/t400/cmos.layout | 2 ++ src/mainboard/lenovo/t420/cmos.default | 2 ++ src/mainboard/lenovo/t420/cmos.layout | 4 +++- src/mainboard/lenovo/t420s/cmos.default | 2 ++ src/mainboard/lenovo/t420s/cmos.layout | 4 +++- src/mainboard/lenovo/t430s/cmos.default | 2 ++ src/mainboard/lenovo/t430s/cmos.layout | 4 +++- src/mainboard/lenovo/t520/cmos.default | 2 ++ src/mainboard/lenovo/t520/cmos.layout | 4 +++- src/mainboard/lenovo/t530/cmos.default | 2 ++ src/mainboard/lenovo/t530/cmos.layout | 4 +++- 12 files changed, 29 insertions(+), 5 deletions(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index ac9f96d..f757425 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,5 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 0c12458..f084e5b 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -78,6 +78,8 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size +944 1 e 1 vga_primary_is_peg +945 1 e 1 vga_secondary_powersave # coreboot config options: EC 952 8 h 0 volume diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 1b8e212..885183f 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -14,3 +14,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index bf0f195..915656c 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 1b8e212..885183f 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -14,3 +14,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 4362840..68b96cd 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 00e8863..1c4d076 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -15,3 +15,5 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 16b499a..b2e4246 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 00e8863..1c4d076 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -15,3 +15,5 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 2cf3629..40d211a 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 00e8863..1c4d076 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -15,3 +15,5 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +vga_primary_is_peg=Disable +vga_secondary_powersave=Enable diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index e21c197..c44427a 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 vga_primary_is_peg +436 1 e 1 vga_secondary_powersave +#437 3 r 0 unused 440 8 h 0 volume

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Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit 9d003f14b1d997f6600e061ef7719a0bb914956f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Depends on change id: I97418f421fb1e525752c32ba886c7c78e8d3aa24 Ie37ec4aeae8ab49fe8e26438c430911d1815551c Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 ++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 107 +++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + src/southbridge/intel/i82801ix/Kconfig | 1 + 9 files changed, 127 insertions(+) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..68a5952 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +static void hybrid_graphics_enable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Switching panel to discrete GPU\n"); + dev->enabled = 1; + + /* Enable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 1; +} + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Switching panel to integrated GPU\n"); + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + dev->vendor, dev->device, bus_path(dev->bus)); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; + diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index d74a813..a444bf8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 935e659..feacb51 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bb898cf..e7ed90b 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SANDYBRIDGE_IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c70581a..ee5dd81 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c1d0625..085711b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 2822774..b3e5069 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS + select SOUTHBRIDGE_INTEL_COMMON_GPIO if SOUTHBRIDGE_INTEL_I82801IX

1 0

Patch set updated for coreboot: device/device: handle multiple VGA devices
by Patrick Rudolph 21 Apr '16

21 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12897 -gerrit commit ba7ac2235606b8bac2087b6196c748a8ba4801c2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:27:20 2015 +0100 device/device: handle multiple VGA devices Add nvram options "vga_primary_is_peg" and "vga_secondary_powersave" to switch between VGA devices. Both options only affects systems where an onboard and a PEG device is installed. Systems with only one VGA device will always use it as the primary VGA device. vga_primary_is_peg allows to choose the primary VGA device, that is where the VGA Option ROM will be run on. In case of a laptop the panel will be connected to the primary device. vga_primary_is_peg=0 : Onboard is primary vga_primary_is_peg=1 : Dedicated is primary vga_secondary_powersave allows to disable secondary VGA devices to save power. vga_secondary_powersave=0 : Leave secondary VGA devices enabled vga_secondary_powersave=1 : Disable secondary VGA devices Tested on Lenovo T530 using Nvidia NVS 5400m. WIP: Do not commit yet ! Change-Id: Ie37ec4aeae8ab49fe8e26438c430911d1815551c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/device.c | 93 +++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 72 insertions(+), 21 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 9ea32cc..5f2a487 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -50,6 +50,7 @@ #include <arch/ebda.h> #endif #include <timer.h> +#include <option.h> /** Linked list of ALL devices */ struct device *all_devices = &dev_root; @@ -754,28 +755,52 @@ static void avoid_fixed_resources(struct device *dev) } } +static struct device *get_next_vga_dev(struct device *dev) +{ + while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { + if (!dev->enabled) + continue; + + return dev; + } + return NULL; +} + +/* + * Disables all PCI_CLASS_DISPLAY_VGA devices except the one + * given as argument. + * @param dev_primary The device to ignore + */ +static void disable_secondary_vga_devs(struct device *dev_primary) +{ + struct device *dev = NULL; + + while ((dev = get_next_vga_dev(dev))) { + /* disable unused devices to save power */ + if (dev != dev_primary) { + if (dev->ops && dev->ops->disable) + dev->ops->disable(dev); + else + dev->enabled = 0; + } + } +} + device_t vga_pri = 0; static void set_vga_bridge_bits(void) { - /* - * FIXME: Modify set_vga_bridge() so it is less PCI-centric! - * This function knows too much about PCI stuff, it should be just - * an iterator/visitor. - */ - /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard; struct bus *bus; + u8 vga_primary_is_peg; + u8 vga_secondary_powersave; bus = 0; vga = 0; vga_onboard = 0; dev = NULL; - while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { - if (!dev->enabled) - continue; - + while ((dev = get_next_vga_dev(dev))) { printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); if (dev->on_mainboard) { @@ -788,23 +813,49 @@ static void set_vga_bridge_bits(void) dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); } - if (!vga) - vga = vga_onboard; + if ((get_option(&vga_primary_is_peg, "vga_primary_is_peg") != CB_SUCCESS) || + (get_option(&vga_secondary_powersave, "vga_secondary_powersave") != CB_SUCCESS) || + !vga || !vga_onboard) { + /* fallback */ + if (!vga) + vga = vga_onboard; + + if (IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && vga_onboard) + vga = vga_onboard; + + /* If we prefer plugin VGA over chipset VGA, the chipset might + want to know. */ + if (!IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && + (vga != vga_onboard) && + vga_onboard) { + printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); + + if (vga_onboard->ops && vga_onboard->ops->disable) + vga_onboard->ops->disable(vga_onboard); + else + vga_onboard->enabled = 0; + } + + disable_secondary_vga_devs(vga); + } else { + /* have vga and vga_onboard (two or more VGAs) */ - if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) - vga = vga_onboard; + /* make onboard primary if vga_primary_is_peg is disabled */ + if (vga_primary_is_peg == 0) { + printk(BIOS_DEBUG, "Use integrated graphics over plugin.\n"); + vga = vga_onboard; + } - /* If we prefer plugin VGA over chipset VGA, the chipset might - want to know. */ - if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && - vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { - printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); - vga_onboard->ops->disable(vga_onboard); + /* disable secondary VGAs if vga_secondary_powersave is enabled */ + if (vga_secondary_powersave == 1) { + printk(BIOS_DEBUG, "Disable secondary graphics to save power.\n"); + disable_secondary_vga_devs(vga); + } } if (vga) { /* VGA is first add-on card or the only onboard VGA. */ - printk(BIOS_DEBUG, "Setting up VGA for %s\n", dev_path(vga)); + printk(BIOS_DEBUG, "Setting up %s for primary VGA.\n", dev_path(vga)); /* All legacy VGA cards have MEM & I/O space registers. */ vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); vga_pri = vga;

1 0

Patch set updated for coreboot: Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14446 -gerrit commit 21da0c1a8b1ab353af291e3059df385ddb1fa52e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:18:36 2016 -0500 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" After substantial testing it has been determined that it is neither required nor safe to disable the DRAM MCA during initial startup. This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32. Tested-On: ASUS KGPE-D16 w/ 1x Kingston 9965516-483.A00LF and 1x Opteron 6262HE Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ---------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 ----- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 35 ++++++++++++++++++++------ 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 3582efa..284e890 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8049,19 +8049,6 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); - /* Prevent lockups on parity errors during initial DCT startup */ - if (!pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; - pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; - pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - dword &= ~(0x1 << 2); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - pDCTstat->mca_config_backed_up = 1; - } - /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index aba39c1..a5a3d88 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -581,12 +581,6 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; - /* MCA backup variables */ - uint8_t mca_config_backed_up; - uint8_t sync_flood_on_dram_err; - uint8_t sync_flood_on_any_uc_err; - uint8_t sync_flood_on_uc_dram_ecc_err; - /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 203d112..abf40a1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,6 +84,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; + uint32_t dword; + uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; + uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; + mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -116,6 +120,24 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; + sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + + uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); + uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" + "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -265,14 +287,11 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - /* Restore MCA settings */ - if (pDCTstat->mca_config_backed_up) { - val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); - val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); - } + /* Restore previous MCA error handling settings */ + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; + dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); } } }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14447 -gerrit commit 9702cc3f9fd0260f62561889b7f06984002ce2bf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:34:03 2016 -0500 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index b354d92..44ea6e8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -358,9 +358,13 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, uint32_t dword; uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); + printk(BIOS_DEBUG, "%s: Start\n", __func__); + struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; + printk(BIOS_DEBUG, "%s: Node %d: New frequency code: %04x\n", __func__, Node, pDCTstat->TargetFreq); + if (is_fam15h()) { /* Program F2x[1, 0]90[DisDllShutDownSR]=1. */ if (pDCTstat->DIMMValidDCT[0]) { @@ -448,6 +452,8 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, FreqChgCtrlWrd(pMCTstat, pDCTstat, 1); } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void Modify_OnDimmMirror(struct DCTStatStruc *pDCTstat, u8 dct, u8 set)

1 0

Patch set updated for coreboot: Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14446 -gerrit commit c8a334151cc90aa3e5ea59df00ace568e31a58a3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:18:36 2016 -0500 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" After substantial testing it has been determined that it is neither required nor safe to disable the DRAM MCA during initial startup. This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32. Tested-On: ASUS KGPE-D16 w/ 1x Kingston 9965516-483.A00LF and 1x Opteron 6262HE Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ------------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 ------ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 20 +++++++++++--------- 3 files changed, 11 insertions(+), 28 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 3582efa..284e890 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8049,19 +8049,6 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); - /* Prevent lockups on parity errors during initial DCT startup */ - if (!pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; - pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; - pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - dword &= ~(0x1 << 2); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - pDCTstat->mca_config_backed_up = 1; - } - /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index aba39c1..a5a3d88 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -581,12 +581,6 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; - /* MCA backup variables */ - uint8_t mca_config_backed_up; - uint8_t sync_flood_on_dram_err; - uint8_t sync_flood_on_any_uc_err; - uint8_t sync_flood_on_uc_dram_ecc_err; - /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 203d112..cef28f4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -116,6 +116,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; + sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -264,15 +275,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore MCA settings */ - if (pDCTstat->mca_config_backed_up) { - val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); - val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); - } } } }

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Patch set updated for coreboot: nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14447 -gerrit commit 89db29c4eaa35c6a77c3a82c1957b398bea6cde4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:34:03 2016 -0500 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index b354d92..2dd7c15 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -358,9 +358,13 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, uint32_t dword; uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); + printk(BIOS_DEBUG, "%s: Start\n", __func__); + struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; + printk(BIOS_DEBUG, "%s: Node %s: New frequency code: \n", __func__, Node, pDCTstat->TargetFreq); + if (is_fam15h()) { /* Program F2x[1, 0]90[DisDllShutDownSR]=1. */ if (pDCTstat->DIMMValidDCT[0]) { @@ -448,6 +452,8 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, FreqChgCtrlWrd(pMCTstat, pDCTstat, 1); } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void Modify_OnDimmMirror(struct DCTStatStruc *pDCTstat, u8 dct, u8 set)

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14441 -gerrit commit a7909e742fe10d16715e7349a35ebbb89c78cc6d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 20 14:00:39 2016 -0500 nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs Certain RDIMMs have inherently large write levelling delays, in some cases exceeding 1.5 MEMCLK. When these DIMMs are utilized, the phase recovery system requires special handling due to the resultant offset exceeding the phase recovery reporting capabilities. Fix an old error where delays > 1.5 MEMCLK were not being programmed (gross delay high bit was not in set range), and restore special delay handling for delays greater than 1.5 MEMCLK. Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 83 +++++++++++++-------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index f246d88..9702126 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -1366,27 +1366,20 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 EccValue = 0; while (ByteLane < lane_count) { - if (is_fam15h()) { - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - } else { - /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) - { - tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; - tempW -= 0xC; - pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); - pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); - } - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - /* Adjust seed gross delay overflow (greater than 3): - * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). - * - Keep original seed gross delay for later reference. - */ - if(grossDelayValue >= 3) - { - grossDelayValue = (grossDelayValue&1)? 1 : 2; - } + /* This subtract 0xC workaround might be temporary. */ + if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { + tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; + tempW -= 0xC; + pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); + pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); } + grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; + /* Adjust seed gross delay overflow (greater than 3): + * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). + * - Keep original seed gross delay for later reference. + */ + if(grossDelayValue >= 3) + grossDelayValue = (grossDelayValue&1)? 1 : 2; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; if (ByteLane < 4) ValueLow |= ((grossDelayValue << 5) | fineDelayValue) << 8*ByteLane; @@ -1405,7 +1398,9 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 } else { - /* Fam10h BKDG Rev. 3.62 2.8.9.9.1 (6) */ + /* Fam10h BKDG: Rev. 3.62 2.8.9.9.1 (6) + * Fam15h BKDG: Rev. 3.14 2.10.5.8.1 + */ index = (u8)(lane_count * dimm); grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; @@ -1433,7 +1428,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 fineStartLoc = (u8)(tempB % 32); fineEndLoc = (u8)(fineStartLoc + 4); grossStartLoc = (u8)(fineEndLoc + 1); - grossEndLoc = (u8)(grossStartLoc + 1); + grossEndLoc = (u8)(grossStartLoc + 2); set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, (u16)addr, fineStartLoc, fineEndLoc,(u32)fineDelayValue); @@ -1498,29 +1493,30 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 gross = get_ADD_DCT_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, (u16)addr, grossStartLoc, grossEndLoc); - printk(BIOS_SPEW, "\tLane %02x raw readback: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x nibble %01x raw readback: %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); - if (!is_fam15h()) { - /* Adjust seed gross delay overflow (greater than 3): - * - Adjust the trained gross delay to the original seed gross delay. + /* Adjust seed gross delay overflow (greater than 3): + * - Adjust the trained gross delay to the original seed gross delay. + */ + if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) + { + gross += pDCTData->WLGrossDelay[index+ByteLane]; + if(pDCTData->WLGrossDelay[index+ByteLane] & 1) + gross -= 1; + else + gross -= 2; + } + else if ((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) + { + /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. + * We will then round the negative number to 0. */ - if(pDCTData->WLGrossDelay[index+ByteLane] >= 3) - { - gross += pDCTData->WLGrossDelay[index+ByteLane]; - if(pDCTData->WLGrossDelay[index+ByteLane] & 1) - gross -= 1; - else - gross -= 2; - } - else if((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) - { - /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. - * We will then round the negative number to 0. - */ - gross = 0; - fine = 0; - } + gross = 0; + fine = 0; } + printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (pre nibble): %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); + + /* Nibble adjustments */ if (nibble == 0) { pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)fine; pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)gross; @@ -1531,6 +1527,5 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)(WLTotalDelay & 0x1f); pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)((WLTotalDelay >> 5) & 0x1f); } - - printk(BIOS_SPEW, "\tLane %02x adjusted value: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (post nibble): %04x\n", ByteLane, nibble, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); }

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Patch set updated for coreboot: Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
by Timothy Pearson 21 Apr '16

21 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14446 -gerrit commit 0b40e374128859f3d75d820a33c086f4e0039079 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 01:18:36 2016 -0500 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" After substantial testing it has been determined that it is neither required nor safe to disable the DRAM MCA during initial startup. This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32. Tested-On: ASUS KGPE-D16 w/ 1x Kingston 9965516-483.A00LF and 1x Opteron 6262HE Tested-On: ASUS KGPE-D16 w/ 4x Crucial 36KSF1G72PZ-1G6M1 and 1x Opteron 6262HE Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ------------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 ------ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 20 +++++++++++--------- 3 files changed, 11 insertions(+), 28 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 3582efa..284e890 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8049,19 +8049,6 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); - /* Prevent lockups on parity errors during initial DCT startup */ - if (!pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; - pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; - pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - dword &= ~(0x1 << 2); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - pDCTstat->mca_config_backed_up = 1; - } - /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index aba39c1..a5a3d88 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -581,12 +581,6 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; - /* MCA backup variables */ - uint8_t mca_config_backed_up; - uint8_t sync_flood_on_dram_err; - uint8_t sync_flood_on_any_uc_err; - uint8_t sync_flood_on_uc_dram_ecc_err; - /* New for LB Support */ u8 NodePresent; u32 dev_host; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 203d112..cef28f4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -116,6 +116,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node; if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; + sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -264,15 +275,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore MCA settings */ - if (pDCTstat->mca_config_backed_up) { - val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); - val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); - } } } }

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coreboot-gerrit April 2016