coreboot-gerrit April 2016

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New patch to review for coreboot: nb/intel/sandybridge/gma: rework FDI link training
by Patrick Rudolph 20 Apr '16

20 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14438 -gerrit commit 05680e7c0e2039aa5c78fcfdb41ad8a72d4ff48d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Apr 13 14:55:47 2016 +0200 nb/intel/sandybridge/gma: rework FDI link training Deblob the FDI link training function by using existing defines from i915_reg.h. All register writes are the same but has been extended to iterate over all possible values and it reads back the interrupt status registers to probe for successful link training. The functionality is very similar to the i915 Intel kernel module, but instead of a variable count of lanes the VBIOS trains all FDI lanes. Tested on T520: Intel Sandybridge and Cougar Point PCH Needs test on: Intel Sandybridge and Panther Point PCH Change-Id: Iafe2b0bcb6a386b2ed02d33558edb3928da96487 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/intel/gma/i915_reg.h | 4 + .../intel/sandybridge/gma_sandybridge_lvds.c | 201 ++++++++++++++++++--- 2 files changed, 175 insertions(+), 30 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..5c917d2 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -3404,6 +3404,8 @@ #define TRANSC_DPLLB_SEL (1<<8) #define TRANSC_DPLLA_SEL (0) +#define HAS_PCH_CPT(dev) ((dev->device & 0xff00) == 0x1c00) + /* transcoder */ #define _TRANS_HTOTAL_A 0xe0000 @@ -3623,6 +3625,8 @@ #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) +#define FDI_DP_PORT_WIDTH_SHIFT 19 +#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) #define FDI_DP_PORT_WIDTH_X1 (0<<19) #define FDI_DP_PORT_WIDTH_X2 (1<<19) #define FDI_DP_PORT_WIDTH_X3 (2<<19) diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 3b4b64c..906d148 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -30,37 +30,180 @@ #include <device/pci_def.h> #include <device/pci_rom.h> -static void train_link(u8 *mmio) +static const int snb_b_fdi_train_param[] = { + FDI_LINK_TRAIN_400MV_0DB_SNB_B, + FDI_LINK_TRAIN_400MV_6DB_SNB_B, + FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, + FDI_LINK_TRAIN_800MV_0DB_SNB_B, +}; + +static void fdi_normal_train(u8 *mmio, struct device *dev) { - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - - write32(mmio + 0xf000c, 0x2040); - write32(mmio + 0xf000c, 0x2050); - write32(mmio + 0x60100, 0x44000); - write32(mmio + 0xf000c, 0x22050); + u32 temp; + + /* enable normal train */ + temp = read32(mmio + FDI_TX_CTL(0)); + temp &= ~FDI_LINK_TRAIN_NONE; + temp |= FDI_LINK_TRAIN_NONE; + temp |= FDI_TX_ENHANCE_FRAME_ENABLE; + write32(mmio + FDI_TX_CTL(0), temp); + + temp = read32(mmio + FDI_RX_CTL(0)); + if (HAS_PCH_CPT(dev)) { + temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; + temp |= FDI_LINK_TRAIN_NORMAL_CPT; + } else { + temp &= ~FDI_LINK_TRAIN_NONE; + temp |= FDI_LINK_TRAIN_NONE; + } + temp |= FDI_DP_PORT_WIDTH_X4; + temp |= FDI_RX_ENHANCE_FRAME_ENABLE; + temp |= FDI_6BPC; + write32(mmio + FDI_RX_CTL(0), temp); mdelay(1); +} - write32(mmio + 0x000f0018, 0x0000008ff); - write32(mmio + 0x000f1018, 0x0000008ff); - - write32(mmio + 0x000f000c, 0x001a2050); - write32(mmio + 0x00060100, 0x001c4000); - - write32(mmio + 0x00060100, 0x801c4000); - write32(mmio + 0x000f000c, 0x801a2050); +/* this function is similar to the GNU/Linux i915 kernel module: + * drivers/gpu/drm/i915/intel_display.c + */ +static void fdi_train_link(u8 *mmio, struct device *dev) +{ + u32 temp; + int retry, i; - write32(mmio + 0x00060100, 0x801c4000); - write32(mmio + 0x000f000c, 0x801a2050); - mdelay(1); + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); - read32(mmio + 0x000f0014); // = 0x00000100 - write32(mmio + 0x000f0014, 0x00000100); - write32(mmio + 0x00060100, 0x901c4000); - write32(mmio + 0x000f000c, 0x801a2150); - mdelay(1); - read32(mmio + 0x000f0014); // = 0x00000600 + /* disable FDI RX and configure pipe */ + temp = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE; + write32(mmio + FDI_RX_CTL(0), temp); + + temp |= FDI_PCDCLK; + write32(mmio + FDI_RX_CTL(0), temp); + + temp = FDI_TX_ENHANCE_FRAME_ENABLE | FDI_TX_PLL_ENABLE; + write32(mmio + FDI_TX_CTL(0), temp); + + temp = FDI_6BPC | FDI_PCDCLK | FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE; + write32(mmio + FDI_RX_CTL(0), temp); + + /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit + for train result */ + temp = read32(mmio + FDI_RX_IMR(0)); + temp &= ~FDI_RX_SYMBOL_LOCK; + temp &= ~FDI_RX_BIT_LOCK; + temp &= ~FDI_RX_INTER_LANE_ALIGN; + write32(mmio + FDI_RX_IMR(0), temp); + + /* Setup CPU FDI TX and PCH FDI RX */ + temp = read32(mmio + FDI_TX_CTL(0)); + temp &= ~FDI_DP_PORT_WIDTH_MASK; + temp |= FDI_DP_PORT_WIDTH_X4; + temp &= ~FDI_LINK_TRAIN_NONE; + temp |= FDI_LINK_TRAIN_PATTERN_1; + temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; + /* SNB-B */ + temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; + write32(mmio + FDI_TX_CTL(0), temp); + + temp = read32(mmio + FDI_RX_CTL(0)); + temp &= ~FDI_DP_PORT_WIDTH_MASK; + temp |= FDI_DP_PORT_WIDTH_X4; + if (HAS_PCH_CPT(dev)) { + temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; + temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; + } else { + temp &= ~FDI_LINK_TRAIN_NONE; + temp |= FDI_LINK_TRAIN_PATTERN_1; + } + write32(mmio + FDI_RX_CTL(0), temp); + + /* Enable CPU FDI TX and PCH FDI RX */ + temp = read32(mmio + FDI_TX_CTL(0)); + temp |= FDI_TX_ENABLE; + write32(mmio + FDI_TX_CTL(0), temp); + + temp = read32(mmio + FDI_RX_CTL(0)); + temp |= FDI_RX_ENABLE; + write32(mmio + FDI_RX_CTL(0), temp); + udelay(150); + + for (i = 0; i < 4; i++) { + printk(BIOS_INFO, "trying FDI param %d\n", i); + + temp = read32(mmio + FDI_TX_CTL(0)); + temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; + temp |= snb_b_fdi_train_param[i]; + write32(mmio + FDI_TX_CTL(0), temp); + + read32(mmio + FDI_TX_CTL(0)); + udelay(500); + + for (retry = 0; retry < 5; retry++) { + temp = read32(mmio + FDI_RX_IIR(0)); + printk(BIOS_INFO, "FDI_RX_IIR 0x%x\n", temp); + if (temp & FDI_RX_BIT_LOCK) { + write32(mmio + FDI_RX_IIR(0), temp | FDI_RX_BIT_LOCK); + printk(BIOS_INFO, "FDI train 1 done.\n"); + break; + } + udelay(50); + } + if (retry < 5) + break; + } + if (i == 4) + printk(BIOS_CRIT, "FDI train 1 fail!\n"); + + /* Train 2 */ + temp = read32(mmio + FDI_TX_CTL(0)); + temp &= ~FDI_LINK_TRAIN_NONE; + temp |= FDI_LINK_TRAIN_PATTERN_2; + + temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; + /* SNB-B */ + temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; + write32(mmio + FDI_TX_CTL(0), temp); + + temp = read32(mmio + FDI_RX_CTL(0)); + if (HAS_PCH_CPT(dev)) { + temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; + temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; + } else { + temp &= ~FDI_LINK_TRAIN_NONE; + temp |= FDI_LINK_TRAIN_PATTERN_2; + } + write32(mmio + FDI_RX_CTL(0), temp); + + read32(mmio + FDI_RX_CTL(0)); + udelay(150); + + for (i = 0; i < 4; i++) { + printk(BIOS_INFO, "trying FDI param %d\n", i); + + temp = read32(mmio + FDI_TX_CTL(0)); + temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; + temp |= snb_b_fdi_train_param[i]; + write32(mmio + FDI_TX_CTL(0), temp); + udelay(500); + + for (retry = 0; retry < 5; retry++) { + temp = read32(mmio + FDI_RX_IIR(0)); + printk(BIOS_INFO, "FDI_RX_IIR 0x%x\n", temp); + if (temp & FDI_RX_SYMBOL_LOCK) { + write32(mmio + FDI_RX_IIR(0), temp | FDI_RX_SYMBOL_LOCK); + printk(BIOS_INFO, "FDI train 2 done.\n"); + break; + } + udelay(50); + } + if (retry < 5) + break; + } + if (i == 4) + printk(BIOS_CRIT, "FDI train 2 fail!\n"); + printk(BIOS_DEBUG, "FDI train done.\n"); } static void power_port(u8 *mmio) @@ -139,6 +282,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 data_n1 = 0x00800000; u32 link_m1; u32 link_n1 = 0x00080000; + struct device *pch_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) return 0; @@ -259,7 +403,6 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, else current_delta = cur_frequency - target_frequency; - if (best_delta > current_delta) { best_delta = current_delta; pixel_n = candn; @@ -402,7 +545,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, else write32(mmio + CPU_VGACNTRL, 0x20298e); - train_link(mmio); + fdi_train_link(mmio, pch_dev); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); @@ -429,9 +572,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1)); - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0x801a2350); - mdelay(1); + fdi_normal_train(mmio, pch_dev); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC

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New patch to review for coreboot: libpayload: time: split time.h from libpayload.h
by Stef van Os 20 Apr '16

20 Apr '16

Stef van Os (stef.van.os(a)prodrive-technologies.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14437 -gerrit commit c86439f7fa29a962123757ad850c160971176a31 Author: Stef van Os <stef.van.os(a)prodrive-technologies.com> Date: Wed Apr 20 15:22:00 2016 +0200 libpayload: time: split time.h from libpayload.h Move time functions and prototypes from libpayload.h to time.h. In a similar manner to other c libary headers, this change makes porting existing applications to libpayload easier. Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648 Signed-off-by: Stef van Os <stef.van.os(a)prodrive-technologies.com> --- payloads/libpayload/include/libpayload.h | 15 +--------- payloads/libpayload/include/time.h | 50 ++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 1b66bf8..b51abdf 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -56,6 +56,7 @@ #include <stdarg.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <arch/types.h> #include <arch/io.h> #include <arch/virtual.h> @@ -354,20 +355,6 @@ u8 *sha1(const u8 *data, size_t len, u8 *buf); /** @} */ /** - * @defgroup time Time functions - * @{ - */ - -/** System time structure */ -struct timeval { - time_t tv_sec; /**< Seconds */ - suseconds_t tv_usec; /**< Microseconds */ -}; - -int gettimeofday(struct timeval *tv, void *tz); -/** @} */ - -/** * @defgroup info System information functions * This module contains functions that return information about the system * @{ diff --git a/payloads/libpayload/include/time.h b/payloads/libpayload/include/time.h new file mode 100644 index 0000000..25f476c --- /dev/null +++ b/payloads/libpayload/include/time.h @@ -0,0 +1,50 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Prodrive Technologies + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _TIME_H +#define _TIME_H + +#include <stddef.h> + +/** + * @defgroup time Time functions + * @{ + */ + +/** System time structure */ +struct timeval { + time_t tv_sec; /**< Seconds */ + suseconds_t tv_usec; /**< Microseconds */ +}; + +int gettimeofday(struct timeval *tv, void *tz); +/** @} */ + +#endif

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Patch set updated for coreboot: arch/x86: clean up write_tables()
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14431 -gerrit commit 87d401f64a842d7893249e7f7cc8014d8a34a6c3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:53:56 2016 -0500 arch/x86: clean up write_tables() There were quite a number of #if/#endif guards in the write_tables() code. Clean up that function by splitting up the subcomponents into their own individual functions. The same ordering and logic is kept maintained. The changes also benefit the goal of using a common core write_tables() logic so that other architectures don't duplicate large swaths of code. Change-Id: I93f6775d698500f25f72793cbe3fd4eb9d01a20c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/tables.c | 86 +++++++++++++++++++++++++++++++++++---------------- 1 file changed, 60 insertions(+), 26 deletions(-) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 5780cd1..309ac16 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -28,28 +28,10 @@ #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE -void write_tables(void) +static unsigned long write_pirq_table(unsigned long rom_table_end) { - unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ unsigned long high_table_pointer; - rom_table_start = 0xf0000; - rom_table_end = 0xf0000; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyond 0x400. Only GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; - -#if CONFIG_GENERATE_PIRQ_TABLE #define MAX_PIRQ_TABLE_SIZE (4 * 1024) post_code(0x9a); @@ -73,9 +55,13 @@ void write_tables(void) new_high_table_pointer - high_table_pointer); } -#endif + return rom_table_end; +} + +static unsigned long write_mptable(unsigned long rom_table_end) +{ + unsigned long high_table_pointer; -#if CONFIG_GENERATE_MP_TABLE #define MAX_MP_TABLE_SIZE (4 * 1024) post_code(0x9b); @@ -96,9 +82,14 @@ void write_tables(void) printk(BIOS_DEBUG, "MP table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } -#endif /* CONFIG_GENERATE_MP_TABLE */ -#if CONFIG_HAVE_ACPI_TABLES + return rom_table_end; +} + +static unsigned long write_acpi_table(unsigned long rom_table_end) +{ + unsigned long high_table_pointer; + #define MAX_ACPI_SIZE (144 * 1024) post_code(0x9c); @@ -157,9 +148,15 @@ void write_tables(void) rom_table_end = ALIGN(rom_table_end, 1024); } -#endif + return rom_table_end; +} + +static unsigned long write_smbios_table(unsigned long rom_table_end) +{ + unsigned long high_table_pointer; + #define MAX_SMBIOS_SIZE 2048 -#if CONFIG_GENERATE_SMBIOS_TABLES + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); if (high_table_pointer) { unsigned long new_high_table_pointer; @@ -179,7 +176,44 @@ void write_tables(void) printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end); rom_table_end = ALIGN(new_rom_table_end, 16); } -#endif + + return rom_table_end; +} + +void write_tables(void) +{ + unsigned long low_table_start, low_table_end; + unsigned long rom_table_start, rom_table_end; + + /* Even if high tables are configured, some tables are copied both to + * the low and the high area, so payloads and OSes don't need to know + * about the high tables. + */ + unsigned long high_table_pointer; + + rom_table_start = 0xf0000; + rom_table_end = 0xf0000; + + /* Start low addr at 0x500, so we don't run into conflicts with the BDA + * in case our data structures grow beyond 0x400. Only GDT + * and the coreboot table use low_tables. + */ + low_table_start = 0; + low_table_end = 0x500; + + /* This table must be between 0x0f0000 and 0x100000 */ + if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) + rom_table_end = write_pirq_table(rom_table_end); + + /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ + if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) + rom_table_end = write_mptable(rom_table_end); + + if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + rom_table_end = write_acpi_table(rom_table_end); + + if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) + rom_table_end = write_smbios_table(rom_table_end); post_code(0x9e);

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Patch set updated for coreboot: arch: only print cbmem entries in one place
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14430 -gerrit commit 4854df69dea4afde69b659251eb856b834b4603a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 15:33:08 2016 -0500 arch: only print cbmem entries in one place Each arch was calling cbmem_list() in their own write_tables() function. Consolidate that call and place it in common code in write_coreboot_table(). Change-Id: If0d4c84e0f8634e5cef6996b2be4a86cc83c95a9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 3 --- src/arch/arm64/tables.c | 3 --- src/arch/mips/tables.c | 3 --- src/arch/power8/tables.c | 3 --- src/arch/riscv/tables.c | 3 --- src/arch/x86/tables.c | 3 --- src/lib/coreboot_table.c | 3 +++ 7 files changed, 3 insertions(+), 18 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 17a3fd1..eb08e6e 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -50,9 +50,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 17a3fd1..eb08e6e 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -50,9 +50,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 2083442..a3d9939 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -51,9 +51,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index 0a88505..02d1c16 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -51,9 +51,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 17a3fd1..eb08e6e 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -50,9 +50,6 @@ void write_tables(void) new_table_pointer - table_pointer); post_code(0x9e); - - /* Print CBMEM sections */ - cbmem_list(); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 8cfd655..5780cd1 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -212,7 +212,4 @@ void write_tables(void) write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); } - - /* Print CBMEM sections */ - cbmem_list(); } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index eeed65e..18e8b34 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -572,6 +572,9 @@ unsigned long write_coreboot_table( /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); + /* Print CBMEM sections */ + cbmem_list(); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); }

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Patch merged into coreboot/master: AGESA vendorcode: Suppress maybe-uninitialized warnings
by gerrit＠coreboot.org 20 Apr '16

20 Apr '16

the following patch was just integrated into master: commit ae2963587603c205dfada1a7cf5b5859390ac27e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 07:17:35 2016 +0300 AGESA vendorcode: Suppress maybe-uninitialized warnings Compiling libagesa with -O2 would throws error on these. Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14413 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14413 for details. -gerrit

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Patch set updated for coreboot: lib/bootmem: allow architecture specific bootmem ranges
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14434 -gerrit commit 24930de3afc3812272d22a41639a55c7ccbde697 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 17:25:59 2016 -0500 lib/bootmem: allow architecture specific bootmem ranges A architecture-specific function, named bootmem_arch_add_ranges(), is added so that each architecture can add entries into the bootmem memory map. This allows for a common write_tables() implementation to avoid code duplication. Change-Id: I834c82eae212869cad8bb02c7abcd9254d120735 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 5 +++++ src/arch/arm64/tables.c | 5 +++++ src/arch/mips/tables.c | 5 +++++ src/arch/power8/tables.c | 5 +++++ src/arch/riscv/tables.c | 5 +++++ src/arch/x86/tables.c | 5 +++++ src/include/bootmem.h | 3 +++ src/lib/bootmem.c | 2 ++ 8 files changed, 35 insertions(+) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index eb08e6e..20891e8 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index eb08e6e..20891e8 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index a3d9939..d54b8d6 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -18,12 +18,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index 02d1c16..17e678a 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index eb08e6e..20891e8 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -17,12 +17,17 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +void bootmem_arch_add_ranges(void) +{ +} + #define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE void write_tables(void) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index b36078d..4fba509 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> @@ -180,6 +181,10 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) return rom_table_end; } +void bootmem_arch_add_ranges(void) +{ +} + void write_tables(void) { unsigned long low_table_start, low_table_end; diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 0665058..10c8d51 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -26,6 +26,9 @@ */ void bootmem_init(void); +/* Architecture hook to add bootmem areas the architecture controls. */ +void bootmem_arch_add_ranges(void); + /* Add a range of a given type to the bootmem address space. */ void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type); diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 29cbec6..ea02a16 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -39,6 +39,8 @@ void bootmem_init(void) /* Add memory used by CBMEM. */ cbmem_add_bootmem(); + + bootmem_arch_add_ranges(); } void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type)

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Patch set updated for coreboot: lib/coreboot_table: add architecture hooks for adding tables
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14435 -gerrit commit 2ffa39e6de70f10fc42b9a52846671043f6c6425 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 20:37:51 2016 -0500 lib/coreboot_table: add architecture hooks for adding tables Add a architecture specific function, arch_write_tables(), that allows an architecture to add its required tables for booting. This callback helps write_tables() to be de-duplicated. Change-Id: I805c2f166b1e75942ad28b6e7e1982d64d2d5498 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 4 ++++ src/arch/arm64/tables.c | 4 ++++ src/arch/mips/tables.c | 4 ++++ src/arch/power8/tables.c | 4 ++++ src/arch/riscv/tables.c | 4 ++++ src/arch/x86/tables.c | 36 +++++++++++++++++++----------------- src/include/boot/tables.h | 12 ++++++++++++ src/lib/coreboot_table.c | 3 +++ 8 files changed, 54 insertions(+), 17 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 20891e8..92213c5 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -24,6 +24,10 @@ #include <cbmem.h> #include <lib.h> +void arch_write_tables(uintptr_t coreboot_table) +{ +} + void bootmem_arch_add_ranges(void) { } diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 20891e8..92213c5 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -24,6 +24,10 @@ #include <cbmem.h> #include <lib.h> +void arch_write_tables(uintptr_t coreboot_table) +{ +} + void bootmem_arch_add_ranges(void) { } diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index d54b8d6..32e73bc 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -25,6 +25,10 @@ #include <cbmem.h> #include <lib.h> +void arch_write_tables(uintptr_t coreboot_table) +{ +} + void bootmem_arch_add_ranges(void) { } diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index 17e678a..ff07c31 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -24,6 +24,10 @@ #include <cbmem.h> #include <lib.h> +void arch_write_tables(uintptr_t coreboot_table) +{ +} + void bootmem_arch_add_ranges(void) { } diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 20891e8..92213c5 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -24,6 +24,10 @@ #include <cbmem.h> #include <lib.h> +void arch_write_tables(uintptr_t coreboot_table) +{ +} + void bootmem_arch_add_ranges(void) { } diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 4fba509..94fe691 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -181,6 +181,25 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) return rom_table_end; } +void arch_write_tables(uintptr_t coreboot_table) +{ + unsigned long rom_table_end = 0xf0000; + + /* This table must be between 0x0f0000 and 0x100000 */ + if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) + rom_table_end = write_pirq_table(rom_table_end); + + /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ + if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) + rom_table_end = write_mptable(rom_table_end); + + if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + rom_table_end = write_acpi_table(rom_table_end); + + if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) + rom_table_end = write_smbios_table(rom_table_end); +} + void bootmem_arch_add_ranges(void) { } @@ -188,7 +207,6 @@ void bootmem_arch_add_ranges(void) void write_tables(void) { unsigned long low_table_start, low_table_end; - unsigned long rom_table_end; /* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know @@ -196,8 +214,6 @@ void write_tables(void) */ unsigned long high_table_pointer; - rom_table_end = 0xf0000; - /* Start low addr at 0x500, so we don't run into conflicts with the BDA * in case our data structures grow beyond 0x400. Only GDT * and the coreboot table use low_tables. @@ -205,20 +221,6 @@ void write_tables(void) low_table_start = 0; low_table_end = 0x500; - /* This table must be between 0x0f0000 and 0x100000 */ - if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) - rom_table_end = write_pirq_table(rom_table_end); - - /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ - if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) - rom_table_end = write_mptable(rom_table_end); - - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) - rom_table_end = write_acpi_table(rom_table_end); - - if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) - rom_table_end = write_smbios_table(rom_table_end); - post_code(0x9e); post_code(0x9d); diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index e86adfc..c2d7b48 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -3,6 +3,18 @@ #include <boot/coreboot_tables.h> +/* + * Write architecture specific tables as well as the common + * coreboot table. + */ void write_tables(void); +/* + * Allow per-architecture table writes called from write_tables(). The + * coreboot_table parameter provides a reference to where the coreboot + * table will be written. The parameter is to allow architectures to + * provide a forwarding table to real coreboot table. + */ +void arch_write_tables(uintptr_t coreboot_table); + #endif /* BOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6967217..583f609 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <ip_checksum.h> #include <boot/coreboot_tables.h> +#include <boot/tables.h> #include <boot_device.h> #include <string.h> #include <version.h> @@ -464,6 +465,8 @@ unsigned long write_coreboot_table( { struct lb_header *head; + arch_write_tables(rom_table_end); + if (low_table_start || low_table_end) { printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", low_table_end);

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Patch set updated for coreboot: arch/x86: remove low coreboot table support
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14432 -gerrit commit 3b204400cb63bca62011a5d697a9c69f22b668ed Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 16:11:22 2016 -0500 arch/x86: remove low coreboot table support In addition to being consistent with all other architectures, all chipsets support cbmem so the low coreboot table path is stale and never taken. Also it's important to note the memory written in to that low area of memory wasn't automatically reserved unless that path was taken. To that end remove low coreboot table support for x86. Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/tables.c | 7 ++----- src/lib/coreboot_table.c | 15 +-------------- 2 files changed, 3 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 309ac16..b36078d 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -183,7 +183,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) void write_tables(void) { unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; + unsigned long rom_table_end; /* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know @@ -191,7 +191,6 @@ void write_tables(void) */ unsigned long high_table_pointer; - rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA @@ -242,8 +241,6 @@ void write_tables(void) printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { - /* The coreboot table must be in 0-4K or 960K-1M */ - write_coreboot_table(low_table_start, low_table_end, - rom_table_start, rom_table_end); + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); } } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 18e8b34..091ceaf 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -447,7 +447,7 @@ static unsigned long lb_table_fini(struct lb_header *head) unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) + unsigned long rom_table_start __unused, unsigned long rom_table_end) { struct lb_header *head; @@ -468,10 +468,6 @@ unsigned long write_coreboot_table( rom_table_end); head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); - rom_table_end = ALIGN(rom_table_end, (64 * 1024)); - printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end); #if CONFIG_USE_OPTION_TABLE { @@ -500,15 +496,6 @@ unsigned long write_coreboot_table( bootmem_add_range(low_table_start, size, LB_MEM_TABLE); } - /* Record the pirq table, acpi tables, and maybe the mptable. However, - * these only need to be added when the rom_table is sitting below - * 1MiB. If it isn't that means high tables are being written. - * The code below handles high tables correctly. */ - if (rom_table_end <= (1 << 20)) { - uint64_t size = rom_table_end - rom_table_start; - bootmem_add_range(rom_table_start, size, LB_MEM_TABLE); - } - /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ bootmem_write_memory_table(lb_memory(head));

1 0

Patch set updated for coreboot: lib: add helper for constructing coreboot forwarding table
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14433 -gerrit commit b6b28a239f6e3408b6174fc6ea7ea9d5587f64c8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 17:06:09 2016 -0500 lib: add helper for constructing coreboot forwarding table The x86 architecture needs to add a forwarding table to the real coreboot table. Provide a helper function to do this for aligning the architectures on a common write_tables() implementation. Change-Id: I9a2875507e6260679874a654ddf97b879222d44e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 6 ++++++ src/lib/coreboot_table.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 8fde545..dda1e1a 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -9,6 +9,12 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); +/* + * Write forwarding table of target address at entry address returning size + * of table written. + */ +size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target); + void fill_lb_gpios(struct lb_gpios *gpios); void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 091ceaf..6967217 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -445,6 +445,19 @@ static unsigned long lb_table_fini(struct lb_header *head) return (unsigned long)rec + rec->size; } +size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) +{ + struct lb_header *head; + + printk(BIOS_DEBUG, "Writing table forward entry at 0x%p\n", + (void *)entry); + + head = lb_table_init(entry); + lb_forward(head, (struct lb_header*)target); + + return (uintptr_t)lb_table_fini(head) - entry; +} + unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start __unused, unsigned long rom_table_end)

1 0

Patch set updated for coreboot: lib: add common write_tables() implementation
by Aaron Durbin 20 Apr '16

20 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14436 -gerrit commit de106d21006a870539f4e8543d73eb3cd544da3b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 21:38:18 2016 -0500 lib: add common write_tables() implementation In order to de-duplicate common patterns implement one write_tables() function. The new write_tables() replaces all the architecture-specific ones that were largely copied. The callbacks are put in place to handle any per-architecture requirements. Change-Id: Id3d7abdce5b30f5557ccfe1dacff3c58c59f5e2b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 34 -------------------- src/arch/arm64/tables.c | 34 -------------------- src/arch/mips/tables.c | 34 -------------------- src/arch/power8/tables.c | 35 -------------------- src/arch/riscv/tables.c | 34 -------------------- src/arch/x86/tables.c | 65 ++++++++++---------------------------- src/include/boot/coreboot_tables.h | 4 --- src/lib/coreboot_table.c | 63 +++++++++++++++++++----------------- 8 files changed, 50 insertions(+), 253 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 92213c5..eef6bf2 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,35 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 92213c5..eef6bf2 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,35 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 32e73bc..50d2a55 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -16,14 +16,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -33,35 +28,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer, - table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, - MAX_COREBOOT_TABLE_SIZE); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index ff07c31..eef6bf2 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,36 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, - MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 92213c5..eef6bf2 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,35 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 94fe691..edcb717 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -27,8 +27,6 @@ #include <cbmem.h> #include <smbios.h> -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - static unsigned long write_pirq_table(unsigned long rom_table_end) { unsigned long high_table_pointer; @@ -181,8 +179,15 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) return rom_table_end; } +/* Start forwarding table at 0x500, so we don't run into conflicts with the BDA + * in case our data structures grow beyond 0x400. Only GDT + * and the coreboot table use low_tables. + */ +static uintptr_t forwarding_table = 0x500; + void arch_write_tables(uintptr_t coreboot_table) { + size_t sz; unsigned long rom_table_end = 0xf0000; /* This table must be between 0x0f0000 and 0x100000 */ @@ -198,56 +203,18 @@ void arch_write_tables(uintptr_t coreboot_table) if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) rom_table_end = write_smbios_table(rom_table_end); -} -void bootmem_arch_add_ranges(void) -{ + sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); + + forwarding_table += sz; + /* Align up to page boundary for historical consistency. */ + forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); } -void write_tables(void) +void bootmem_arch_add_ranges(void) { - unsigned long low_table_start, low_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ - unsigned long high_table_pointer; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyond 0x400. Only GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; + /* Memory from 0 through the forwarding_table is reserved. */ + const uintptr_t base = 0; - post_code(0x9e); - - post_code(0x9d); - - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - - if (high_table_pointer) { - unsigned long new_high_table_pointer; - - /* FIXME: The high_table_base parameter is not reference when tables are high, - * or high_table_pointer >1 MB. - */ - u64 fixme_high_tables_base = 0; - - /* Also put a forwarder entry into 0-4K */ - new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - fixme_high_tables_base, high_table_pointer); - - if (new_high_table_pointer > (high_table_pointer + - MAX_COREBOOT_TABLE_SIZE)) - printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_high_table_pointer - - high_table_pointer); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); - } else { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - } + bootmem_add_range(base, forwarding_table - base, LB_MEM_TABLE); } diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index dda1e1a..5647629 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -5,10 +5,6 @@ #include <stddef.h> /* function prototypes for building the coreboot table */ -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); - /* * Write forwarding table of target address at entry address returning size * of table written. diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 583f609..58c6f48 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -459,29 +459,12 @@ size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) return (uintptr_t)lb_table_fini(head) - entry; } -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start __unused, unsigned long rom_table_end) +static uintptr_t write_coreboot_table(uintptr_t rom_table_end) { struct lb_header *head; - arch_write_tables(rom_table_end); - - if (low_table_start || low_table_end) { - printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head); - printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n", - low_table_end); - low_table_end = ALIGN(low_table_end, 4096); - printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end); - } - printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n", - rom_table_end); + (long)rom_table_end); head = lb_table_init(rom_table_end); @@ -505,13 +488,6 @@ unsigned long write_coreboot_table( /* Initialize the memory map at boot time. */ bootmem_init(); - if (low_table_start || low_table_end) { - uint64_t size = low_table_end - low_table_start; - /* Record the mptable and the the lb_table. - * (This will be adjusted later) */ - bootmem_add_range(low_table_start, size, LB_MEM_TABLE); - } - /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ bootmem_write_memory_table(lb_memory(head)); @@ -575,9 +551,38 @@ unsigned long write_coreboot_table( /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); - /* Print CBMEM sections */ - cbmem_list(); - /* Remember where my valid memory ranges are */ return lb_table_fini(head); } + +void write_tables(void) +{ + uintptr_t cbtable_start; + uintptr_t cbtable_end; + size_t cbtable_size; + const size_t max_table_size = CONFIG_COREBOOT_TABLE_SIZE; + + cbtable_start = (uintptr_t)cbmem_add(CBMEM_ID_CBTABLE, max_table_size); + + if (!cbtable_start) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return; + } + + /* Add architecture specific tables. */ + arch_write_tables(cbtable_start); + + /* Write the coreboot table. */ + cbtable_end = write_coreboot_table(cbtable_start); + cbtable_size = cbtable_end - cbtable_start; + + if (cbtable_size > max_table_size) { + printk(BIOS_ERR, "%s: coreboot table didn't fit (%zx/%zx)\n", + __func__, cbtable_size, max_table_size); + } + + printk(BIOS_DEBUG, "coreboot table: %zd bytes.\n", cbtable_size); + + /* Print CBMEM sections */ + cbmem_list(); +}

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coreboot-gerrit April 2016