coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

1 participants
1270 discussions

Patch merged into coreboot/master: AGESA vendorcode: Fix logic error
by gerrit＠coreboot.org 20 Apr '16

20 Apr '16

the following patch was just integrated into master: commit 4dcbdb0ab998b18ae209b561ffab33bac96ce4b5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 18 14:36:40 2016 +0300 AGESA vendorcode: Fix logic error We have not really hit this error, due the test on AGESA_UNSUPPORTED above. Change-Id: I6e7d136a1bb46138cc347225bc4c82cfeaff385d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14394 for details. -gerrit

1 0

Patch merged into coreboot/master: AMD CIMX: Drop unused code
by gerrit＠coreboot.org 20 Apr '16

20 Apr '16

the following patch was just integrated into master: commit 318e2ac974e4f02e75fcfe9772b90de3dbe01327 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 18 14:34:18 2016 +0300 AMD CIMX: Drop unused code We never define B1_IMAGE or B2_IMAGE. These are about building CIMx as separate binary modules, while coreboot builds these into same romstage or ramstage module. Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Kerry Sheh <shekairui(a)gmail.com> See https://review.coreboot.org/14393 for details. -gerrit

1 0

Patch set updated for coreboot: buildgcc: Make package build() function more versatile
by Nico Huber 20 Apr '16

20 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13471 -gerrit commit e2370eb04e34ac2b1c71f8ad984c6060cbbbd8f0 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:09:31 2016 +0100 buildgcc: Make package build() function more versatile Refactor build() to make things more flexible: Add a parameter that tells if we build a package for the host or for a target architecture. This is just passed to the build_$package() function and can be used later to take different steps in each case (e.g. for bootstrapping a host gcc). Move .success files into the destination directory. That way we can tell that a package has been built even if the package build directory has been removed. Change-Id: I52a7245714a040d11f6e1ac8bdbff8057bb7f0a1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 50 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d4655ca..fae8bd3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -297,39 +297,57 @@ package_uses_targetarch() fi } -build() { +generic_build() +{ package=$1 + host_target=$2 + builddir=$3 + success=$4 fn_exists build_$package || return version="$(eval echo \$$package"_VERSION")" - package_uses_targetarch "$package" && \ - BUILDDIR=build-${TARGETARCH}-$package || \ - BUILDDIR=build-$package - mkdir -p ${BUILDDIR} + mkdir -p "$builddir" - is_package_enabled "$package" && \ - if [ -f ${BUILDDIR}/.success ]; then + if [ -f "$success" ]; then printf "Skipping $package as it is already built\n" else printf "Building $package $version ... " - DIR=$PWD - cd ${BUILDDIR} + DIR="$PWD" + cd "$builddir" rm -f .failed - build_${package} > build.log 2>&1 - cd $DIR/${BUILDDIR} - if [ ! -f .failed ]; then touch .success; fi - cd .. - - if [ -r "${BUILDDIR}/.failed" ]; then - printf "${RED}failed${NC}. Check ${BUILDDIR}/build.log.\n" + build_${package} $host_target > build.log 2>&1 + cd "$DIR" + if [ ! -f "$builddir/.failed" ]; then + touch "$success"; + else + printf "${RED}failed${NC}. Check $builddir/build.log.\n" exit 1 fi printf "${green}ok${NC}\n" fi } +build_for_host() +{ + generic_build $1 host build-$1 "${TARGETDIR}/.$1.success" +} + +build_for_target() +{ + generic_build $1 target build-${TARGETARCH}-$1 "${TARGETDIR}/.${TARGETARCH}-$1.success" +} + +build() +{ + if package_uses_targetarch $1; then + build_for_target $1 + else + build_for_host $1 + fi +} + cleanup() { if [ $SAVETEMPS -ne 0 ]; then

1 0

Patch set updated for coreboot: buildgcc: Always set HOSTCFLAGS
by Nico Huber 20 Apr '16

20 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13550 -gerrit commit e9e7c496b0b346f79f38035d0e7805fc80eb3e67 Author: Nico Huber <nico.h(a)gmx.de> Date: Sun Jan 31 23:05:19 2016 +0100 buildgcc: Always set HOSTCFLAGS Always set HOSTCFLAGS to the flags GMP was built with, defaulting to "-Os" if it isn't built yet. Previously, if GMP was already built or not even in the list of packages to be built, this was silently skipped and other packages were built with empty HOSTCFLAGS. Change-Id: I29b2ea75283410a6cea60dc1c92b87573aebfb34 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/crossgcc/buildgcc | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 98b57f7..d4655ca 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -405,18 +405,28 @@ GNU General Public License for more details. EOF } +have_hostcflags_from_gmp() { + grep -q __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h >/dev/null 2>&1 +} + +set_hostcflags_from_gmp() { + # Now set CFLAGS to match GMP CFLAGS but strip out -pedantic + # as GCC 4.6.x fails if it's there. + export HOSTCFLAGS=$(grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2 |\ + sed s,-pedantic,,) +} + build_GMP() { - CC="$CC" CFLAGS="-Os" ../${GMP_DIR}/configure --disable-shared --enable-fat --prefix=$TARGETDIR $OPTIONS \ + CC="$CC" CFLAGS="$HOSTCFLAGS" \ + ../${GMP_DIR}/configure --disable-shared --enable-fat \ + --prefix=$TARGETDIR $OPTIONS \ || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed normalize_dirs - # Now set CFLAGS to match GMP CFLAGS but strip out -pedantic - # as GCC 4.6.x fails if it's there. - export HOSTCFLAGS=$(grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2 |\ - sed s,-pedantic,,) + set_hostcflags_from_gmp } build_MPFR() { @@ -779,6 +789,11 @@ elif [ $UNAME = "NetBSD" ]; then fi fi # GCC +export HOSTCFLAGS="-Os" +if have_hostcflags_from_gmp; then + set_hostcflags_from_gmp +fi + if [ "$USECCACHE" = 1 ]; then CC="ccache $CC" fi

1 0

Patch set updated for coreboot: buildgcc: Add option to bootstrap a host gcc
by Nico Huber 20 Apr '16

20 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit 71ddaaab2ae21c1f84bee6f4ee6e273a9308e0ab Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 buildgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (+bootstrapping from clang, building python (-S) works too) o current Arch Linux (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fae8bd3..df5aa45 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="April 3rd, 2016" -CROSSGCC_VERSION="1.38" +CROSSGCC_DATE="April 20th, 2016" +CROSSGCC_VERSION="1.39" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -30,6 +30,7 @@ LANGUAGES=c DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -342,6 +343,9 @@ build_for_target() build() { if package_uses_targetarch $1; then + if [ $BOOTSTRAP -eq 1 -a ! -f "${TARGETDIR}/.GCC.success" ]; then + build_for_host GCC + fi build_for_target $1 else build_for_host $1 @@ -386,6 +390,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -498,8 +504,35 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } - -build_GCC() { +bootstrap_GCC() { + CC="$CC" \ + CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + CXXFLAGS="$HOSTCFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CXXFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-shared --disable-multilib \ + --disable-libssp --disable-libquadmath --disable-libcc1 \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ + --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ + $MAKE install-gcc \ + install-target-libgcc \ + maybe-install-target-libada \ + maybe-install-target-libstdc++-v3 \ + DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$TARGETDIR/bin/cc || touch .failed +} + +build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" @@ -537,6 +570,14 @@ build_GCC() { fi } +build_GCC() { + if [ "$1" = host ]; then + bootstrap_GCC + else + build_cross_GCC + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed @@ -642,11 +683,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:p:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:l:P:j:D:tSys: $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys: $*) set -- $args fi @@ -662,6 +703,7 @@ while true ; do -c|--clean) shift; clean=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;;

1 0

Patch set updated for coreboot: AGESA boards: Split dispatcher to romstage and ramstage
by Kyösti Mälkki 20 Apr '16

20 Apr '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14417 -gerrit commit aa6cad215b85b50d29d83ab4f30430ffb7817a49 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:18:02 2016 +0300 AGESA boards: Split dispatcher to romstage and ramstage The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/buildOpts.c | 17 -- src/mainboard/amd/inagua/buildOpts.c | 15 -- src/mainboard/amd/olivehill/buildOpts.c | 12 - src/mainboard/amd/parmer/buildOpts.c | 12 - src/mainboard/amd/persimmon/buildOpts.c | 15 -- src/mainboard/amd/south_station/buildOpts.c | 15 -- src/mainboard/amd/thatcher/buildOpts.c | 12 - src/mainboard/amd/torpedo/buildOpts.c | 16 -- src/mainboard/amd/union_station/buildOpts.c | 15 -- src/mainboard/asrock/e350m1/buildOpts.c | 16 -- src/mainboard/asrock/imb-a180/buildOpts.c | 12 - src/mainboard/asus/f2a85-m/buildOpts.c | 12 - src/mainboard/asus/f2a85-m_le/buildOpts.c | 12 - src/mainboard/bap/ode_e20XX/buildOpts.c | 13 -- src/mainboard/biostar/am1ml/buildOpts.c | 12 - src/mainboard/gizmosphere/gizmo/buildOpts.c | 15 -- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 13 -- src/mainboard/hp/abm/buildOpts.c | 12 - src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 12 - src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 15 -- src/mainboard/lenovo/g505s/buildOpts.c | 12 - src/mainboard/lippert/frontrunner-af/buildOpts.c | 15 -- src/mainboard/lippert/toucan-af/buildOpts.c | 15 -- src/mainboard/pcengines/apu1/buildOpts.c | 15 -- src/mainboard/supermicro/h8qgi/buildOpts.c | 12 - src/mainboard/supermicro/h8scm/buildOpts.c | 12 - src/mainboard/tyan/s8226/buildOpts.c | 12 - src/vendorcode/amd/agesa/Makefile.inc | 5 + src/vendorcode/amd/agesa/common/agesa-entry-cfg.h | 86 +++++++ src/vendorcode/amd/agesa/common/agesa-entry.c | 177 +++++++++++++++ .../amd/agesa/f10/Include/OptionDmiInstall.h | 2 - .../amd/agesa/f10/Include/OptionHtAssistInstall.h | 2 - .../amd/agesa/f12/Include/OptionDmiInstall.h | 2 - .../agesa/f12/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f12/Include/OptionPstateInstall.h | 2 +- .../amd/agesa/f12/Include/PlatformInstall.h | 246 +------------------- .../amd/agesa/f14/Include/OptionDmiInstall.h | 2 - .../amd/agesa/f14/Include/OptionHtAssistInstall.h | 2 - .../amd/agesa/f14/Include/PlatformInstall.h | 248 +------------------- .../amd/agesa/f15/Include/OptionDmiInstall.h | 2 - .../agesa/f15/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f15/Include/PlatformInstall.h | 247 +------------------- .../amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 - .../agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f15tn/Include/PlatformInstall.h | 247 +------------------- .../amd/agesa/f16kb/Include/OptionDmiInstall.h | 2 - .../agesa/f16kb/Include/OptionL3FeaturesInstall.h | 2 - .../f16kb/Include/OptionPrefetchModeInstall.h | 2 - .../amd/agesa/f16kb/Include/PlatformInstall.h | 251 +-------------------- 49 files changed, 279 insertions(+), 1622 deletions(-) diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index f69f005..0b08cc6 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -26,7 +26,6 @@ */ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE @@ -153,24 +152,9 @@ #define BLDCFG_PSTATE_HPC_MODE FALSE #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap -/* - * Agesa entry points used in this implementation. - */ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE /***************************************************************************** @@ -395,7 +379,6 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterfaceStub.h" diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 57590a2..980fb3e 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 18e403f..d558694 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 41b3e39..e5637d0 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -172,17 +172,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 23e2706..915303c 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index ad4047a..ab3efec 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 94d842a..69b8a87 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -172,17 +172,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index b42d9a1..16817c2 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -83,20 +82,6 @@ //For revision C single-link processors #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /***************************************************************************** * Define the RELEASE VERSION string @@ -230,7 +215,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index ad4047a..ab3efec 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 140ece4..83049b6 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -103,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE /* * Agesa configuration values selection. @@ -246,7 +231,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 742646c..ea47cec 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 83f96f9..755505b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -187,17 +186,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c index c6810f1..8b01f24 100644 --- a/src/mainboard/asus/f2a85-m_le/buildOpts.c +++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -187,17 +186,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 8162d42..9a02b43 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -//#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -172,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 075fe57..0e98517 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 8279802..9b62536 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -103,20 +103,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -220,7 +206,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 8162d42..9a02b43 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -//#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -172,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 96d59db..05889cb 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -176,17 +176,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -256,7 +245,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8d02f03..23457d6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -33,7 +33,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -188,17 +187,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 73673ef..48b9118 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> @@ -115,20 +114,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * AGESA entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 7b491d4..19ea01e 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -33,7 +33,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -188,17 +187,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 3211966..e054e58 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -102,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -219,7 +205,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 3211966..e054e58 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -102,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -219,7 +205,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 50cf4cf..52b8f52 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index f6e654a..cbc7bd6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -426,17 +425,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* #if CONFIG_CPU_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c index 1403999..2f96f78 100644 --- a/src/mainboard/supermicro/h8scm/buildOpts.c +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -339,17 +338,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #include "SanMarinoInstall.h" diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 4a3d808..cdefa03 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -426,17 +425,6 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* #if CONFIG_CPU_AMD_AGESA_FAMILY15 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 02d9063..4a304be 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -5,3 +5,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb + +ifeq ($(CONFIG_CPU_AMD_AGESA),y) +romstage-y += common/agesa-entry.c +ramstage-y += common/agesa-entry.c +endif diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h new file mode 100644 index 0000000..e882f2e --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -0,0 +1,86 @@ +#ifndef AGESA_ENTRY_CFG_H +#define AGESA_ENTRY_CFG_H + + +#if defined(__PRE_RAM__) + +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE + +/* Not implemented in coreboot romstage. */ +#define AGESA_ENTRY_INIT_RECOVERY FALSE + +#define AGESA_ENTRY_INIT_RESUME IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#define AGESA_ENTRY_INIT_LATE_RESTORE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + +/* Move to ramstage? */ +#define AGESA_ENTRY_INIT_ENV TRUE + +#else + +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + +#endif + +/* Not required. */ +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +/* Required for any multi-core. */ +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/* Defaults below. */ + +/* Process user desired AGESA entry points */ +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RECOVERY + #define AGESA_ENTRY_INIT_RECOVERY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE +#endif + +#endif /* AGESA_ENTRY_CFG_H */ diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c new file mode 100644 index 0000000..e722fc1 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry.c @@ -0,0 +1,177 @@ +#include <Porting.h> +#include <AMD.h> +#include <AGESA.h> + +#include "CommonReturns.h" + +#include <heapManager.h> +#include <CreateStruct.h> + +#include <Options.h> + +#include <agesa-entry-cfg.h> + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, + sizeof (AMD_RECOVERY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, 0, NULL } +}; + +CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h index 2ad7792..232d407 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h @@ -60,8 +60,6 @@ #define USER_DMI_OPTION &GetDmiInfoMain #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #ifdef OPTION_FAMILY10H diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h index c084924..a7149f0 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h @@ -79,8 +79,6 @@ &HtAssistFamilyServiceArray[0] }; - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef HT_ASSIST_AP_DISABLE_CACHE #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef HT_ASSIST_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h index 410d3cb..ead4fce 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h @@ -63,8 +63,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h index f3ef633..7f3ac07 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h @@ -82,8 +82,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h index d52adfb..7d6433d 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h @@ -129,7 +129,7 @@ #if AGESA_ENTRY_INIT_LATE == TRUE #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; +// OPTION_ACPI_FEATURE CreateAcpiTablesStub; #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub #endif #if AGESA_ENTRY_INIT_POST == TRUE diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h index 14dd179..2b99660 100644 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h @@ -52,30 +52,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature @@ -91,61 +67,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2268,6 +2189,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2484,171 +2407,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h index 31111e3..eb4bc91 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h @@ -66,8 +66,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h index d98300f..175482b 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h @@ -97,8 +97,6 @@ &HtAssistFamilyServiceArray[0] }; - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef HT_ASSIST_AP_DISABLE_CACHE #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef HT_ASSIST_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h index 8641589..9a8bd68 100644 --- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h @@ -51,31 +51,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -90,62 +65,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -2149,12 +2068,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess #endif - /***************************************************************************** * * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2329,170 +2249,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h index a6d48b3..b09a58f 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h @@ -64,8 +64,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h index 5804f1d..4a73c40 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h @@ -94,8 +94,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h index 38ec4ad..0e6f1c8 100644 --- a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h @@ -49,31 +49,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -88,61 +63,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2249,6 +2169,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2499,171 +2421,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h index fb1b54d..541cee9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h @@ -63,8 +63,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h index 5d188e2..203b9e2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h @@ -82,8 +82,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h index eca567b..af5c8b7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h @@ -48,31 +48,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -87,61 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2618,6 +2538,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2883,171 +2805,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h index ce8ef06..e0b09b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h @@ -75,8 +75,6 @@ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef CPU_DMI_AP_GET_TYPE4_TYPE7 #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #endif diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h index 8d34603..3323fea 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h @@ -57,8 +57,6 @@ #if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE) #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h index aa510aa..711b1a3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h @@ -57,8 +57,6 @@ #if OPTION_PREFETCH_MODE == TRUE #if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef CPU_PREFETCH_MODE_AP_TASK #define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask}, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 1295888..afe15b6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -48,31 +48,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -87,62 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -1727,6 +1646,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2008,174 +1929,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #if OPTION_DATA_EYE == TRUE - { AMD_GET_2D_DATA_EYE, (IMAGE_ENTRY)AmdGet2DDataEye }, - #endif - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK

1 0

Patch set updated for coreboot: AGESA vendorcode: Fix type mismatch
by Kyösti Mälkki 20 Apr '16

20 Apr '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14416 -gerrit commit 8ab64969bd9cac53b826d795a68c8ac4f708deb8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:17:50 2016 +0300 AGESA vendorcode: Fix type mismatch Fix is required to compile AGESA ramstage without raminit. Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h | 6 +++--- src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h | 10 +++++----- src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h | 10 +++++----- src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h | 10 +++++----- src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h | 10 +++++----- src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h | 10 +++++----- 6 files changed, 28 insertions(+), 28 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h index 3516fcb..23422a5 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h @@ -2563,7 +2563,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -2604,12 +2604,12 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h index cfb55cc..4fd5354 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h @@ -4033,7 +4033,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -4086,18 +4086,18 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL + 0 }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h index 97b2d41..f97caa9 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h @@ -3865,7 +3865,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -3918,18 +3918,18 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL + 0 }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h index 24c1ae8..a4d8346 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h @@ -3629,7 +3629,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -3674,18 +3674,18 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL + 0 }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h index 873ed8b..e1c47ee 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h @@ -4687,7 +4687,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -4744,18 +4744,18 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL + 0 }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 1aaa027..647c370 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -1556,7 +1556,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -1581,18 +1581,18 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL + 0 }; #endif /*---------------------------------------------------------------------------------------------------

1 0

Patch set updated for coreboot: AGESA: Rewrite agesawrapper [NOTFORMERGE]
by Kyösti Mälkki 20 Apr '16

20 Apr '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14418 -gerrit commit c02923724f35758ca219dd8b39d93fa455a99f5e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:51:24 2016 +0300 AGESA: Rewrite agesawrapper [NOTFORMERGE] Change-Id: Ic111291a2c0f1f171d2330c9ddaf6061a648bc86 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/agesawrapper.c | 254 ++++++++++++------------------- 1 file changed, 94 insertions(+), 160 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index a72e239..19b7e33 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -25,60 +25,74 @@ static const struct OEM_HOOK *OemHook = &OemCustomize; + +static void prepare_AmdParams(AMD_INTERFACE_PARAMS *p, int f) +{ + memset(p, 0, sizeof(AMD_INTERFACE_PARAMS)); + p->StdHeader.CalloutPtr = GetBiosCallout; + p->AgesaFunctionName = f; + + p->AllocationMethod = 0; /* Only byHost makes difference. */ +} + +static void * empty_AmdParams(AMD_INTERFACE_PARAMS *p, int f) +{ + prepare_AmdParams(p, f); + + AmdCreateStruct(p); + return (void *) p->NewStructPtr; +} + +static void free_AmdParams(AMD_INTERFACE_PARAMS *p) +{ + AmdReleaseStruct(p); +} + #if defined(__PRE_RAM__) +static void * local_AmdParams(AMD_INTERFACE_PARAMS *p, int f, void *buf, size_t len) +{ + prepare_AmdParams(p, f); + + memset(buf, 0, len); + p->NewStructPtr = buf; + p->NewStructSize = len; + p->AllocationMethod = ByHost; + + AmdCreateStruct(p); + return (void *) p->NewStructPtr; +} + AGESA_STATUS agesawrapper_amdinitreset(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; + AMD_RESET_PARAMS tmp; + + AMD_RESET_PARAMS *AmdResetParams = local_AmdParams(&aip, + AMD_INIT_RESET, &tmp, sizeof(tmp)); + + AmdResetParams->HtConfig.Depth = 0; + + status = AmdInitReset(AmdResetParams); + AGESA_EVENTLOG(status, &aip.StdHeader); return status; } AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; /* OEM Should Customize the defaults through this hook. */ - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_EARLY_PARAMS *AmdEarlyParams = empty_AmdParams(&aip, AMD_INIT_EARLY); if (OemHook->InitEarly) - OemHook->InitEarly(AmdEarlyParamsPtr); + OemHook->InitEarly(AmdEarlyParams); - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); + status = AmdInitEarly(AmdEarlyParams); + AGESA_EVENTLOG(status, &aip.StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); return status; } @@ -86,29 +100,17 @@ AGESA_STATUS agesawrapper_amdinitearly(void) AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; /* OEM Should Customize the defaults through this hook. */ - PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_POST_PARAMS *PostParams = empty_AmdParams(&aip, AMD_INIT_POST); if (OemHook->InitPost) OemHook->InitPost(PostParams); status = AmdInitPost(PostParams); AGESA_EVENTLOG(status, &PostParams->StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); /* Initialize heap space */ EmptyHeap(); @@ -119,29 +121,18 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_RESUME_PARAMS *AmdResumeParams = empty_AmdParams(&aip, AMD_INIT_RESUME); - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemInitResume(AmdResumeParamsPtr); + AmdResumeParams->S3DataBlock.NvStorageSize = 0; + AmdResumeParams->S3DataBlock.VolatileStorageSize = 0; + OemInitResume(AmdResumeParams); - status = AmdInitResume(AmdResumeParamsPtr); + status = AmdInitResume(AmdResumeParams); + AGESA_EVENTLOG(status, &aip.StdHeader); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); return status; } @@ -149,55 +140,34 @@ AGESA_STATUS agesawrapper_amdinitresume(void) AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_INTERFACE_PARAMS aip; - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_ENV_PARAMS *EnvParam = empty_AmdParams(&aip, AMD_INIT_ENV); status = AmdInitEnv(EnvParam); AGESA_EVENTLOG(status, &EnvParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); return status; } AGESA_STATUS agesawrapper_amds3laterestore(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + AMD_INTERFACE_PARAMS aip; + AMD_S3LATE_PARAMS tmp; - AmdCreateStruct(&AmdInterfaceParams); + AMD_S3LATE_PARAMS *AmdS3LateParams = local_AmdParams(&aip, + AMD_S3LATE_RESTORE, &tmp, sizeof(tmp)); -#if 0 - /* TODO: What to do with NvStorage here? */ - AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; +#if 0 /* TODO: What to do with NvStorage here? */ + AmdS3LateParams->S3DataBlock.NvStorageSize = 0; #endif - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemS3LateRestore(AmdS3LateParamsPtr); + AmdS3LateParams->S3DataBlock.VolatileStorageSize = 0; + OemS3LateRestore(AmdS3LateParams); - status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); + status = AmdS3LateRestore(AmdS3LateParams); + AGESA_EVENTLOG(status, &aip.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; @@ -208,28 +178,20 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_MID_PARAMS *MidParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; /* OEM Should Customize the defaults through this hook. */ - MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_MID_PARAMS *MidParam = empty_AmdParams(&aip, AMD_INIT_MID); if (OemHook->InitMid) OemHook->InitMid(MidParam); status = AmdInitMid(MidParam); AGESA_EVENTLOG(status, &MidParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); +#if 0 /* TODO: Why not? */ + ASSERT(status == AGESA_SUCCESS); +#endif + + free_AmdParams(&aip); return status; } @@ -237,30 +199,19 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); + AMD_INTERFACE_PARAMS aip; - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); + AMD_S3SAVE_PARAMS *AmdS3SaveParams = empty_AmdParams(&aip, AMD_S3_SAVE); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + AmdS3SaveParams->StdHeader = aip.StdHeader; - status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); + status = AmdS3Save(AmdS3SaveParams); + AGESA_EVENTLOG(status, &aip.StdHeader); ASSERT(status == AGESA_SUCCESS); - OemS3Save(AmdS3SaveParamsPtr); + OemS3Save(AmdS3SaveParams); - AmdReleaseStruct(&AmdInterfaceParams); + free_AmdParams(&aip); return status; } @@ -271,29 +222,15 @@ static AMD_LATE_PARAMS *AmdLateParams = NULL; AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_INTERFACE_PARAMS aip; - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); + AmdLateParams = empty_AmdParams(&aip, AMD_INIT_LATE); - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; -#endif - - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); - /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ + /* No free_AmdParams(&aip), we need AmdLateParams later. */ return status; } @@ -336,11 +273,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf AP_EXE_PARAMS ApExeParams; memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr;

1 0

Patch set updated for coreboot: buildgcc: Add option to bootstrap a host gcc
by Nico Huber 20 Apr '16

20 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit 680a818d3316d591d0c0a6a2f825ea0b3983b9b6 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 buildgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (+bootstrapping from clang, building python (-S) works too) o current Arch Linux (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index eddafe5..eee3ac3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="April 3rd, 2016" -CROSSGCC_VERSION="1.38" +CROSSGCC_DATE="April 20th, 2016" +CROSSGCC_VERSION="1.39" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -30,6 +30,7 @@ LANGUAGES=c DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -342,6 +343,9 @@ build_for_target() build() { if package_uses_targetarch $1; then + if [ $BOOTSTRAP -eq 1 -a ! -f "${TARGETDIR}/.GCC.success" ]; then + build_for_host GCC + fi build_for_target $1 else build_for_host $1 @@ -381,6 +385,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -493,8 +499,35 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } - -build_GCC() { +bootstrap_GCC() { + CC="$CC" \ + CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + CXXFLAGS="$HOSTCFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CXXFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-shared --disable-multilib \ + --disable-libssp --disable-libquadmath --disable-libcc1 \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ + --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ + $MAKE install-gcc \ + install-target-libgcc \ + maybe-install-target-libada \ + maybe-install-target-libstdc++-v3 \ + DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$TARGETDIR/bin/cc || touch .failed +} + +build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" @@ -532,6 +565,14 @@ build_GCC() { fi } +build_GCC() { + if [ "$1" = host ]; then + bootstrap_GCC + else + build_cross_GCC + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed @@ -637,11 +678,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:p:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:l:P:j:D:tSys: $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys: $*) set -- $args fi @@ -657,6 +698,7 @@ while true ; do -c|--clean) shift; clean=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;;

1 0

New patch to review for coreboot: lib: add common write_tables() implementation
by Aaron Durbin 19 Apr '16

19 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14436 -gerrit commit f5d2b31b65206d6c148e26cc01c59dcdce3e1d2e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 19 21:38:18 2016 -0500 lib: add common write_tables() implementation In order to de-duplicate common patterns implement one write_tables() function. The new write_tables() replaces all the architecture-specific ones that were largely copied. The callbacks are put in place to handle any per-architecture requirements. Change-Id: Id3d7abdce5b30f5557ccfe1dacff3c58c59f5e2b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/tables.c | 34 -------------------- src/arch/arm64/tables.c | 34 -------------------- src/arch/mips/tables.c | 34 -------------------- src/arch/power8/tables.c | 35 -------------------- src/arch/riscv/tables.c | 34 -------------------- src/arch/x86/tables.c | 65 ++++++++++---------------------------- src/include/boot/coreboot_tables.h | 4 --- src/lib/coreboot_table.c | 63 +++++++++++++++++++----------------- 8 files changed, 50 insertions(+), 253 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 92213c5..eef6bf2 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,35 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 92213c5..eef6bf2 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,35 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 32e73bc..50d2a55 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -16,14 +16,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -33,35 +28,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer, - table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, - MAX_COREBOOT_TABLE_SIZE); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c index ff07c31..eef6bf2 100644 --- a/src/arch/power8/tables.c +++ b/src/arch/power8/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,36 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, - MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 92213c5..eef6bf2 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -15,14 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <cpu/cpu.h> #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <string.h> -#include <cbmem.h> -#include <lib.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -32,35 +27,6 @@ void bootmem_arch_add_ranges(void) { } -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - -void write_tables(void) -{ - unsigned long table_pointer, new_table_pointer; - - post_code(0x9d); - - table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, - MAX_COREBOOT_TABLE_SIZE); - if (!table_pointer) { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return; - } - - new_table_pointer = write_coreboot_table(0UL, 0UL, - table_pointer, table_pointer); - - if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", - new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); - } - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); - - post_code(0x9e); -} - void lb_arch_add_records(struct lb_header *header) { } diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 94fe691..edcb717 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -27,8 +27,6 @@ #include <cbmem.h> #include <smbios.h> -#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE - static unsigned long write_pirq_table(unsigned long rom_table_end) { unsigned long high_table_pointer; @@ -181,8 +179,15 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) return rom_table_end; } +/* Start forwarding table at 0x500, so we don't run into conflicts with the BDA + * in case our data structures grow beyond 0x400. Only GDT + * and the coreboot table use low_tables. + */ +static uintptr_t forwarding_table = 0x500; + void arch_write_tables(uintptr_t coreboot_table) { + size_t sz; unsigned long rom_table_end = 0xf0000; /* This table must be between 0x0f0000 and 0x100000 */ @@ -198,56 +203,18 @@ void arch_write_tables(uintptr_t coreboot_table) if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) rom_table_end = write_smbios_table(rom_table_end); -} -void bootmem_arch_add_ranges(void) -{ + sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); + + forwarding_table += sz; + /* Align up to page boundary for historical consistency. */ + forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); } -void write_tables(void) +void bootmem_arch_add_ranges(void) { - unsigned long low_table_start, low_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ - unsigned long high_table_pointer; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyond 0x400. Only GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; + /* Memory from 0 through the forwarding_table is reserved. */ + const uintptr_t base = 0; - post_code(0x9e); - - post_code(0x9d); - - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - - if (high_table_pointer) { - unsigned long new_high_table_pointer; - - /* FIXME: The high_table_base parameter is not reference when tables are high, - * or high_table_pointer >1 MB. - */ - u64 fixme_high_tables_base = 0; - - /* Also put a forwarder entry into 0-4K */ - new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - fixme_high_tables_base, high_table_pointer); - - if (new_high_table_pointer > (high_table_pointer + - MAX_COREBOOT_TABLE_SIZE)) - printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_high_table_pointer - - high_table_pointer); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); - } else { - printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - } + bootmem_add_range(base, forwarding_table - base, LB_MEM_TABLE); } diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index dda1e1a..5647629 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -5,10 +5,6 @@ #include <stddef.h> /* function prototypes for building the coreboot table */ -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); - /* * Write forwarding table of target address at entry address returning size * of table written. diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 583f609..58c6f48 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -459,29 +459,12 @@ size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) return (uintptr_t)lb_table_fini(head) - entry; } -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start __unused, unsigned long rom_table_end) +static uintptr_t write_coreboot_table(uintptr_t rom_table_end) { struct lb_header *head; - arch_write_tables(rom_table_end); - - if (low_table_start || low_table_end) { - printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head); - printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n", - low_table_end); - low_table_end = ALIGN(low_table_end, 4096); - printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end); - } - printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n", - rom_table_end); + (long)rom_table_end); head = lb_table_init(rom_table_end); @@ -505,13 +488,6 @@ unsigned long write_coreboot_table( /* Initialize the memory map at boot time. */ bootmem_init(); - if (low_table_start || low_table_end) { - uint64_t size = low_table_end - low_table_start; - /* Record the mptable and the the lb_table. - * (This will be adjusted later) */ - bootmem_add_range(low_table_start, size, LB_MEM_TABLE); - } - /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ bootmem_write_memory_table(lb_memory(head)); @@ -575,9 +551,38 @@ unsigned long write_coreboot_table( /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); - /* Print CBMEM sections */ - cbmem_list(); - /* Remember where my valid memory ranges are */ return lb_table_fini(head); } + +void write_tables(void) +{ + uintptr_t cbtable_start; + uintptr_t cbtable_end; + size_t cbtable_size; + const size_t max_table_size = CONFIG_COREBOOT_TABLE_SIZE; + + cbtable_start = (uintptr_t)cbmem_add(CBMEM_ID_CBTABLE, max_table_size); + + if (!cbtable_start) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return; + } + + /* Add architecture specific tables. */ + arch_write_tables(cbtable_start); + + /* Write the coreboot table. */ + cbtable_end = write_coreboot_table(cbtable_start); + cbtable_size = cbtable_end - cbtable_start; + + if (cbtable_size > max_table_size) { + printk(BIOS_ERR, "%s: coreboot table didn't fit (%zx/%zx)\n", + __func__, cbtable_size, max_table_size); + } + + printk(BIOS_DEBUG, "coreboot table: %zd bytes.\n", cbtable_size); + + /* Print CBMEM sections */ + cbmem_list(); +}

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2016