coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: sb/amd/sb700: Add sb7xx_51xx_decode_last_reset()
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14263 -gerrit commit 300ae6c76689b49f809c59cd5ff754bbc3e8a3ba Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:18:52 2016 -0500 sb/amd/sb700: Add sb7xx_51xx_decode_last_reset() The SB700 family has the ability to report the last reset reason. This is useful in the context of handling MCEs and recovering from fatal errors / sync floods. Add a function to retrieve the last reset flags. Change-Id: I754cb25e47bd9c1e4a29ecb6cb18017d1b7c3dc4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 13 ++++++++++++- src/southbridge/amd/sb700/sb700.h | 1 + 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 8042849..ffdd34b 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -758,6 +758,17 @@ static void sb700_por_init(void) sb700_pmio_por_init(); } +uint16_t sb7xx_51xx_decode_last_reset(void) { + uint16_t reset_status = 0; + reset_status |= pmio_read(0x44); + reset_status |= (pmio_read(0x45) << 8); + printk(BIOS_INFO, "sb700 reset flags: %04x\n", reset_status); + if (reset_status & (0x1 << 10)) + printk(BIOS_WARNING, "WARNING: Last reset was caused by fatal error / sync flood!\n"); + + return reset_status; +} + /* * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. */ diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index f895811..f23956c 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -66,6 +66,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); void sb7xx_51xx_disable_wideio(u8 wio_index); void sb7xx_51xx_early_setup(void); void sb7xx_51xx_before_pci_init(void); +uint16_t sb7xx_51xx_decode_last_reset(void); #else #include <device/pci.h> /* allow override in mainboard.c */

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Patch set updated for coreboot: sb/amd/sb700: Enable reset on sync flood
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14260 -gerrit commit be725b7f7d43b8b897f58024a049ed0943dcfac1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Apr 5 23:10:48 2016 -0500 sb/amd/sb700: Enable reset on sync flood The logic to enable reset on sync flood per RPR guidelines somehow ended up guarded on the SATA AHCI setup. Unconditionally enable reset on sync flood per the RPR. Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 76855fb..8042849 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -543,13 +543,13 @@ static void sb700_devices_por_init(void) /* set Device ID consistent with IDE emulation mode configuration */ pci_write_config32(dev, 0x0, 0x43901002); - - /* rpr v2.13 4.17 Reset CPU on Sync Flood */ - abcfg_reg(0x10050, 1 << 2, 1 << 2); } #endif } + /* rpr v2.13 4.17 Reset CPU on Sync Flood */ + abcfg_reg(0x10050, 1 << 2, 1 << 2); + /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);

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Patch merged into coreboot/master: crossgcc: Fix compilation on Clang systems
by gerrit＠coreboot.org 06 Apr '16

06 Apr '16

the following patch was just integrated into master: commit 45f77b81a49de76cb723ca4c5af7d89a97e67016 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Apr 3 20:52:01 2016 -0700 crossgcc: Fix compilation on Clang systems Most cross compilers fail to compile on systems with Clang being the default compiler (OS X and some BSDs). Clang dislikes some of GCC's autogenerated code. We also missed switching CFLAGS to CXXFLAGS when GCC switched to C++ compilation per default. Change-Id: I87caa1a15982c431048aa79748ea7ef655a9a3a1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14232 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14232 for details. -gerrit

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: support calling dram_freq multiple times
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14174 -gerrit commit 7f0813a23d32dd61d9bac37d7a95381b5f41c908 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 17:20:02 2016 +0100 nb/intel/sandybridge/raminit: support calling dram_freq multiple times The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 19ca1b0..c32c855 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -810,6 +810,17 @@ static void dram_freq(ramctr_timing * ctrl) /* Frequency mulitplier. */ u32 FRQ = get_FRQ(ctrl->tCK); + /* The PLL will never lock if the required frequency is + * already set. Exit early to prevent a system hang. + */ + reg1 = MCHBAR32(0x5e04); + val2 = (u8) reg1; + if (val2 == FRQ) { + printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + (1000 << 8) / ctrl->tCK); + return; + } + /* Step 2 - Select frequency in the MCU */ reg1 = FRQ; reg1 |= 0x80000000; // set running bit

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: add additional fallbacks
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14173 -gerrit commit eba0461239461d86ec8f7a57ff14398b9e7112d3 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:16:29 2016 +0100 nb/intel/sandybridge/raminit: add additional fallbacks Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 44 +++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 042898d..19ca1b0 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -201,6 +201,7 @@ typedef struct ramctr_timing_st { #define MAX_TIMA 127 #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) +#define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); @@ -241,6 +242,18 @@ static void toggle_io_reset(void) { } /* + * Disable a channel in ramctr_timing. + */ +static void disable_channel(ramctr_timing *ctrl, int channel) { + ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); +} + +/* * Fill cbmem with information for SMBIOS type 17. */ static void fill_smbios17(ramctr_timing *ctrl) @@ -4245,6 +4258,37 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); } + + if (err && (ctrl.tCK < TCK_400MHZ)) { + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } + + if (err && (ctrl.tCK < TCK_400MHZ)) { + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } + + if (err) { + /* fallback: disable failing channel */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Disable failing channel.\n"); + + /* Reset DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + + /* disable failing channel */ + disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } + if (err) die("raminit failed");

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14172 -gerrit commit b300e83db2627327fe78709911217b10d1843c9c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Use new fallback in case of broken mrc cache. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Test result: The system boots a lot faster using the MRC cache. On swapping DIMMs the CRC16 doesn't match and normal ram training is started. Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 102 +++++++++++++++++++++------- 1 file changed, 77 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 48ec5b5..042898d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -324,6 +325,24 @@ static void report_memory_config(void) } } +/* + * Return CRC16 match for all SPDs. + */ +static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +{ + int channel, slot, spd_slot; + int match = 1; + + FOR_ALL_CHANNELS { + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + match &= ctrl->spd_crc[channel][slot] == + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + } + } + return match; +} + void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -376,6 +395,10 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in CRC16 for MRC cache */ + ctrl->spd_crc[channel][slot] = + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -4014,12 +4037,14 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int me_uma_size) { int err; - if (!s3resume) { + printk(BIOS_DEBUG, "Starting RAM training (%d).\n", fast_boot); + + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4029,7 +4054,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Set MCU frequency */ dram_freq(ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(ctrl); } @@ -4072,7 +4097,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4123,11 +4148,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); - if (!s3resume) { - err = channel_test(ctrl); - if (err) - return err; - } + err = channel_test(ctrl); + if (err) + return err; return 0; } @@ -4138,6 +4161,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int fast_boot; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; int err; MCHBAR32(0x5f00) |= 1; @@ -4171,28 +4197,54 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + ctrl_cached = NULL; } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + if (!fast_boot && s3resume) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } + } else + fast_boot = 0; + + if (fast_boot) { + printk(BIOS_DEBUG, "Trying stored timings.\n"); + memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (err) { + /* no need to erase bad mrc cache here, it gets overritten on + * successful boot. */ + printk(BIOS_ERR, "Stored timings are invalid !\n"); + fast_boot = 0; + } + } + if (!fast_boot) { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); - } - err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } if (err) die("raminit failed"); @@ -4208,7 +4260,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4218,7 +4270,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */

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New patch to review for coreboot: MAINTAINERS: add myself
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14262 -gerrit commit 6d2959c05f552425bc795d87c5e7ef87c8f918fe Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Apr 6 16:17:40 2016 +0200 MAINTAINERS: add myself Add myself to MAINTAINERS file. Change-Id: I959ef193b69095b05ae9e42bd10d3b21001e0bc8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 28628ff..7d5b731 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,6 +141,7 @@ F: src/ec/lenovo/ LENOVO MAINBOARDS M: Alexander Couzens <lynxis(a)fe80.eu> +M: Patrick Rudolph <siro(a)das-labor.org> S: Maintained F: src/mainboard/lenovo/ @@ -307,6 +308,8 @@ F: src/include/pc80/ F: src/include/cpu/x86/ INTEL SUPPORT +M: Patrick Rudolph <siro(a)das-labor.org> +S: Maintained F: src/vendorcode/intel/ F: src/cpu/intel/ F: src/northbridge/intel/

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: support calling dram_freq multiple times
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14174 -gerrit commit e6858d07550d7d13e6829c23f0cc2377b9e24cb8 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 17:20:02 2016 +0100 nb/intel/sandybridge/raminit: support calling dram_freq multiple times The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b71f2ad..c812a24 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -810,6 +810,17 @@ static void dram_freq(ramctr_timing * ctrl) /* Frequency mulitplier. */ u32 FRQ = get_FRQ(ctrl->tCK); + /* The PLL will never lock if the required frequency is + * already set. Exit early to prevent a system hang. + */ + reg1 = MCHBAR32(0x5e04); + val2 = (u8) reg1; + if (val2 == FRQ) { + printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + (1000 << 8) / ctrl->tCK); + return; + } + /* Step 2 - Select frequency in the MCU */ reg1 = FRQ; reg1 |= 0x80000000; // set running bit

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: add additional fallbacks
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14173 -gerrit commit bf8ba972a4d5f8bf8911d72be5e761f839f6f8c2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 26 12:16:29 2016 +0100 nb/intel/sandybridge/raminit: add additional fallbacks Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 44 +++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index ff9aed4..b71f2ad 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -201,6 +201,7 @@ typedef struct ramctr_timing_st { #define MAX_TIMA 127 #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) +#define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); @@ -241,6 +242,18 @@ static void toggle_io_reset(void) { } /* + * Disable a channel in ramctr_timing. + */ +static void disable_channel(ramctr_timing *ctrl, int channel) { + ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); +} + +/* * Fill cbmem with information for SMBIOS type 17. */ static void fill_smbios17(ramctr_timing *ctrl) @@ -4240,6 +4253,37 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); } + + if (err && (ctrl.tCK < TCK_400MHZ)) { + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } + + if (err && (ctrl.tCK < TCK_400MHZ)) { + /* fallback: lower clock frequency */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Decreasing clock frequency.\n"); + ctrl.tCK++; + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } + + if (err) { + /* fallback: disable failing channel */ + printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); + printram("Disable failing channel.\n"); + + /* Reset DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + + /* disable failing channel */ + disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } + if (err) die("raminit failed");

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 06 Apr '16

06 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14172 -gerrit commit a26a78d184ae28c7e92ee63d057abc3ebe231c3c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Use new fallback in case of broken mrc cache. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Test result: The system boots a lot faster using the MRC cache. On swapping DIMMs the CRC16 doesn't match and normal ram training is started. Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 97 +++++++++++++++++++++-------- 1 file changed, 72 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 48ec5b5..ff9aed4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -324,6 +325,24 @@ static void report_memory_config(void) } } +/* + * Return CRC16 match for all SPDs. + */ +static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +{ + int channel, slot, spd_slot; + int match = 1; + + FOR_ALL_CHANNELS { + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + match &= ctrl->spd_crc[channel][slot] == + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + } + } + return match; +} + void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -376,6 +395,10 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in CRC16 for MRC cache */ + ctrl->spd_crc[channel][slot] = + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -4014,12 +4037,14 @@ static void restore_timings(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int me_uma_size) { int err; - if (!s3resume) { + printk(BIOS_DEBUG, "Starting RAM training.\n"); + + if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); @@ -4029,7 +4054,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, /* Set MCU frequency */ dram_freq(ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(ctrl); } @@ -4072,7 +4097,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4123,11 +4148,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume, write_controller_mr(ctrl); - if (!s3resume) { - err = channel_test(ctrl); - if (err) - return err; - } + err = channel_test(ctrl); + if (err) + return err; return 0; } @@ -4138,6 +4161,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; + int fast_boot; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; int err; MCHBAR32(0x5f00) |= 1; @@ -4171,28 +4197,49 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof(ctrl)); + ctrl_cached = NULL; } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + } else + fast_boot = 0; + + if (fast_boot) { + printk(BIOS_DEBUG, "Trying stored timings.\n"); + memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); + + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + if (err) { + /* no need to erase bad mrc cache here, it gets overritten on + * successful boot. */ + printk(BIOS_ERR, "Stored timings are invalid !\n"); + fast_boot = 0; + } + } + if (!fast_boot) { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); - } - err = try_init_dram_ddr3(&ctrl, s3resume, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + } if (err) die("raminit failed"); @@ -4208,7 +4255,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4218,7 +4265,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */

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coreboot-gerrit April 2016