coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Fill _PRT entry in DSDT
by Lijian Zhao 06 Apr '16

06 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14243 -gerrit commit 0cbbaa555b75ecc380c1da386ce45fc4256be971 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 15:34:45 2015 -0800 soc/intel/apollolake: Fill _PRT entry in DSDT ACPI aware OS will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC gets fixed interrupt line. Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pci_irqs.asl | 59 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/soc_int.asl | 52 +++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 2 + 3 files changed, 113 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..024282c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "soc_int.asl" + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, NPK_INT}, + Package(){0x0000FFFF, 1, 0, PUNIT_INT}, + Package(){0x0002FFFF, 0, 0, GEN_INT}, + Package(){0x0003FFFF, 0, 0, IUNIT_INT}, + Package(){0x000DFFFF, 1, 0, PMC_INT}, + Package(){0x000EFFFF, 0, 0, AUDIO_INT}, + Package(){0x000FFFFF, 0, 0, CSE_INT}, + Package(){0x0011FFFF, 0, 0, ISH_INT}, + Package(){0x0012FFFF, 0, 0, SATA_INT}, + Package(){0x0013FFFF, 0, 0, PIRQA_INT}, + Package(){0x0013FFFF, 1, 0, PIRQB_INT}, + Package(){0x0013FFFF, 2, 0, PIRQC_INT}, + Package(){0x0013FFFF, 3, 0, PIRQD_INT}, + Package(){0x0014FFFF, 0, 0, PIRQB_INT}, + Package(){0x0014FFFF, 1, 0, PIRQC_INT}, + Package(){0x0014FFFF, 2, 0, PIRQD_INT}, + Package(){0x0014FFFF, 3, 0, PIRQA_INT}, + Package(){0x0015FFFF, 0, 0, XHCI_INT}, + Package(){0x0015FFFF, 1, 0, XDCI_INT}, + Package(){0x0016FFFF, 0, 0, I2C0_INT}, + Package(){0x0016FFFF, 1, 0, I2C1_INT}, + Package(){0x0016FFFF, 2, 0, I2C2_INT}, + Package(){0x0016FFFF, 3, 0, I2C3_INT}, + Package(){0x0017FFFF, 0, 0, I2C4_INT}, + Package(){0x0017FFFF, 1, 0, I2C5_INT}, + Package(){0x0017FFFF, 2, 0, I2C6_INT}, + Package(){0x0017FFFF, 3, 0, I2C7_INT}, + Package(){0x0018FFFF, 0, 0, UART0_INT}, + Package(){0x0018FFFF, 1, 0, UART1_INT}, + Package(){0x0018FFFF, 2, 0, UART2_INT}, + Package(){0x0018FFFF, 3, 0, UART3_INT}, + Package(){0x0019FFFF, 0, 0, SPI0_INT}, + Package(){0x0019FFFF, 1, 0, SPI1_INT}, + Package(){0x0019FFFF, 2, 0, SPI2_INT}, + Package(){0x001BFFFF, 0, 0, SDCARD_INT}, + Package(){0x001CFFFF, 0, 0, EMMC_INT}, + Package(){0x001EFFFF, 0, 0, SDIO_INT}, + Package(){0x001FFFFF, 1, 0, SMBUS_INT}, + } + ) +} diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl new file mode 100644 index 0000000..3464d5c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_INT_DEFINE_ASL_ +#define _SOC_INT_DEFINE_ASL_ + +#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/ +#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/ +#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/ +#define UAR21_INT 6 /* Need to be shared by PMC and SCC only*/ +#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ +#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define NPK_INT 16 +#define PIRQA_INT 16 +#define PIRQB_INT 17 +#define PIRQC_INT 18 +#define SATA_INT 19 +#define GEN_INT 19 +#define PIRQD_INT 19 +#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/ +#define SMBUS_INT 20 /* PIRQE */ +#define CSE_INT 20 /* PIRQE */ +#define IUNIT_INT 21 /* PIRQF */ +#define PUNIT_INT 24 +#define AUDIO_INT 25 +#define ISH_INT 26 +#define I2C0_INT 27 +#define I2C1_INT 28 +#define I2C2_INT 29 +#define I2C3_INT 30 +#define I2C4_INT 31 +#define I2C5_INT 32 +#define I2C6_INT 33 +#define I2C7_INT 34 +#define SPI0_INT 35 +#define SPI1_INT 36 +#define SPI2_INT 37 +#define UFS_INT 38 +#define EMMC_INT 39 +#define SDIO_INT 42 + + +#endif /* _SOC_INT_DEFINE_ASL_ */ \ No newline at end of file diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 7e9329f..9b78ea4 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -13,3 +13,5 @@ /* LPSS device */ #include "lpss.asl" +/* PCI IRQ */ +#include "pci_irqs.asl"

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New patch to review for coreboot: lib/prog_ops: Add explicit no-op to change layout
by Paul Menzel 06 Apr '16

06 Apr '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14268 -gerrit commit cb84fed2e35b1522fe3e4431f5900c06181ed25e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 6 07:33:43 2016 +0200 lib/prog_ops: Add explicit no-op to change layout Change the code layout to debug the boot time increase on the ASRock E350M1 due to commit 096f4579 (lib/prog_loading: introduce > prog_segment_loaded()). Change-Id: Ie7b6b876fec264bc1368ec945cf614212822e71a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/lib/prog_ops.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index bc889fc..4f12d2c 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -27,6 +27,7 @@ void __attribute__ ((weak)) platform_segment_loaded(uintptr_t start, size_t size, int flags) { /* do nothing */ + asm volatile ("nop\n"); } void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size,

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Patch set updated for coreboot: edid: Make framebuffer row alignment configurable
by Julius Werner 06 Apr '16

06 Apr '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14267 -gerrit commit 6e179384d74bb0f1d0eacc6954e30577bfb913f8 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Apr 6 12:50:40 2016 -0700 edid: Make framebuffer row alignment configurable Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/include/edid.h | 3 ++- src/lib/edid.c | 17 ++++++++++++----- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra132/dc.c | 2 +- src/soc/nvidia/tegra210/dc.c | 2 +- src/soc/rockchip/rk3288/display.c | 2 +- 8 files changed, 20 insertions(+), 12 deletions(-) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f32fee0..74a7247 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -113,7 +113,7 @@ static void bochs_init(struct device *dev) edid.mode.va = height; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32); + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 84c2958..dc20f54 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -332,7 +332,7 @@ static void cirrus_init(struct device *dev) edid.mode.va = height; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32); + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/include/edid.h b/src/include/edid.h index f46c761..73412a3 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -93,7 +93,8 @@ struct edid { /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); -void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp); +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, + int row_byte_alignment); void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/lib/edid.c b/src/lib/edid.c index 52898fb..8bcb956 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -481,9 +481,14 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, out->mode.vborder = x[16]; /* We assume rgb888 (32 bits per pixel) framebuffers by default. - * Chipsets that want something else will need to override this - * with another call to edid_set_framebuffer_bits_per_pixel(). */ - edid_set_framebuffer_bits_per_pixel(out, 32); + * Chipsets that want something else will need to override this with + * another call to edid_set_framebuffer_bits_per_pixel(). As a cheap + * heuristic, assume that X86 systems require a 64-byte row alignment + * (since that seems to be true for most Intel chipsets). */ + if (IS_ENABLED(CONFIG_ARCH_X86)) + edid_set_framebuffer_bits_per_pixel(out, 32, 64); + else + edid_set_framebuffer_bits_per_pixel(out, 32, 0); switch ((x[17] & 0x18) >> 3) { case 0x00: @@ -1524,14 +1529,16 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) */ /* Set the framebuffer bits-per-pixel, recalculating all dependent values. */ -void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp) +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, + int row_byte_alignment) { /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); + row_byte_alignment = max(row_byte_alignment, 1); edid->framebuffer_bits_per_pixel = fb_bpp; edid->bytes_per_line = ALIGN_UP(edid->mode.ha * - div_round_up(fb_bpp, 8), 64); + div_round_up(fb_bpp, 8), row_byte_alignment); edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); edid->y_resolution = edid->mode.va; } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 74202ba..bb96831 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -334,6 +334,6 @@ void display_startup(device_t dev) edid.mode.va = config->yres; edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index 562061a..3ae25bc 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -230,7 +230,7 @@ void pass_mode_info_to_payload( edid.mode.va = config->display_yres; edid.mode.ha = config->display_xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 72f1bcb..88e599d 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -230,7 +230,7 @@ void pass_mode_info_to_payload( edid.mode.va = config->display_yres; edid.mode.ha = config->display_xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 66b2edc..306baad 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -95,7 +95,7 @@ void rk_display_init(device_t dev, u32 lcdbase, } edid_set_framebuffer_bits_per_pixel(&edid, - conf->framebuffer_bits_per_pixel); + conf->framebuffer_bits_per_pixel, 0); rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid);

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New patch to review for coreboot: edid: Make framebuffer row alignment configurable
by Julius Werner 06 Apr '16

06 Apr '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14267 -gerrit commit bb85653f808c6edb9373d945fe338065536f2d5a Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Apr 6 12:50:40 2016 -0700 edid: Make framebuffer row alignment configurable Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/include/edid.h | 3 ++- src/lib/edid.c | 16 +++++++++++----- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra132/dc.c | 2 +- src/soc/nvidia/tegra210/dc.c | 2 +- src/soc/rockchip/rk3288/display.c | 2 +- 8 files changed, 19 insertions(+), 12 deletions(-) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f32fee0..74a7247 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -113,7 +113,7 @@ static void bochs_init(struct device *dev) edid.mode.va = height; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32); + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 84c2958..dc20f54 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -332,7 +332,7 @@ static void cirrus_init(struct device *dev) edid.mode.va = height; edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32); + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); set_vbe_mode_info_valid(&edid, addr); #else vga_misc_write(0x1); diff --git a/src/include/edid.h b/src/include/edid.h index f46c761..73412a3 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -93,7 +93,8 @@ struct edid { /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); -void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp); +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, + int row_byte_alignment); void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/lib/edid.c b/src/lib/edid.c index 52898fb..0381735 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -481,9 +481,14 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, out->mode.vborder = x[16]; /* We assume rgb888 (32 bits per pixel) framebuffers by default. - * Chipsets that want something else will need to override this - * with another call to edid_set_framebuffer_bits_per_pixel(). */ - edid_set_framebuffer_bits_per_pixel(out, 32); + * Chipsets that want something else will need to override this with + * another call to edid_set_framebuffer_bits_per_pixel(). As a cheap + * heuristic, assume that X86 systems require a 64-byte row alignment + * (since that seems to be true for most Intel chipsets). */ + if (IS_ENABLED(CONFIG_ARCH_X86)) + edid_set_framebuffer_bits_per_pixel(out, 32, 64); + else + edid_set_framebuffer_bits_per_pixel(out, 32, 0); switch ((x[17] & 0x18) >> 3) { case 0x00: @@ -1524,14 +1529,15 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) */ /* Set the framebuffer bits-per-pixel, recalculating all dependent values. */ -void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp) +void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, + int row_byte_alignment) { /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); edid->framebuffer_bits_per_pixel = fb_bpp; edid->bytes_per_line = ALIGN_UP(edid->mode.ha * - div_round_up(fb_bpp, 8), 64); + div_round_up(fb_bpp, 8), row_byte_alignment); edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); edid->y_resolution = edid->mode.va; } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 74202ba..bb96831 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -334,6 +334,6 @@ void display_startup(device_t dev) edid.mode.va = config->yres; edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index 562061a..3ae25bc 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -230,7 +230,7 @@ void pass_mode_info_to_payload( edid.mode.va = config->display_yres; edid.mode.ha = config->display_xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 72f1bcb..88e599d 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -230,7 +230,7 @@ void pass_mode_info_to_payload( edid.mode.va = config->display_yres; edid.mode.ha = config->display_xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 66b2edc..306baad 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -95,7 +95,7 @@ void rk_display_init(device_t dev, u32 lcdbase, } edid_set_framebuffer_bits_per_pixel(&edid, - conf->framebuffer_bits_per_pixel); + conf->framebuffer_bits_per_pixel, 0); rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid);

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Patch set updated for coreboot: nb/amd/mct_ddr3: Add MCE reporting logic
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14265 -gerrit commit d5e1e9f99d162fe7534ec43ebe81deaa67a223ce Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:25:09 2016 -0500 nb/amd/mct_ddr3: Add MCE reporting logic When a fatal error and subsequent sync flood / reset occurs, the MCA status registers may contain valuable information on the cause of the fatal error. Add functions to report MCEs and reset the MCA status registers early in the boot process. Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 23 +++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 2 +- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0b88331..d5699f3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2939,6 +2939,29 @@ fatalexit: die("mct_d: fatalexit"); } +void initialize_mca(uint8_t bsp, uint8_t suppress_errors) { + uint8_t node; + uint32_t mc4_status_high; + uint32_t mc4_status_low; + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + if (bsp && (node > 0)) + break; + + mc4_status_high = pci_read_config32(PCI_DEV(0, 0x18 + node, 3), 0x4c); + mc4_status_low = pci_read_config32(PCI_DEV(0, 0x18 + node, 3), 0x48); + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { + if (!suppress_errors) + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + + /* Clear MC4 error status */ + pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x48, 0x0); + pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x4c, 0x0); + } + } +} + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 67eb2b4..49945dc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -991,6 +991,7 @@ u32 SetupDqsPattern_1PassA(u8 Pass); u32 SetupDqsPattern_1PassB(u8 Pass); u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass); u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, u16 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass); +void initialize_mca(uint8_t bsp, uint8_t suppress_errors); void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); uint64_t mctGetLogicalCPUID(u32 Node); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 1077cb8..65de0f8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -256,7 +256,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) if ((val & 0x3) == 0x3) { /* Node has dram populated */ uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); - if (mc4_status_high != 0) { + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); }

1 0

Patch set updated for coreboot: mb/asus/kgpe-d16|kcma-d8: Enable early MCE reporting
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14266 -gerrit commit 6d4f0f500533fccc3d066d8bc5d9117da26c2b45 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:27:04 2016 -0500 mb/asus/kgpe-d16|kcma-d8: Enable early MCE reporting Change-Id: I55e68c1dba2b5f1d086179af9b3bc30c5e471f6c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/romstage.c | 6 ++++++ src/mainboard/asus/kgpe-d16/romstage.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4552b1c..c217ff3 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -324,6 +324,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint32_t bsp_apicid = 0, val; uint8_t byte; + uint8_t power_on_reset = 0; msr_t msr; int s3resume = acpi_is_wakeup_s3(); @@ -388,6 +389,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + if (!sb7xx_51xx_decode_last_reset()) + power_on_reset = 1; + + initialize_mca(1, power_on_reset); update_microcode(val); post_code(0x33); @@ -404,6 +409,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); + initialize_mca(0, power_on_reset); post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 1904bc2..e6bd91c 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -365,6 +365,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint32_t bsp_apicid = 0, val; uint8_t byte; + uint8_t power_on_reset = 0; msr_t msr; int s3resume = acpi_is_wakeup_s3(); @@ -429,6 +430,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + if (!sb7xx_51xx_decode_last_reset()) + power_on_reset = 1; + + initialize_mca(1, power_on_reset); update_microcode(val); post_code(0x33); @@ -445,6 +450,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); + initialize_mca(0, power_on_reset); post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */

1 0

Patch merged into coreboot/master: buildgcc: enable interwork/multilib for binutils
by gerrit＠coreboot.org 06 Apr '16

06 Apr '16

the following patch was just integrated into master: commit 2fe2d3d7752bd65f87c4bada85853bf29c4278ba Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 5 02:14:48 2016 -0700 buildgcc: enable interwork/multilib for binutils Otherwise, on OS X, some architectures will fail to build libgcc (verified for ARM toolchain). Change-Id: I8b58e0582596ad39cad92e9d478158c46a96a26e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14256 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14256 for details. -gerrit

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New patch to review for coreboot: mb/asus/kgpe-d16|kcma-d8: Enable early MCE reporting
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14266 -gerrit commit 773d82ffd3707263ab43d28541c8ba1fd1cbbda5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:27:04 2016 -0500 mb/asus/kgpe-d16|kcma-d8: Enable early MCE reporting Change-Id: I55e68c1dba2b5f1d086179af9b3bc30c5e471f6c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/romstage.c | 6 ++++++ src/mainboard/asus/kgpe-d16/romstage.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4552b1c..ae0b8aa 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -324,6 +324,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint32_t bsp_apicid = 0, val; uint8_t byte; + uint8_t power_on_reset = 0; msr_t msr; int s3resume = acpi_is_wakeup_s3(); @@ -388,6 +389,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + if (!sb7xx_51xx_decode_last_reset()) + power_on_reset = 1; + + initialize_bsp_mca(power_on_reset); update_microcode(val); post_code(0x33); @@ -404,6 +409,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); + initialize_mca(power_on_reset); post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 1904bc2..0251f14 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -365,6 +365,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint32_t bsp_apicid = 0, val; uint8_t byte; + uint8_t power_on_reset = 0; msr_t msr; int s3resume = acpi_is_wakeup_s3(); @@ -429,6 +430,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + if (!sb7xx_51xx_decode_last_reset()) + power_on_reset = 1; + + initialize_bsp_mca(power_on_reset); update_microcode(val); post_code(0x33); @@ -445,6 +450,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); + initialize_mca(power_on_reset); post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */

1 0

New patch to review for coreboot: nb/amd/mct_ddr3: Add MCE reporting logic
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14265 -gerrit commit 4194bd0ceb4407b64105175a1e394e0c8780a392 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:25:09 2016 -0500 nb/amd/mct_ddr3: Add MCE reporting logic When a fatal error and subsequent sync flood / reset occurs, the MCA status registers may contain valuable information on the cause of the fatal error. Add functions to report MCEs and reset the MCA status registers early in the boot process. Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 37 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 2 +- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0b88331..64a7a38 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2939,6 +2939,43 @@ fatalexit: die("mct_d: fatalexit"); } +static void initialize_bsp_mca(uint8_t suppress_errors) { + uint32_t mc4_status_high; + uint32_t mc4_status_low; + + mc4_status_high = pci_read_config32(PCI_DEV(0, 0x18, 3), 0x4c); + mc4_status_low = pci_read_config32(PCI_DEV(0, 0x18, 3), 0x48); + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { + if (!suppress_errors) + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected on BSP!\n" + "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); + + /* Clear MC4 error status */ + pci_write_config32(PCI_DEV(0, 0x18, 3), 0x48, 0x0); + pci_write_config32(PCI_DEV(0, 0x18, 3), 0x4c, 0x0); + } +} + +static void initialize_mca(uint8_t suppress_errors) { + uint8_t node; + uint32_t mc4_status_high; + uint32_t mc4_status_low; + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + mc4_status_high = pci_read_config32(PCI_DEV(0, 0x18 + node, 3), 0x4c); + mc4_status_low = pci_read_config32(PCI_DEV(0, 0x18 + node, 3), 0x48); + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { + if (!suppress_errors) + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + + /* Clear MC4 error status */ + pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x48, 0x0); + pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x4c, 0x0); + } + } +} + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 1077cb8..65de0f8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -256,7 +256,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) if ((val & 0x3) == 0x3) { /* Node has dram populated */ uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); - if (mc4_status_high != 0) { + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); }

1 0

New patch to review for coreboot: nb/amd/amdfam10: Only flag machine check exception if valid bit is set
by Timothy Pearson 06 Apr '16

06 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14264 -gerrit commit 92aa9c9877f709add23408fdd0199c5f0d4e7ba9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:24:21 2016 -0500 nb/amd/amdfam10: Only flag machine check exception if valid bit is set Change-Id: I42d901ae9445943a863fb3ba9bda5a915f255e02 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index de9f342..eee5c46 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -178,7 +178,7 @@ static void misc_control_init(struct device *dev) if (dimm_present) { uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); uint32_t mc4_status_low = pci_read_config32(dev, 0x48); - if (mc4_status_high != 0) { + if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); }

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coreboot-gerrit April 2016