coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/amd/mct_ddr3: Reenable sync flood after ECC init
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14270 -gerrit commit d59a59e48a29bedad114cc4a58b098be8d4f7756 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 22:07:58 2016 -0500 nb/amd/mct_ddr3: Reenable sync flood after ECC init The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 8 -------- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 9 +++++++++ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index eee5c46..775af66 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -186,14 +186,6 @@ static void misc_control_init(struct device *dev) /* Clear MC4 error status */ pci_write_config32(dev, 0x48, 0x0); pci_write_config32(dev, 0x4c, 0x0); - - if (mem_info->dct_stat[node].mca_config_backed_up) { - dword = pci_read_config32(dev, 0x44); - dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; - dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; - dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(dev, 0x44, dword); - } } } #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 65de0f8..203d112 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -264,6 +264,15 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore MCA settings */ + if (pDCTstat->mca_config_backed_up) { + val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); + val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; + pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); + } } } }

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Patch set updated for coreboot: Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14271 -gerrit commit a3ec6e099acb82dbeb99906ac24261834568be97 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 22:19:43 2016 -0500 Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed" This reverts commit f961becc433bf23fc8744fdfd757f0cdb75c2c62. On studying the BKDG more closely this is not the correct place to enable DIMM parity. Further patches to clarify the parity setup process on Family 15h are forthcoming. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebecd --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index bb12746..3582efa 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5152,7 +5152,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (Status & (1 << SB_Registered)) { /* Registered DIMMs */ - DramConfigLo |= 1 << ParEn; + if (!is_fam15h()) { + DramConfigLo |= 1 << ParEn; + } } else { /* Unbuffered DIMMs */ DramConfigLo |= 1 << UnBuffDimm;

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Patch set updated for coreboot: sb/amd/sb700: Enable reset on sync flood
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14260 -gerrit commit cd7101035d2af4e8e35d944d3a1e78e9f0ee7d23 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Apr 5 23:10:48 2016 -0500 sb/amd/sb700: Enable reset on sync flood The logic to enable reset on sync flood per RPR guidelines somehow ended up guarded on the SATA AHCI setup. Unconditionally enable reset on sync flood per the RPR. Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 76855fb..8042849 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -543,13 +543,13 @@ static void sb700_devices_por_init(void) /* set Device ID consistent with IDE emulation mode configuration */ pci_write_config32(dev, 0x0, 0x43901002); - - /* rpr v2.13 4.17 Reset CPU on Sync Flood */ - abcfg_reg(0x10050, 1 << 2, 1 << 2); } #endif } + /* rpr v2.13 4.17 Reset CPU on Sync Flood */ + abcfg_reg(0x10050, 1 << 2, 1 << 2); + /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);

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Patch set updated for coreboot: nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14273 -gerrit commit 7e09b7a11cc6f547c4d267d01b8f9e148d4fa7e3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 16:10:38 2016 -0500 nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level Certain AMD platforms, such as those using the SP5100 southbridge, contain a very poorly documented bug related to LPC ROM access, which is triggered by repeated (hundreds or more) rapid calls to get_option(). This bug manifests as a complete system deadlock in ramstage device configuration, requiring standby power to be removed from the system to release the deadlock. Cache the platform ECC status to avoid repeated calls to get_option() in the lane count detection logic. Change-Id: I8b48c523218ccc8c113319957d6eca2d15e1070f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 ++++++++--- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0b88331..f31fb3c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -336,9 +336,8 @@ uint8_t is_ecc_enabled(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs { uint8_t ecc_enabled = 1; - if (!mctGet_NVbits(NV_ECC_CAP) || !mctGet_NVbits(NV_ECC)) { - return 0; - } + if (!pMCTstat->try_ecc) + ecc_enabled = 0; if (pDCTstat->NodePresent && pDCTstat->DIMMValid) { if (!(pDCTstat->Status & (1 << SB_ECCDIMMs))) { @@ -2659,6 +2658,12 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, uint8_t s3resume = acpi_is_wakeup_s3(); restartinit: + + if (!mctGet_NVbits(NV_ECC_CAP) || !mctGet_NVbits(NV_ECC)) + pMCTstat->try_ecc = 0; + else + pMCTstat->try_ecc = 1; + mctInitMemGPIOs_A_D(); /* Set any required GPIOs*/ if (s3resume) { printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_En_Fam15\n"); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 67eb2b4..a3a9439 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -300,6 +300,7 @@ struct MCTStatStruc { u32 SysLimit; /* LIMIT[39:8] (system address)*/ uint32_t TSCFreq; uint16_t nvram_checksum; + uint8_t try_ecc; } __attribute__((packed)); /*=============================================================================

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Patch set updated for coreboot: sb/amd/sb700: Add sb7xx_51xx_decode_last_reset()
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14263 -gerrit commit 1816c2efea24995eea19989938fceea103a0e64c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:18:52 2016 -0500 sb/amd/sb700: Add sb7xx_51xx_decode_last_reset() The SB700 family has the ability to report the last reset reason. This is useful in the context of handling MCEs and recovering from fatal errors / sync floods. Add a function to retrieve the last reset flags. Change-Id: I754cb25e47bd9c1e4a29ecb6cb18017d1b7c3dc4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 13 ++++++++++++- src/southbridge/amd/sb700/sb700.h | 1 + 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 8042849..ffdd34b 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -758,6 +758,17 @@ static void sb700_por_init(void) sb700_pmio_por_init(); } +uint16_t sb7xx_51xx_decode_last_reset(void) { + uint16_t reset_status = 0; + reset_status |= pmio_read(0x44); + reset_status |= (pmio_read(0x45) << 8); + printk(BIOS_INFO, "sb700 reset flags: %04x\n", reset_status); + if (reset_status & (0x1 << 10)) + printk(BIOS_WARNING, "WARNING: Last reset was caused by fatal error / sync flood!\n"); + + return reset_status; +} + /* * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. */ diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index f895811..f23956c 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -66,6 +66,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); void sb7xx_51xx_disable_wideio(u8 wio_index); void sb7xx_51xx_early_setup(void); void sb7xx_51xx_before_pci_init(void); +uint16_t sb7xx_51xx_decode_last_reset(void); #else #include <device/pci.h> /* allow override in mainboard.c */

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Patch set updated for coreboot: superio/winbond/w83667hg-a: Set SPI device mask correctly
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14272 -gerrit commit 07b51647e3769bd895071b9464d2042754498617 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 23:56:51 2016 -0500 superio/winbond/w83667hg-a: Set SPI device mask correctly This resolves error messages of the form: ERROR: device PNP: 002e.6 index 98 has no mask. Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/superio/winbond/w83667hg-a/superio.c | 2 +- src/superio/winbond/w83667hg-a/w83667hg-a.h | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 6cd54ef..43b4674 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -99,7 +99,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, - { &ops, W83667HG_A_SPI, PNP_IO1, {0x0ff8, 0}}, + { &ops, W83667HG_A_SPI1, PNP_IO1, {}, {0x0ff8, 0}}, { &ops, W83667HG_A_WDT1}, { &ops, W83667HG_A_ACPI}, { &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, }, diff --git a/src/superio/winbond/w83667hg-a/w83667hg-a.h b/src/superio/winbond/w83667hg-a/w83667hg-a.h index 2a8c511..0c0d427 100644 --- a/src/superio/winbond/w83667hg-a/w83667hg-a.h +++ b/src/superio/winbond/w83667hg-a/w83667hg-a.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> - * Copyright (C) 2015 Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,7 +34,8 @@ #define W83667HG_A_VID_BUSSEL 0x0D /* VID and BUSSEL */ #define W83667HG_A_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ -/* virtual LDN for GPIO */ +/* Virtual LDN for GPIO and SPI */ +#define W83667HG_A_SPI1 ((1 << 8) | W83667HG_A_SPI) #define W83667HG_A_GPIO1 ((1 << 8) | W83667HG_A_WDT1) #define W83667HG_A_GPIO2 ((0 << 8) | W83667HG_A_GPIO2345_V) #define W83667HG_A_GPIO3 ((1 << 8) | W83667HG_A_GPIO2345_V)

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Patch set updated for coreboot: superio/winbond/w83667hg-a: Set SPI device mask correctly
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14272 -gerrit commit b1bab70c97ce11b7d1414a8c4badb57baaf4be11 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 23:56:51 2016 -0500 superio/winbond/w83667hg-a: Set SPI device mask correctly This resolves error messages of the form: ERROR: device PNP: 002e.6 index 98 has no mask. Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/superio/winbond/w83667hg-a/superio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 6cd54ef..6e4dd96 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -99,7 +99,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, - { &ops, W83667HG_A_SPI, PNP_IO1, {0x0ff8, 0}}, + { &ops, W83667HG_A_SPI, PNP_IO1, {0, 0}, {0x0ff8, 0}}, { &ops, W83667HG_A_WDT1}, { &ops, W83667HG_A_ACPI}, { &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, },

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Patch set updated for coreboot: Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14271 -gerrit commit d00634f8346f09afc673f880eb75c0c258744522 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 22:19:43 2016 -0500 Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed" This reverts commit f961becc433bf23fc8744fdfd757f0cdb75c2c62. On studying the BKDG more closely this is not the correct place to enable DIMM parity. Further patches to clarify the parity setup process on Family 15h are forthcoming. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebecd --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index bb12746..3582efa 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5152,7 +5152,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (Status & (1 << SB_Registered)) { /* Registered DIMMs */ - DramConfigLo |= 1 << ParEn; + if (!is_fam15h()) { + DramConfigLo |= 1 << ParEn; + } } else { /* Unbuffered DIMMs */ DramConfigLo |= 1 << UnBuffDimm;

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Patch set updated for coreboot: nb/amd/mct_ddr3: Reenable sync flood after ECC init
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14270 -gerrit commit e3ed67b9b5a6773df7cbfdf15fbc64234eae658e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 22:07:58 2016 -0500 nb/amd/mct_ddr3: Reenable sync flood after ECC init The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 8 -------- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 9 +++++++++ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index eee5c46..775af66 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -186,14 +186,6 @@ static void misc_control_init(struct device *dev) /* Clear MC4 error status */ pci_write_config32(dev, 0x48, 0x0); pci_write_config32(dev, 0x4c, 0x0); - - if (mem_info->dct_stat[node].mca_config_backed_up) { - dword = pci_read_config32(dev, 0x44); - dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; - dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; - dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(dev, 0x44, dword); - } } } #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 65de0f8..203d112 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -264,6 +264,15 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore MCA settings */ + if (pDCTstat->mca_config_backed_up) { + val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); + val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; + pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); + } } } }

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Patch set updated for coreboot: mb/asus/kgpe-d16|kcma-d8: Enable early MCE reporting
by Timothy Pearson 07 Apr '16

07 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14266 -gerrit commit e7ac54a901289368c18e4dde8be97c35c6d8dd28 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Apr 6 13:27:04 2016 -0500 mb/asus/kgpe-d16|kcma-d8: Enable early MCE reporting Change-Id: I55e68c1dba2b5f1d086179af9b3bc30c5e471f6c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/romstage.c | 6 ++++++ src/mainboard/asus/kgpe-d16/romstage.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4552b1c..c217ff3 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -324,6 +324,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint32_t bsp_apicid = 0, val; uint8_t byte; + uint8_t power_on_reset = 0; msr_t msr; int s3resume = acpi_is_wakeup_s3(); @@ -388,6 +389,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + if (!sb7xx_51xx_decode_last_reset()) + power_on_reset = 1; + + initialize_mca(1, power_on_reset); update_microcode(val); post_code(0x33); @@ -404,6 +409,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); + initialize_mca(0, power_on_reset); post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 1904bc2..e6bd91c 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -365,6 +365,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint32_t bsp_apicid = 0, val; uint8_t byte; + uint8_t power_on_reset = 0; msr_t msr; int s3resume = acpi_is_wakeup_s3(); @@ -429,6 +430,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + if (!sb7xx_51xx_decode_last_reset()) + power_on_reset = 1; + + initialize_mca(1, power_on_reset); update_microcode(val); post_code(0x33); @@ -445,6 +450,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); + initialize_mca(0, power_on_reset); post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */

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coreboot-gerrit April 2016