coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

Patch set updated for coreboot: arch/x86: document CAR symbols and expose them in symbols.h
by Aaron Durbin 04 Mar '16

04 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13804 -gerrit commit 31ed96a9b813a7c1e8a865b2457918da0071cd83 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 17:22:17 2016 -0800 arch/x86: document CAR symbols and expose them in symbols.h Attempt to better document the symbol usage in car.ld for cache-as-ram usage. Additionally, add _car_region_[start|end] that completely covers the entire cache-as-ram region. The _car_data_[start|end] symbols were renamed to _car_relocatable_data_[start|end] in the hopes of making it clearer that objects within there move. Lastly, all these symbols were added to arch/symbols.h. Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/car.ld | 11 +++--- src/arch/x86/include/arch/early_variables.h | 8 ++--- src/arch/x86/include/arch/symbols.h | 52 +++++++++++++++++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 4 +-- src/cpu/x86/car.c | 10 +++--- 5 files changed, 69 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d19e613..c221fb8 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -18,6 +18,7 @@ /* This file is included inside a SECTIONS block */ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { + _car_region_start = . ; /* Vboot work buffer is completely volatile outside of verstage and * romstage. Appropriate code needs to handle the transition. */ #if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) @@ -36,12 +37,12 @@ * so that multiple stages (romstage and verstage) have a consistent * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) - _car_data_start = .; + _car_relocatable_data_start = .; /* The timestamp implementation relies on this storage to be around * after migration. One of the fields indicates not to use it as the * backing store once cbmem comes online. Therefore, this data needs - * to reside in the migrated area (between _car_data_start and - * _car_data_end). */ + * to reside in the migrated area (between _car_relocatable_data_start + * and _car_relocatable_data_end). */ TIMESTAMP(., 0x100) /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -51,7 +52,9 @@ *(.car.global_data); . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _car_global_end = .; - _car_data_end = .; + _car_relocatable_data_end = .; + + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } /* Global variables are not allowed in romstage diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 16eeacc..e78b846 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -16,6 +16,7 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H +#include <arch/symbols.h> #include <stdlib.h> #include <rules.h> @@ -59,18 +60,15 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) -extern char _car_data_start[]; -extern char _car_data_end[]; - static inline size_t car_data_size(void) { - size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + size_t car_size = _car_relocatable_data_size; return ALIGN(car_size, 64); } static inline size_t car_object_offset(void *ptr) { - return (char *)ptr - &_car_data_start[0]; + return (char *)ptr - &_car_relocatable_data_start[0]; } #else diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h new file mode 100644 index 0000000..e055fa0 --- /dev/null +++ b/src/arch/x86/include/arch/symbols.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_SYMBOLS_H +#define __ARCH_SYMBOLS_H + +/* + * The _car_region_[start|end] covers the entirety of the cache as ram + * region. All other symbols with the _car prefix a subsets of this + * larger region. + */ +extern char _car_region_start[]; +extern char _car_region_end[]; +#define _car_region_size (_car_region_end - _car_region_start) + +/* + * This is the stack used under CONFIG_C_ENVIRONMENT_BOOTBLOCK for + * all stages that execute when cache-as-ram is up. + */ +extern char _car_stack_start[]; +extern char _car_stack_end[]; +#define _car_stack_size (_car_stack_end - _car_stack_start) + +/* + * The _car_relocatable_data_[start|end] symbols cover CAR data which is + * relocatable once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. The _car_global_[start|end] is a subset of the + * relocatable region which excludes the timestamp region because of + * intricacies in the timestamp code. + */ +extern char _car_relocatable_data_start[]; +extern char _car_relocatable_data_end[]; +#define _car_relocatable_data_size \ + (_car_relocatable_data_end - _car_relocatable_data_start) +extern char _car_global_start[]; +extern char _car_global_end[]; +#define _car_global_size (_car_global_end - _car_global_start) + +#endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 7e33d32..0a59696 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -150,11 +150,11 @@ void post_cache_as_ram(void) void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); print_car_debug("Copying data from cache to RAM..."); - memcpy_(migrated_car, &_car_data_start[0], car_size); + memcpy_(migrated_car, _car_relocatable_data_start, car_size); print_car_debug(" Done\n"); print_car_debug("Verifying data integrity in RAM..."); - if (memcmp_(migrated_car, &_car_data_start[0], car_size) == 0) + if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0) print_car_debug(" Done\n"); else print_car_debug(" FAILED\n"); diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index fda3f7d..f9b427a 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -46,8 +46,8 @@ void *car_get_var_ptr(void *var) { char *migrated_base = NULL; int offset; - void * _car_start = &_car_data_start; - void * _car_end = &_car_data_end; + void * _car_start = _car_relocatable_data_start; + void * _car_end = _car_relocatable_data_end; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -84,8 +84,8 @@ void *car_get_var_ptr(void *var) void *car_sync_var_ptr(void *var) { void ** mig_var = car_get_var_ptr(var); - void * _car_start = &_car_data_start; - void * _car_end = &_car_data_end; + void * _car_start = _car_relocatable_data_start; + void * _car_end = _car_relocatable_data_end; /* Not moved or migrated yet. */ if (mig_var == var) @@ -129,7 +129,7 @@ static void do_car_migrate_variables(void) return; } - memcpy(migrated_base, &_car_data_start[0], car_size); + memcpy(migrated_base, _car_relocatable_data_start, car_size); /* Mark that the data has been moved. */ car_migrated = ~0;

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add Notify Phase API
by Andrey Petrov 04 Mar '16

04 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13800 -gerrit commit ee621a8eeca73005cb5dafb2e54a03f0e53a530d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:19:07 2016 -0800 drivers/intel/fsp2_0: Add Notify Phase API This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/notify.c | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c new file mode 100644 index 0000000..820bd45 --- /dev/null +++ b/src/drivers/intel/fsp2_0/notify.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +enum fsp_status fsp_notify(enum fsp_notify_phase phase) +{ + fsp_notify_fn fspnotify; + struct fsp_notify_params notify_params = { .phase = phase }; + + if (!fsps_hdr.silicon_init_entry_offset) + return FSP_NOT_FOUND; + + fspnotify = (void*) (fsps_hdr.image_base + + fsps_hdr.notify_phase_entry_offset); + + printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + + return fspnotify(&notify_params); +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add SiliconInit API
by Andrey Petrov 04 Mar '16

04 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13799 -gerrit commit e904161609ce6e45b9cc4728faf350c68b88f3ec Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:17:45 2016 -0800 drivers/intel/fsp2_0: Add SiliconInit API This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/silicon_init.c | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c new file mode 100644 index 0000000..9d6eb46 --- /dev/null +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> + +#define FSPS_OFFSET_S_CONFIG 0x40 + +struct fsp_header fsps_hdr; + +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); + +static enum fsp_status do_silicon_init(struct fsp_header *hdr) +{ + uint8_t *silicon_upd; + struct FSP_S_CONFIG *fsp_s_config; + fsp_silicon_init_fn silicon_init; + enum fsp_status status; + + silicon_upd = (uint8_t *) (hdr->cfg_region_offset + hdr->image_base); + /* UPD region is in RW memory, so it can be modified directly */ + fsp_s_config = (struct FSP_S_CONFIG *) (silicon_upd + + FSPS_OFFSET_S_CONFIG); + + /* Give SoC/mainboard a chance to populate entries */ + platform_fsp_silicon_init_params_cb(fsp_s_config); + + silicon_init = (void *) (hdr->image_base + + hdr->silicon_init_entry_offset); + + status = silicon_init(silicon_upd); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + return status; +} + +enum fsp_status fsp_silicon_init(struct range_entry *range) +{ + /* Load FSP-S and save FSP header. We will need it for Notify */ + if (fsp_load_binary(&fsps_hdr, "blobs/fsps.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_silicon_init(&fsps_hdr); +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add MemoryInit API
by Andrey Petrov 04 Mar '16

04 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798 -gerrit commit 1b70eea938f3184edc341b80fe1f36bd3c7b1d22 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:16:33 2016 -0800 drivers/intel/fsp2_0: Add MemoryInit API This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/memory_init.c | 125 +++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c new file mode 100644 index 0000000..06d0b03 --- /dev/null +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +/* offsets for fields in ARCH UPD from the beginning of FSP-M config region */ +#define FSPM_UPD_OFFSET_REVISION 0x20 +#define FSPM_UPD_OFFSET_NVSBUFFER 0x24 +#define FSPM_UPD_OFFSET_STACKBASE 0x28 +#define FSPM_UPD_OFFSET_STACKSIZE 0x2c +#define FSPM_UPD_OFFSET_BLSZ 0x30 +#define FSPM_UPD_OFFSET_BOOTMODE 0x34 +/* + * FSP_M_CONFIG structure start. + * FSP_M_CONFIG contains all SoC-specific parameters. + */ +#define FSPM_UPD_OFFSET_MCONFIG 0x40 + +struct fsp_memory_init_params { + void *nvs_buffer; + void *raminit_upd; + void **hob_list; +} __attribute__ ((__packed__)); + +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (struct fsp_memory_init_params *); + +static struct FSP_M_CONFIG *fspm_parse_upd(void *cfg_region, + struct fsp_m_arch_upd *arch_upd) +{ + uint8_t *raw_hdr = (uint8_t*) cfg_region; + + arch_upd->revision = read8(raw_hdr + FSPM_UPD_OFFSET_REVISION); + arch_upd->nvs_buffer = read32(raw_hdr + FSPM_UPD_OFFSET_NVSBUFFER); + arch_upd->stack_base = read32(raw_hdr + FSPM_UPD_OFFSET_STACKBASE); + arch_upd->stack_size = read32(raw_hdr + FSPM_UPD_OFFSET_STACKSIZE); + arch_upd->bootloader_tolumsz = read32(raw_hdr + FSPM_UPD_OFFSET_BLSZ); + arch_upd->boot_mode = read32(raw_hdr + FSPM_UPD_OFFSET_BOOTMODE); + + return (struct FSP_M_CONFIG *) (raw_hdr + FSPM_UPD_OFFSET_MCONFIG); +} + +static void fspm_update_cfg(void *cfg_region, struct fsp_m_arch_upd *arch_upd) +{ + uint8_t *raw_hdr = (uint8_t*) cfg_region; + + write8(raw_hdr + FSPM_UPD_OFFSET_REVISION, arch_upd->revision); + write32(raw_hdr + FSPM_UPD_OFFSET_NVSBUFFER, arch_upd->nvs_buffer); + write32(raw_hdr + FSPM_UPD_OFFSET_STACKBASE, arch_upd->stack_base); + write32(raw_hdr + FSPM_UPD_OFFSET_STACKSIZE, arch_upd->stack_size); + write32(raw_hdr + FSPM_UPD_OFFSET_BLSZ, arch_upd->bootloader_tolumsz); + write32(raw_hdr + FSPM_UPD_OFFSET_BOOTMODE, arch_upd->boot_mode); +} + +static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, + struct fsp_header *hdr) +{ + enum fsp_status status; + fsp_memory_init_fn fsp_raminit; + struct fsp_memory_init_params raminit_params; + struct fsp_m_arch_upd arch_upd; + struct FSP_M_CONFIG *fsp_m_config; + void *mem_upd; + + post_code(0x34); + /* UPD region resides in CAR. Thus, it can be directly modified. */ + mem_upd = (void *)(hdr->cfg_region_offset + hdr->image_base); + + /* Read default values from arch_upd, perhaps they can be useful. */ + fsp_m_config = fspm_parse_upd(mem_upd, &arch_upd); + + /* Get any board specific changes */ + raminit_params.nvs_buffer = NULL; + raminit_params.raminit_upd = mem_upd; + raminit_params.hob_list = hob_list_ptr; + + /* Give SoC and mainboard a chance to update the UPD */ + platform_fsp_memory_init_params_cb(&arch_upd, fsp_m_config); + + /* Update the actual upd region */ + fspm_update_cfg(mem_upd, &arch_upd); + + /* Call FspMemoryInit */ + fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); + printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", raminit_params.raminit_upd); + printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_raminit(&raminit_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + return status; +} + +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range) +{ + struct fsp_header hdr; + + if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_fsp_memory_init(hob_list, &hdr); +}

1 0

New patch to review for coreboot: tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabled
by Martin Roth 04 Mar '16

04 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13890 -gerrit commit 835b084b7823d079a1de3c27d8a98a74520e2d0d Author: Martin Roth <martinroth(a)google.com> Date: Thu Mar 3 16:20:53 2016 -0700 tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabled If the TPM code isn't getting built in, the Kconfig symbol CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist. This ends up creating an invalid operating region in the ACPI tables, causing a bluescreen in windows. Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/pc80/tpm/acpi/tpm.asl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index de25114..090bf4c 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -15,6 +15,8 @@ /* Trusted Platform Module */ +#if CONFIG_LPC_TPM + Device (TPM) { Name (_HID, EISAID ("PNP0C31")) @@ -41,7 +43,7 @@ Device (TPM) Method (_STA, 0) { -#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE +#if !CONFIG_TPM_DEACTIVATE If (LAnd (LGreater (DVID, 0), LLess (DVID, 0xffffffff))) { Return (0xf) } Else { @@ -213,3 +215,5 @@ Device (TPM) Return (Buffer (1) { 0 }) } } + +#endif /* CONFIG_LPC_TPM */

1 0

Patch set updated for coreboot: arch/x86: Add common assembly code for stages that run in CAR
by Andrey Petrov 04 Mar '16

04 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13861 -gerrit commit b955a0590d5d649cd60de14701cf3bfef8c1a3c2 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:37:15 2016 -0800 arch/x86: Add common assembly code for stages that run in CAR This adds a few assembly lines that are generic enough to be shared between romstage and verstage that are ran in CAR. The GDT reload is bypassed and the stack is reloaded with the CAR stack defined in car.ld. The entry point for all those stages is car_stage_entry(). Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/assembly_entry.S | 45 ++++++++++++++++++++++++++++++++++++++++- src/arch/x86/include/arch/cpu.h | 9 +++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 01e91b0..8a13189 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. + * Copyright 2016 Google Inc. + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,8 @@ * GNU General Public License for more details. */ +#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) + /* This file assembles the start of the romstage program by the order of the * includes. Thus, it's extremely important that one pays very careful * attention to the order of the includes. */ @@ -31,3 +34,43 @@ * cache-as-ram setup files would be here. */ #include <generated/assembly.inc> + +#else + +/* + * This path for stages that post bootblock when employing + * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc + * as all those settings are cached within the processor. In order to + * continue with C code execution one needs to set stack pointer and clear + * CAR_GLOBAL variables that are stage specific. + */ +.section ".text._start", "ax", @progbits +.global _start +_start: + + /* + * This code is meant to be used for stages that are ran in CAR. + * The assumption is that gdt is already loaded. So in order to + * continue with C code execution we needed to set stack pointer + * and clear CAR_GLOBAL variables that are stage-specific. + */ + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + jmp car_stage_entry + +/* This is here for linking purposes. */ +.weak car_stage_entry +car_stage_entry: +1: + jmp 1b +#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 408fa15..f50901f 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -239,4 +239,13 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) #define alwaysinline inline __attribute__((always_inline)) +#ifndef __ROMCC__ +/* + * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() + * is the symbol jumped to for each stage after bootblock using + * cache-as-ram. + */ +void asmlinkage car_stage_entry(void); +#endif + #endif /* ARCH_CPU_H */

1 0

Patch merged into coreboot/master: arch/x86: Allow soc/chipset to set linking address
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit ccd300b4b402167bd1f390ba13378593f1962712 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:04:51 2016 -0800 arch/x86: Allow soc/chipset to set linking address Until recently x86 romstage used to be linked at some default address. The address itself is not meaningful because the code was normally relocated at address calculated during insertion in CBFS. Since some newer SoC run romstage at CAR it became useful to link romstage code at some address in CAR and avoid relocation during build/run time altogether. Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13860 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13860 for details. -gerrit

1 0

Patch set updated for coreboot: arch/x86: always use _start as entry symbol for all stages
by Aaron Durbin 03 Mar '16

03 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13882 -gerrit commit 28a4ffb4c96532c9e31562174b14c9195d7f45d8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 15:26:10 2016 -0600 arch/x86: always use _start as entry symbol for all stages Instead of keeping track of all the combinations of entry points depending on the stage and other options just use _start. That way, there's no need to update the arch/header.ld for complicated cases as _start is always the entry point for a stage. Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/header.ld | 23 ----------------------- src/cpu/x86/32bit/entry32.inc | 12 ++++++++++-- 2 files changed, 10 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index d7fbf07..77eb187 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -20,27 +20,4 @@ PHDRS to_load PT_LOAD; } -/* - * For CONFIG_SEPARATE_VERSTAGE romstage doesn't have the cache-as-ram setup. - * It only contains the teardown code. The verstage has the cache-as-ram setup - * code. Therefore, it needs the protected_start symbol as its entry point. - * The romstage entry will be named _start for consistency, but it's likely - * to be implemented in the chipset code in order to control the logic flow. - */ -#if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) - #if ENV_RAMSTAGE || ENV_RMODULE || ENV_ROMSTAGE - ENTRY(_start) - #elif ENV_VERSTAGE - ENTRY(protected_start) - #endif -#else - #if ENV_RAMSTAGE || ENV_RMODULE - ENTRY(_start) - #elif ENV_ROMSTAGE - ENTRY(protected_start) - #endif -#endif - -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) && ENV_BOOTBLOCK ENTRY(_start) -#endif diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 9ef3bc1..8c39008 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -2,6 +2,7 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> +#include <rules.h> .code32 @@ -44,10 +45,17 @@ gdt_end: * * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. + * + * In the bootblock there is already a ljmp to __protected_start and + * the reset vector jumps to symbol _start16bit in entry16.inc from + * the reset vectors's symbol which is _start. Therefore, don't + * expose the _start symbol for bootblock. */ .align 4 -.globl protected_start -protected_start: +#if !ENV_BOOTBLOCK +.globl _start +_start: +#endif lgdt %cs:gdtptr ljmp $ROM_CODE_SEG, $__protected_start

1 0

Patch set updated for coreboot: arch/x86: rename reset_vector -> _start
by Aaron Durbin 03 Mar '16

03 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13881 -gerrit commit 044bfedeca52afef5009628cba54e74f16ac3c2b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 15:13:12 2016 -0600 arch/x86: rename reset_vector -> _start In order to align the entry points for the various stages on x86 to _start one needs to rename the reset_vector symbol. The section is the same; it's just a symbol change. Change-Id: I0e6bbf1da04a6e248781a9c222a146725c34268a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/failover.ld | 2 +- src/arch/x86/include/arch/header.ld | 2 +- src/cpu/x86/16bit/reset16.inc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index c8c00bb..e9613d9 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -ENTRY(reset_vector) +ENTRY(_start) MEMORY { rom : ORIGIN = 0xffff0000, LENGTH = 64K diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 89cb6de..d7fbf07 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -42,5 +42,5 @@ PHDRS #endif #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) && ENV_BOOTBLOCK -ENTRY(reset_vector) +ENTRY(_start) #endif diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index d99f0b1..48cb275 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -1,7 +1,7 @@ .section ".reset", "ax", %progbits .code16 -.globl reset_vector -reset_vector: +.globl _start +_start: .byte 0xe9 .int _start16bit - ( . + 2 ) /* Note: The above jump is hand coded to work around bugs in binutils.

1 0

Patch merged into coreboot/master: cpu/x86/16bit: rename _start -> _start16bit
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit f8468d43e01c8110bdcb5956106c904b41d1ca09 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 14:47:37 2016 -0600 cpu/x86/16bit: rename _start -> _start16bit In order to avoid collisions with other _start symbols while grepping and future ones be explicit about which _start this one is: the 16-bit one only used by the reset vector in the bootblock. Change-Id: I6d7580596c0e6602a87fb158633ce9d45910cec2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13880 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13880 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2016