coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch merged into coreboot/master: cpu/x86/16bit/reset16: mark reset vector executable
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit 0fd068b3c3b80274fa2db9eaf27a85ceb9dd47e7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 14:55:32 2016 -0600 cpu/x86/16bit/reset16: mark reset vector executable It's helpful to see the reset vector in objdump output. Without it being marked executable it doesn't get displayed. Change-Id: I85cb72ea0727d3f3c2186ae20b9c5cfe5d23aeed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13879 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13879 for details. -gerrit

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Patch merged into coreboot/master: cpu/x86/16bit/reset16: remove stale 32-bit jump
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit 998d8561d10df7a1077a5bfa4465a571607c0f66 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 13:42:57 2016 -0600 cpu/x86/16bit/reset16: remove stale 32-bit jump Patrick at least indicated this jump after the reset vector jump was a remnant from some construct used long ago in the project. It's not longer used (nor could I find where it was). Therefore, remove it. Change-Id: I31512c66a9144267739b08d5f9659c4fcde1b794 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13878 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13878 for details. -gerrit

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Patch set updated for coreboot: amd/thatcher: Removed #include early_serial.c from romstage
by Antonello Dettori 03 Mar '16

03 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13887 -gerrit commit f3ffc50c6725ede2fa4a34e7c81a3db3235934bf Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Mar 3 16:25:35 2016 +0000 amd/thatcher: Removed #include early_serial.c from romstage Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/amd/thatcher/romstage.c | 2 +- src/superio/smsc/lpc47n217/Makefile.inc | 1 + src/superio/smsc/lpc47n217/early_serial.c | 2 +- src/superio/smsc/lpc47n217/lpc47n217.h | 5 +++++ 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 10b7df1..4c9c8fa 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -30,7 +30,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/smsc/lpc47n217/early_serial.c> +#include <superio/smsc/lpc47n217/lpc47n217.h> #include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc index f3c5ad4..0bff637 100644 --- a/src/superio/smsc/lpc47n217/Makefile.inc +++ b/src/superio/smsc/lpc47n217/Makefile.inc @@ -14,4 +14,5 @@ ## GNU General Public License for more details. ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index dfe06b9..454d77f 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -105,7 +105,7 @@ static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n217/lpc47n217.h b/src/superio/smsc/lpc47n217/lpc47n217.h index 20689d1..1cae5a0 100644 --- a/src/superio/smsc/lpc47n217/lpc47n217.h +++ b/src/superio/smsc/lpc47n217/lpc47n217.h @@ -17,6 +17,9 @@ #ifndef SUPERIO_SMSC_LPC47N217_LPC47N217_H #define SUPERIO_SMSC_LPC47N217_LPC47N217_H +#include <arch/io.h> +#include <stdint.h> + /* * These are arbitrary, but must match declarations in the mainboard * devicetree.cb file. Values chosen to match SMSC LPC47B37x. @@ -27,4 +30,6 @@ #define LPC47N217_MAX_CONFIG_REGISTER 0x39 +void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase); + #endif

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add utility functions
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit 9738970c152600798407fd3f4e6703b2df277982 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:15:37 2016 -0800 drivers/intel/fsp2_0: Add utility functions This adds a set of utility functions that help load and identify FSP blobs. Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13797 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13797 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add coreboot<->FSP header files
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit b37fd67e8757e2eaf3ae7dd453e9aaa1518e9439 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Mar 1 16:25:38 2016 -0800 drivers/intel/fsp2_0: Add coreboot<->FSP header files This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13796 for details. -gerrit

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Patch set updated for coreboot: amd/thatcher: Removed #include early_serial.c from romstage
by Antonello Dettori 03 Mar '16

03 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13887 -gerrit commit 19f20eec7bf86e9167fb538a41b5b4b6ce25c079 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Mar 3 16:25:35 2016 +0000 amd/thatcher: Removed #include early_serial.c from romstage Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/amd/thatcher/romstage.c | 3 ++- src/superio/smsc/lpc47n217/Makefile.inc | 2 ++ src/superio/smsc/lpc47n217/early_serial.c | 3 ++- src/superio/smsc/lpc47n217/lpc47n217.h | 6 ++++++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 10b7df1..11997bc 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +31,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/smsc/lpc47n217/early_serial.c> +#include <superio/smsc/lpc47n217/lpc47n217.h> #include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc index f3c5ad4..df9f1b5 100644 --- a/src/superio/smsc/lpc47n217/Makefile.inc +++ b/src/superio/smsc/lpc47n217/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2005 Digital Design Corporation +## Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,4 +15,5 @@ ## GNU General Public License for more details. ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index dfe06b9..8944b26 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -105,7 +106,7 @@ static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n217/lpc47n217.h b/src/superio/smsc/lpc47n217/lpc47n217.h index 20689d1..cc38a3c 100644 --- a/src/superio/smsc/lpc47n217/lpc47n217.h +++ b/src/superio/smsc/lpc47n217/lpc47n217.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,9 @@ #ifndef SUPERIO_SMSC_LPC47N217_LPC47N217_H #define SUPERIO_SMSC_LPC47N217_LPC47N217_H +#include <arch/io.h> +#include <stdint.h> + /* * These are arbitrary, but must match declarations in the mainboard * devicetree.cb file. Values chosen to match SMSC LPC47B37x. @@ -27,4 +31,6 @@ #define LPC47N217_MAX_CONFIG_REGISTER 0x39 +void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase); + #endif

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Patch set updated for coreboot: adm/thatcher: Removed #include early_serial.c from romstage
by Antonello Dettori 03 Mar '16

03 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13887 -gerrit commit ac8507066becc4624121600eba194372ceadac0c Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Mar 3 16:25:35 2016 +0000 adm/thatcher: Removed #include early_serial.c from romstage Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/amd/thatcher/romstage.c | 3 ++- src/superio/smsc/lpc47n217/Makefile.inc | 2 ++ src/superio/smsc/lpc47n217/early_serial.c | 3 ++- src/superio/smsc/lpc47n217/lpc47n217.h | 6 ++++++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 10b7df1..11997bc 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +31,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/smsc/lpc47n217/early_serial.c> +#include <superio/smsc/lpc47n217/lpc47n217.h> #include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc index f3c5ad4..df9f1b5 100644 --- a/src/superio/smsc/lpc47n217/Makefile.inc +++ b/src/superio/smsc/lpc47n217/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2005 Digital Design Corporation +## Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,4 +15,5 @@ ## GNU General Public License for more details. ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index dfe06b9..8944b26 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -105,7 +106,7 @@ static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n217/lpc47n217.h b/src/superio/smsc/lpc47n217/lpc47n217.h index 20689d1..cc38a3c 100644 --- a/src/superio/smsc/lpc47n217/lpc47n217.h +++ b/src/superio/smsc/lpc47n217/lpc47n217.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2016 Antonello Dettori <dev(a)dettori.io> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,9 @@ #ifndef SUPERIO_SMSC_LPC47N217_LPC47N217_H #define SUPERIO_SMSC_LPC47N217_LPC47N217_H +#include <arch/io.h> +#include <stdint.h> + /* * These are arbitrary, but must match declarations in the mainboard * devicetree.cb file. Values chosen to match SMSC LPC47B37x. @@ -27,4 +31,6 @@ #define LPC47N217_MAX_CONFIG_REGISTER 0x39 +void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase); + #endif

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Patch merged into coreboot/master: kconfig_lint: make sure if and endif statements are balanced
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit 0e6c0e18e37b0fa8d543b39a97e676896c7799ba Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 2 12:16:13 2016 -0700 kconfig_lint: make sure if and endif statements are balanced In Kconfig files, the 'if' and 'endif' statements need to match up. A file can't start an if statement that's completed in the next file. Add a check as the files are being parsed to make sure that they match up correctly. Change-Id: If51207ea037089ab84c768e5a868270468cf4c4f Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13876 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit b97009ed43704fe452cc1c1e8b7f5ef40e5828fd Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Feb 28 15:24:04 2016 +0100 nb/intel/sandybridge/raminit: Fill SMBIOS type17 info Fill minimal info required for SMBIOS type 17. Report * DIMM size * channel * rank per DIMM * speed in Mhz * DIMM type * slot * manufacturer ID * serial Allows dmidecode to print the current RAM configuration. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Linux 4.3 * dmidecode 3.0 dmidecode output: Handle 0x0005, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Handle 0x0006, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-1-DIMM-1 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/13852 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13852 for details. -gerrit

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Patch merged into coreboot/master: src/device/dram/ddr3: Parse additional information
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit 076915955fa3bf05a1c324327827522063b9f757 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Feb 29 18:21:00 2016 +0100 src/device/dram/ddr3: Parse additional information Parse manufacturer id and ASCII serial. Required for SMBIOS type 17 field. Change-Id: I710de1a6822e4777c359d0bfecc6113cb2a5ed8e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/13862 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13862 for details. -gerrit

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coreboot-gerrit March 2016