coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: arch/x86: Add common assembly code for stages that run in CAR
by Aaron Durbin 03 Mar '16

03 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13861 -gerrit commit b847931d9bdc92a497b268bdf7f7a6f05d12b1cc Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:37:15 2016 -0800 arch/x86: Add common assembly code for stages that run in CAR This adds a few assembly lines that are generic enough to be shared between romstage and verstage that are ran in CAR. The GDT reload is bypassed and the stack is reloaded with the CAR stack defined in car.ld. The entry point for all those stages is car_stage_entry(). Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/assembly_entry.S | 45 ++++++++++++++++++++++++++++++++++++++++- src/arch/x86/include/arch/cpu.h | 9 +++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 01e91b0..8a13189 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. + * Copyright 2016 Google Inc. + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,8 @@ * GNU General Public License for more details. */ +#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) + /* This file assembles the start of the romstage program by the order of the * includes. Thus, it's extremely important that one pays very careful * attention to the order of the includes. */ @@ -31,3 +34,43 @@ * cache-as-ram setup files would be here. */ #include <generated/assembly.inc> + +#else + +/* + * This path for stages that post bootblock when employing + * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc + * as all those settings are cached within the processor. In order to + * continue with C code execution one needs to set stack pointer and clear + * CAR_GLOBAL variables that are stage specific. + */ +.section ".text._start", "ax", @progbits +.global _start +_start: + + /* + * This code is meant to be used for stages that are ran in CAR. + * The assumption is that gdt is already loaded. So in order to + * continue with C code execution we needed to set stack pointer + * and clear CAR_GLOBAL variables that are stage-specific. + */ + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + jmp car_stage_entry + +/* This is here for linking purposes. */ +.weak car_stage_entry +car_stage_entry: +1: + jmp 1b +#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 408fa15..f50901f 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -239,4 +239,13 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) #define alwaysinline inline __attribute__((always_inline)) +#ifndef __ROMCC__ +/* + * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() + * is the symbol jumped to for each stage after bootblock using + * cache-as-ram. + */ +void asmlinkage car_stage_entry(void); +#endif + #endif /* ARCH_CPU_H */

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Patch merged into coreboot/master: buildgcc: Bump version to 1.36
by gerrit＠coreboot.org 03 Mar '16

03 Mar '16

the following patch was just integrated into master: commit 266b5171a30e0334b7503ec3284665b244d77b61 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 1 22:34:34 2016 -0800 buildgcc: Bump version to 1.36 Numerous changes have gone in since the last bump, let's increase the version. Change-Id: Ie3ae8c24b26bd22b70bc5ddf5c1125b5b1d3a021 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13873 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/13873 for details. -gerrit

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Patch set updated for coreboot: src/mainboard: Fix cmos.default for power_on_after_fail on laptop's
by Philipp Deppenwiese 03 Mar '16

03 Mar '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13884 -gerrit commit 4524dccec02d19d5542f1a3071752a82aa578c34 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Thu Mar 3 01:14:03 2016 +0100 src/mainboard: Fix cmos.default for power_on_after_fail on laptop's power_on_after_fail=Enable in cmos.default lead to wake on AC behaviour on mobile systems. Therefore set cmos.default entry to "Disable" in order to improve user experience. Change-Id: I977a4e6bc028c8c4c7fc1c2f5fdd74a59e951c60 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/t420s/cmos.default | 4 ++-- src/mainboard/lenovo/t430s/cmos.default | 4 ++-- src/mainboard/lenovo/t520/cmos.default | 4 ++-- src/mainboard/lenovo/t530/cmos.default | 4 ++-- src/mainboard/lenovo/x201/cmos.default | 2 +- src/mainboard/lenovo/x220/cmos.default | 2 +- src/mainboard/lenovo/x230/cmos.default | 4 ++-- src/mainboard/packardbell/ms2290/cmos.default | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 6f3f75d..1b8e212 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -13,4 +13,4 @@ sata_mode=AHCI fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable -hyper_threading=Enable \ No newline at end of file +hyper_threading=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 710edfc..50d17ae 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 8038d64..1b8e212 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/packardbell/ms2290/cmos.default b/src/mainboard/packardbell/ms2290/cmos.default index aef840c..43c09e8 100644 --- a/src/mainboard/packardbell/ms2290/cmos.default +++ b/src/mainboard/packardbell/ms2290/cmos.default @@ -1,6 +1,6 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable sata_mode=AHCI

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New patch to review for coreboot: src/mainboard: Fix cmos.default for power_on_after_fail on laptop's
by Philipp Deppenwiese 03 Mar '16

03 Mar '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13884 -gerrit commit 966f4ce358cd3d59e405cd81040b90b2cceba77a Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Thu Mar 3 01:14:03 2016 +0100 src/mainboard: Fix cmos.default for power_on_after_fail on laptop's power_on_after_fail=Enable in cmos.default lead to wake on AC behaviour on mobile systems. Therefore set cmos.default entry to "Disable" in order to improve user experience. Change-Id: I977a4e6bc028c8c4c7fc1c2f5fdd74a59e951c60 --- src/mainboard/lenovo/t420s/cmos.default | 4 ++-- src/mainboard/lenovo/t430s/cmos.default | 4 ++-- src/mainboard/lenovo/t520/cmos.default | 4 ++-- src/mainboard/lenovo/t530/cmos.default | 4 ++-- src/mainboard/lenovo/x201/cmos.default | 2 +- src/mainboard/lenovo/x220/cmos.default | 2 +- src/mainboard/lenovo/x230/cmos.default | 4 ++-- src/mainboard/packardbell/ms2290/cmos.default | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 6f3f75d..1b8e212 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -13,4 +13,4 @@ sata_mode=AHCI fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable -hyper_threading=Enable \ No newline at end of file +hyper_threading=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 710edfc..50d17ae 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 8038d64..1b8e212 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 99a0f1a..00e8863 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -1,7 +1,7 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable volume=0x3 first_battery=Primary @@ -14,4 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/packardbell/ms2290/cmos.default b/src/mainboard/packardbell/ms2290/cmos.default index aef840c..43c09e8 100644 --- a/src/mainboard/packardbell/ms2290/cmos.default +++ b/src/mainboard/packardbell/ms2290/cmos.default @@ -1,6 +1,6 @@ boot_option=Fallback baud_rate=115200 debug_level=Spew -power_on_after_fail=Enable +power_on_after_fail=Disable nmi=Enable sata_mode=AHCI

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Patch set updated for coreboot: cpu/x86/16bit/reset16: remove stale 32-bit jump
by Ronald G. Minnich 03 Mar '16

03 Mar '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13878 -gerrit commit 13c86f368c0aa64cd4c6594bef31e63d74e6875d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 13:42:57 2016 -0600 cpu/x86/16bit/reset16: remove stale 32-bit jump Patrick at least indicated this jump after the reset vector jump was a remnant from some construct used long ago in the project. It's not longer used (nor could I find where it was). Therefore, remove it. Change-Id: I31512c66a9144267739b08d5f9659c4fcde1b794 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/16bit/reset16.inc | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index 33712d1..2220aab 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -10,7 +10,4 @@ reset_vector: * instead of the weird 16 bit relocations that binutils does not * handle consistenly between versions because they are used so rarely. */ - .org 0x8; - .code32 - jmp protected_start .previous

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Patch set updated for coreboot: soc/intel/apollolake: Add cbmem_top() implementation
by Andrey Petrov 03 Mar '16

03 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13883 -gerrit commit 843a769f8dcd5b8c02fd66419f4181ac10f7ac4c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 2 15:09:27 2016 -0800 soc/intel/apollolake: Add cbmem_top() implementation On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 3 +++ src/soc/intel/apollolake/memmap.c | 27 +++++++++++++++++++++++++++ src/soc/intel/apollolake/placeholders.c | 5 ----- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a95e27c..9bc7fcf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -19,15 +19,18 @@ bootblock-y += uart_early.c romstage-y += placeholders.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c +romstage-y += memmap.c romstage-y += mmap_boot.c romstage-y += uart_early.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c +ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart_early.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c new file mode 100644 index 0000000..8cfb073 --- /dev/null +++ b/src/soc/intel/apollolake/memmap.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <soc/northbridge.h> +#include <soc/pci_devs.h> + +static uintptr_t smm_region_start(void) +{ + return pci_read_config32(NB_DEV_ROOT, TSEG) & 0xfff00000; +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c index 3a818eb..808bd54 100644 --- a/src/soc/intel/apollolake/placeholders.c +++ b/src/soc/intel/apollolake/placeholders.c @@ -3,11 +3,6 @@ #include <delay.h> #include <rules.h> -void *cbmem_top(void) -{ - return NULL; -} - void southbridge_smi_set_eos(void) { }

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New patch to review for coreboot: soc/intel/apollolake: Add cbmem_top() implementation
by Andrey Petrov 03 Mar '16

03 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13883 -gerrit commit bf8745d855f40bdb2ec26bbbb13bf5c11895b978 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 2 15:09:27 2016 -0800 soc/intel/apollolake: Add cbmem_top() implementation On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 3 +++ src/soc/intel/apollolake/memmap.c | 27 +++++++++++++++++++++++++++ src/soc/intel/apollolake/placeholders.c | 5 ----- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a95e27c..9bc7fcf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -19,15 +19,18 @@ bootblock-y += uart_early.c romstage-y += placeholders.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c +romstage-y += memmap.c romstage-y += mmap_boot.c romstage-y += uart_early.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c +ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart_early.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c new file mode 100644 index 0000000..8cfb073 --- /dev/null +++ b/src/soc/intel/apollolake/memmap.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <soc/northbridge.h> +#include <soc/pci_devs.h> + +static uintptr_t smm_region_start(void) +{ + return pci_read_config32(NB_DEV_ROOT, TSEG) & 0xfff00000; +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c index 3a818eb..808bd54 100644 --- a/src/soc/intel/apollolake/placeholders.c +++ b/src/soc/intel/apollolake/placeholders.c @@ -3,11 +3,6 @@ #include <delay.h> #include <rules.h> -void *cbmem_top(void) -{ - return NULL; -} - void southbridge_smi_set_eos(void) { }

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Add configuration for memory training
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13870 -gerrit commit fbb298887361a1352401ed38010e7361a8a8835c Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Mar 1 17:03:23 2016 -0800 mainboard/intel/apollolake_rvp: Add configuration for memory training Pass memory training information to MemoryInit, so memory training can be completed. Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/romstage.c | 125 +++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 7cfef9f..c94c6a3 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1 +1,124 @@ -/* Nothing here yet, but this file is needed by the build system */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <fsp/api.h> +#include <fsp/FspmUpd.h> + +static const uint8_t swizzling_rvp1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static const uint8_t swizzling0_rvp2[] = { + 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1, + 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9, +}; + +static const uint8_t swizzling1_rvp2[] = { + 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4, + 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25, +}; + +static const uint8_t swizzling2_rvp2[] = { + 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18, + 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2, +}; + +static const uint8_t swizzling3_rvp2[] = { + 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19, + 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, +}; + +static void rvp1_fill_memory_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Profile = 33; + cfg->DIMM0SPDAddress = 0xa0; + cfg->DIMM1SPDAddress = 0xa4; + cfg->Ch0_RankEnable = 0; + cfg->Ch0_DeviceWidth = 0; + cfg->Ch0_DramDensity = 0; + cfg->Ch0_Option = 3; + cfg->Ch1_RankEnable = 0; + cfg->Ch1_DeviceWidth = 0; + cfg->Ch1_DramDensity = 0; + cfg->Ch1_Option = 3; + cfg->Ch2_RankEnable = 0; + cfg->Ch2_DeviceWidth = 0; + cfg->Ch2_DramDensity = 0; + cfg->Ch2_Option = 3; + cfg->Ch3_RankEnable = 0; + cfg->Ch3_DeviceWidth = 0; + cfg->Ch3_DramDensity = 0; + cfg->Ch3_Option = 3; + memcpy(cfg->Ch0_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); +} + +static void rvp2_fill_memory_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Profile = 5; + cfg->DIMM0SPDAddress = 0; + cfg->DIMM1SPDAddress = 0; + cfg->Ch0_RankEnable = 3; + cfg->Ch0_DeviceWidth = 2; + cfg->Ch0_DramDensity = 0; + cfg->Ch0_Option = 3; + cfg->Ch1_RankEnable = 3; + cfg->Ch1_DeviceWidth = 2; + cfg->Ch1_DramDensity = 0; + cfg->Ch1_Option = 3; + cfg->Ch2_RankEnable = 3; + cfg->Ch2_DeviceWidth = 2; + cfg->Ch2_DramDensity = 0; + cfg->Ch2_Option = 3; + cfg->Ch3_RankEnable = 3; + cfg->Ch3_DeviceWidth = 2; + cfg->Ch3_DramDensity = 0; + cfg->Ch3_Option = 3; + memcpy(cfg->Ch0_Bit_swizzling, swizzling0_rvp2, + sizeof(swizzling0_rvp2)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling1_rvp2, + sizeof(swizzling1_rvp2)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling2_rvp2, + sizeof(swizzling2_rvp2)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling3_rvp2, + sizeof(swizzling3_rvp2)); +} + +void mainboard_memory_init_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Package = 0; + cfg->MemoryDown = 1; + cfg->DDR3LPageSize = 0; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0; + cfg->SliceHashMask = 0; + cfg->InterleavedMode = 0; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 0; + cfg->RmtMode = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) + rvp1_fill_memory_params(cfg); + else + rvp2_fill_memory_params(cfg); +}

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Patch set updated for coreboot: soc/intel/apollolake: Enable using FSP 2.0 driver
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13806 -gerrit commit 9f3846c297bd5ff4a987e6a8c6b81a8f800cbd77 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 18:39:38 2016 -0800 soc/intel/apollolake: Enable using FSP 2.0 driver Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2ff93c9..e7b4a90 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 + select PLATFORM_USES_FSP2_0 config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address"

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Patch set updated for coreboot: cpu/x86/16bit/reset16: mark reset vector executable
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13879 -gerrit commit e2d0387b64e4aaaf32239f7f3224c4bd83dfdd2d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 14:55:32 2016 -0600 cpu/x86/16bit/reset16: mark reset vector executable It's helpful to see the reset vector in objdump output. Without it being marked executable it doesn't get displayed. Change-Id: I85cb72ea0727d3f3c2186ae20b9c5cfe5d23aeed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/16bit/reset16.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index 2220aab..ebc3d4c 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -1,4 +1,4 @@ - .section ".reset" + .section ".reset", "ax", %progbits .code16 .globl reset_vector reset_vector:

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coreboot-gerrit March 2016