coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: buildgcc: Add 'nocolor' option to remove color codes from output
by gerrit＠coreboot.org 02 Mar '16

02 Mar '16

the following patch was just integrated into master: commit 4a53db06ecd7a39a1839adc9fe5ad72a62a4dc1e Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 1 15:21:07 2016 -0700 buildgcc: Add 'nocolor' option to remove color codes from output When writing to a logfile, the color codes just make things confusing. The --nocolor option will allow these to not be printed. Change-Id: I67645aac20b420ac83b828e77e0e50aab88d3d47 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13866 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Use $(CURDIR) instead of $(PWD)
by gerrit＠coreboot.org 02 Mar '16

02 Mar '16

the following patch was just integrated into master: commit 9b1936dc829ef1c0fd32368ecbce432f1b05cffb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 1 12:55:47 2016 -0800 buildgcc: Use $(CURDIR) instead of $(PWD) coreboot's top level Makefile does the same, so let's stay consistent. Change-Id: I9e995f3ecadd05d6fbfda64b45dee3a9900d9189 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13869 for details. -gerrit

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Patch merged into coreboot/master: abuild: Use 12 lines of context for errors
by gerrit＠coreboot.org 02 Mar '16

02 Mar '16

the following patch was just integrated into master: commit ed5642234ada914d057c31e77c322932e2e0e641 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Dec 14 16:36:45 2015 -0800 abuild: Use 12 lines of context for errors The current default of 6 lines leaves us with no context about the actual error: *** ERROR: 3 warnings encountered, and warnings are errors. coreboot-gerrit/util/kconfig/Makefile:38: recipe for target 'oldconfig' failed make[1]: *** [oldconfig] Error 1 make[1]: Leaving directory 'coreboot-gerrit' Change-Id: I67e7d740e7b3b1c66005dc1bf50557a20bc15428 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/12720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12720 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Disable RISC-V GDB
by gerrit＠coreboot.org 02 Mar '16

02 Mar '16

the following patch was just integrated into master: commit c77e0419098f3ce241922d60181727ee676c2594 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 1 22:28:20 2016 -0800 buildgcc: Disable RISC-V GDB Our GDB doesn't support RISC-V yet, so let's disable it for now to keep the build from breaking. Change-Id: Iecc6d97fb16d16410c56965abeea55c67800f220 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/13872 for details. -gerrit

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New patch to review for coreboot: cbfstool: Use fixed width data types for e820entry struct.
by Werner Zeh 02 Mar '16

02 Mar '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13875 -gerrit commit 4f3ecaefc45d562b5de881c6d63778915d706954 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Mar 2 17:55:31 2016 +0100 cbfstool: Use fixed width data types for e820entry struct. In e820entry struct, the members are defined using standard types. This can lead to different structure size when compiling on 32 bit vs. 64 bit environment. This in turn will affect the size of the struct linux_params. Using the fixed width types resolves this issue and ensures that the size of the structures will have the same length on both 32 and 64 bit systems. Change-Id: I1869ff2090365731e79b34950446f1791a083d0f Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/cbfstool/linux.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/linux.h b/util/cbfstool/linux.h index 529d239..b96f447 100644 --- a/util/cbfstool/linux.h +++ b/util/cbfstool/linux.h @@ -31,9 +31,9 @@ typedef uint64_t u64; #define E820MAX 32 /* number of entries in E820MAP */ struct e820entry { - unsigned long long addr; /* start of memory segment */ - unsigned long long size; /* size of memory segment */ - unsigned long type; /* type of memory segment */ + u64 addr; /* start of memory segment */ + u64 size; /* size of memory segment */ + u32 type; /* type of memory segment */ #define E820_RAM 1 #define E820_RESERVED 2 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */

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New patch to review for coreboot: cbfstool: Initialize contents of linux_params to 0
by Werner Zeh 02 Mar '16

02 Mar '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13874 -gerrit commit a84c8a7ef8d4f66b652015e5919d36f60783fec4 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Mar 2 17:45:53 2016 +0100 cbfstool: Initialize contents of linux_params to 0 When linux is used as payload, the parameters to the kernel are build when cbfstool includes bzImage into the image. Since not all parameters are used, the unused will stay uninitialized. There is a chance, that the uninitialized parameters contain random values. That in turn can lead to early kernel panic. To avoid it, initialize all parameters with 0 at the beginning. The ones that are used will be set up as needed and the rest will contain 0 for sure. This way, kernel can deal with the provided parameter list the right way. Change-Id: Id081c24351ec80375255508378b5e1eba2a92e48 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/cbfstool/cbfs-payload-linux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index 34b21e9..79ee7ea 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -224,6 +224,8 @@ int parse_bzImage_to_payload(const struct buffer *input, /* Setup parameter block. Imitate FILO. */ struct linux_params params; + + memset(&params, 0, sizeof(struct linux_params)); params.mount_root_rdonly = hdr->root_flags; params.orig_root_dev = hdr->root_dev; /* Sensible video defaults. Might be overridden on runtime by coreboot tables. */

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
by Patrick Rudolph 02 Mar '16

02 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13852 -gerrit commit 504d9b55cb139eaff685f838beee8661ed3d568a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Feb 28 15:24:04 2016 +0100 nb/intel/sandybridge/raminit: Fill SMBIOS type17 info Fill minimal info required for SMBIOS type 17. Report * DIMM size * channel * rank per DIMM * speed in Mhz * DIMM type * slot * manufacturer ID * serial Allows dmidecode to print the current RAM configuration. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Linux 4.3 * dmidecode 3.0 dmidecode output: Handle 0x0005, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Handle 0x0006, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-1-DIMM-1 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 46 +++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 40089e2..348468d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -27,6 +27,8 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <memory_info.h> +#include <smbios.h> #include "raminit_native.h" #include "sandybridge.h" #include <delay.h> @@ -233,6 +235,45 @@ static void toggle_io_reset(void) { } /* + * Fill cbmem with information for SMBIOS type 17. + */ +static void fill_smbios17(dimm_info *info, uint16_t ddr_freq) +{ + struct memory_info *mem_info; + int channel, slot; + struct dimm_info *dimm; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (!mem_info) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + FOR_ALL_CHANNELS for(slot = 0; slot < NUM_SLOTS; slot++) { + dimm = &mem_info->dimm[mem_info->dimm_cnt]; + if (info->dimm[channel][slot].size_mb) { + dimm->ddr_type = MEMORY_TYPE_DDR3; + dimm->ddr_frequency = ddr_freq; + dimm->dimm_size = info->dimm[channel][slot].size_mb; + dimm->channel_num = channel; + dimm->rank_per_dimm = info->dimm[channel][slot].ranks; + dimm->dimm_num = slot; + memcpy(dimm->module_part_number, + info->dimm[channel][slot].part_number, 16); + dimm->mod_id = info->dimm[channel][slot].manufacturer_id; + dimm->mod_type = info->dimm[channel][slot].dimm_type; + dimm->bus_width = info->dimm[channel][slot].width; + mem_info->dimm_cnt++; + } + } +} + +/* * Dump in the log memory controller configuration as read from the memory * controller registers. */ @@ -3884,6 +3925,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, { int me_uma_size; int cbmem_was_inited; + dimm_info info; MCHBAR32(0x5f00) |= 1; @@ -3937,8 +3979,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, } if (!s3resume) { - dimm_info info; - /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &info, &ctrl); @@ -4065,6 +4105,8 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, outb(0x6, 0xcf9); halt(); } + + fill_smbios17(&info, (1000 << 8) / ctrl.tCK); } #define HOST_BRIDGE PCI_DEVFN(0, 0)

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Patch set updated for coreboot: amdfwtool: Fix some PSP2 issues
by Zheng Bao 02 Mar '16

02 Mar '16

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13808 -gerrit commit 36f4870c1ce5dd3f870a468e7590c93324855a9b Author: zbao <fishbaozi(a)gmail.com> Date: Wed Mar 2 14:47:27 2016 +0800 amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 195 +++++++++++++++++++++++---------------------- 1 file changed, 101 insertions(+), 94 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 073c138..3dff2ac 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -46,6 +46,8 @@ * +------------+---------------+----------------+------------+ * | 'PSP2' | Fletcher | Count |Look up mode| * +------------+---------------+----------------+------------+ + * | R e s e r v e d | + * +------------+---------------+----------------+------------+ * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory * +------------+---------------+----------------+------------+ * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory @@ -166,6 +168,7 @@ typedef enum _amd_fw_type { AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, + AMD_FW_INVALID, } amd_fw_type; typedef struct _amd_fw_entry { @@ -187,6 +190,7 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, { .type = AMD_FW_PSP_SMUSCS }, { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_INVALID }, }; #if PSP2 @@ -204,6 +208,7 @@ amd_fw_entry amd_psp2_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, { .type = AMD_FW_PSP_SMUSCS }, { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_INVALID }, }; #endif @@ -211,6 +216,7 @@ amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, + { .type = AMD_FW_INVALID }, }; void fill_psp_head(uint32_t *pspdir, int count) @@ -221,70 +227,76 @@ void fill_psp_head(uint32_t *pspdir, int count) pspdir[1] = fletcher32((uint16_t *)&pspdir[1], (count *16 + 16)/2 - 2); } -uint32_t integerate_one_fw(void *base, uint32_t pos, uint32_t *romsig, int i) +uint32_t integrate_firmwares(void *base, uint32_t pos, uint32_t *romsig, amd_fw_entry *fw_table) { int fd; struct stat fd_stat; + int i; - if (amd_fw_table[i].filename != NULL) { - fd = open (amd_fw_table[i].filename, O_RDONLY); - fstat(fd, &fd_stat); - - switch (amd_fw_table[i].type) { - case AMD_FW_IMC: - pos = ALIGN(pos, 0x10000); - romsig[1] = pos + ROM_BASE_ADDRESS; - break; - case AMD_FW_GEC: - romsig[2] = pos + ROM_BASE_ADDRESS; - break; - case AMD_FW_XHCI: - romsig[3] = pos + ROM_BASE_ADDRESS; - break; - default: - /* Error */ - break; - } + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i ++) { + if (fw_table[i].filename != NULL) { + fd = open (fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + + switch (fw_table[i].type) { + case AMD_FW_IMC: + pos = ALIGN(pos, 0x10000); + romsig[1] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_GEC: + romsig[2] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_XHCI: + romsig[3] = pos + ROM_BASE_ADDRESS; + break; + default: + /* Error */ + break; + } - read (fd, base+pos, fd_stat.st_size); + read (fd, base+pos, fd_stat.st_size); - pos += fd_stat.st_size; - pos = ALIGN(pos, 0x100); - close (fd); + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } } return pos; } -uint32_t integerate_one_psp(void *base, uint32_t pos, uint32_t *pspdir, int i) +uint32_t integrate_psp_firmwares(void *base, uint32_t pos, uint32_t *pspdir, amd_fw_entry *fw_table) { int fd; struct stat fd_stat; + int i; - if (amd_psp_fw_table[i].type == AMD_PSP_FUSE_CHAIN) { - pspdir[4+4*i+0] = amd_psp_fw_table[i].type; - pspdir[4+4*i+1] = 0xFFFFFFFF; - pspdir[4+4*i+2] = 1; - pspdir[4+4*i+3] = 0; - } else if (amd_psp_fw_table[i].filename != NULL) { - pspdir[4+4*i+0] = amd_psp_fw_table[i].type; - - fd = open (amd_psp_fw_table[i].filename, O_RDONLY); - fstat(fd, &fd_stat); - pspdir[4+4*i+1] = fd_stat.st_size; - - pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; - pspdir[4+4*i+3] = 0; - - read (fd, base+pos, fd_stat.st_size); - - pos += fd_stat.st_size; - pos = ALIGN(pos, 0x100); - close (fd); - } else { - /* This APU doesn't have this firmware. */ + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i ++) { + if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { + pspdir[4+4*i+0] = fw_table[i].type; + pspdir[4+4*i+1] = 0xFFFFFFFF; + pspdir[4+4*i+2] = 1; + pspdir[4+4*i+3] = 0; + } else if (fw_table[i].filename != NULL) { + pspdir[4+4*i+0] = fw_table[i].type; + + fd = open (fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + pspdir[4+4*i+1] = fd_stat.st_size; + + pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; + pspdir[4+4*i+3] = 0; + + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } else { + /* This APU doesn't have this firmware. */ + } } - + fill_psp_head(pspdir, i); return pos; } @@ -363,12 +375,15 @@ void register_fw_filename(amd_fw_type type, char filename[], int pspflag) int main(int argc, char **argv) { - int c, count, pspflag = 0; + int c, pspflag = 0; #if PSP2 int psp2flag = 0; - int psp2count; uint32_t *psp2dir; #endif +#if PSP_COMBO + int psp2count; +#endif + void *rom = NULL; uint32_t current; uint32_t *amd_romsig, *pspdir; @@ -519,9 +534,7 @@ int main(int argc, char **argv) } current = ALIGN(current, 0x100); - for (count = 0; count < sizeof(amd_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_fw(rom, current, amd_romsig, count); - } + current = integrate_firmwares(rom, current, amd_romsig, amd_fw_table); if (pspflag == 1) { current = ALIGN(current, 0x10000); @@ -529,51 +542,45 @@ int main(int argc, char **argv) amd_romsig[4] = current + ROM_BASE_ADDRESS; current += 0x200; /* Conservative size of pspdir */ - for (count = 0; count < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, pspdir, count); - } - - fill_psp_head(pspdir, count); + current = integrate_psp_firmwares(rom, current, pspdir, amd_psp_fw_table); + } #if PSP2 - if (psp2flag == 1) { - current = ALIGN(current, 0x10000); /* PSP2 dir */ - psp2dir = rom + current; - amd_romsig[5] = current + ROM_BASE_ADDRESS; - current += 0x100; /* Add conservative size of psp2dir. */ - - #if PSP_COMBO - /* TODO: remove the hardcode. */ - psp2count = 1; /* Start from 1. */ - /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ - /* Now the psp2dir is psp combo dir. */ - psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ - psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ - psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS; - pspdir = rom + current; - psp2dir[psp2count*4 + 3] = 0; - - current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ - for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, pspdir, count); - } - fill_psp_head(pspdir, count); - /* } */ /* End of loop */ - - /* fill the PSP combo head */ - psp2dir[0] = 0x50535032; /* 'PSP2' */ - psp2dir[2] = psp2count; /* Count */ - psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ - psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2); - #else - for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, psp2dir, count); - } - fill_psp_head(psp2dir, count); - #endif - } + if (psp2flag == 1) { + current = ALIGN(current, 0x10000); /* PSP2 dir */ + psp2dir = rom + current; + amd_romsig[5] = current + ROM_BASE_ADDRESS; + current += 0x100; /* Add conservative size of psp2dir. */ + +#if PSP_COMBO + /* TODO: remove the hardcode. */ + psp2count = 1; /* Start from 1. */ + /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ + /* Now the psp2dir is psp combo dir. */ + psp2dir[psp2count*4 + 0 + 4] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ + psp2dir[psp2count*4 + 1 + 4] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ + psp2dir[psp2count*4 + 2 + 4] = current + ROM_BASE_ADDRESS; + pspdir = rom + current; + psp2dir[psp2count*4 + 3 + 4] = 0; + + current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ + current = integrate_psp_firmwares(rom, current, pspdir, amd_psp2_fw_table); + /* } */ /* End of loop */ + + /* fill the PSP combo head */ + psp2dir[0] = 0x50535032; /* 'PSP2' */ + psp2dir[2] = psp2count; /* Count */ + psp2dir[3] = 1; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ + psp2dir[4] = 0; /* reserved 4 dwords. */ + psp2dir[5] = 0; + psp2dir[6] = 0; + psp2dir[7] = 0; + psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 32)/2 - 2); +#else + current = integrate_psp_firmwares(rom, current, psp2dir, amd_psp2_fw_table); #endif } +#endif targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); write(targetfd, amd_romsig, current - AMD_ROMSIG_OFFSET);

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New patch to review for coreboot: buildgcc: Bump version to 1.36
by Stefan Reinauer 02 Mar '16

02 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13873 -gerrit commit 52ba958bd8dbf55edee2379e088ef37fc6b95a1b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 1 22:34:34 2016 -0800 buildgcc: Bump version to 1.36 Numerous changes have gone in since the last bump, let's increase the version. Change-Id: Ie3ae8c24b26bd22b70bc5ddf5c1125b5b1d3a021 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 679c0ef..df9ac4a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="January 29th, 2016" -CROSSGCC_VERSION="1.35" +CROSSGCC_DATE="March 1st, 2016" +CROSSGCC_VERSION="1.36" # default settings PACKAGE=GCC

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New patch to review for coreboot: buildgcc: Disable RISC-V GDB
by Stefan Reinauer 02 Mar '16

02 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13872 -gerrit commit 522b87f2d0d3fc8a03488a732b5de73297832783 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 1 22:28:20 2016 -0800 buildgcc: Disable RISC-V GDB Our GDB doesn't support RISC-V yet, so let's disable it for now to keep the build from breaking. Change-Id: Iecc6d97fb16d16410c56965abeea55c67800f220 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index aadf316..62adb7f 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -57,7 +57,8 @@ build-mips: @$(MAKE) build_tools BUILD_PLATFORM=mipsel-elf build-riscv: - @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf + # GDB is currently not supported on RISC-V + @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf build-power8: @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu

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coreboot-gerrit March 2016