coreboot-gerrit March 2016

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add hand-off-block parsers
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13801 -gerrit commit 56f80321af65820d51deca9591c5bcd16c22bca9 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Feb 25 14:20:38 2016 -0800 drivers/intel/fsp2_0: Add hand-off-block parsers FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 294 ++++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c new file mode 100644 index 0000000..3bc33af --- /dev/null +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -0,0 +1,294 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <fsp/util.h> +#include <inttypes.h> +#include <lib.h> +#include <string.h> + +#define HOB_HEADER_LEN 8 + +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + +static const char *resource_names[] = { + [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY", + [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO", + [EFI_RESOURCE_IO] = "IO", + [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE", + [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT", + [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED", + [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ +static const uint8_t uuid_owner_bootloader_tolum[16] = { + 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, +}; + +static const uint8_t uuid_owner_fsp[16] = { + 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43, + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, +}; + +static const uint8_t uuid_owner_tseg[16] = { + 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49, + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 +}; + +static const uint8_t empty_uuid[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const struct uuid_name_map { + const void *uuid; + const char *name; +} uuid_names[] = { + { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, + { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, + { uuid_owner_tseg, "TSEG" }, +}; + +static const char *resource_name(enum resource_type type) +{ + if (type >= ARRAY_SIZE(resource_names)) + return "UNKNOWN"; + return resource_names[type]; +} + +/* + * Utilities for walking HOBs + */ + +static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +{ + return !memcmp(uuid1, uuid2, 16); +} + +static const char *uuid_name(const uint8_t uuid[16]) +{ + size_t i; + const struct uuid_name_map *owner_entry; + + for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { + owner_entry = uuid_names + i; + if (uuid_compare(uuid, owner_entry->uuid)) + return owner_entry->name; + } + return "UNKNOWN"; +} + +static const struct hob_header *next_hob(const struct hob_header *parent) +{ + union { + const struct hob_header *hob; + uintptr_t addr; + } hob_walker; + + hob_walker.hob = parent; + hob_walker.addr += parent->length; + return hob_walker.hob; +} + +static const void *hob_header_to_struct(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN; + return hob_walker.hob_descr; +} + +static const void *hob_header_to_extension_hob(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */ + return hob_walker.hob_descr; +} + +static const +struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +{ + return hob_header_to_struct(hob); +} + +/* + * Utilities for locating and identifying HOBs + */ + +void fsp_save_hob_list(void *hob_list_ptr) +{ + void **cbmem_loc; + cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr)); + *cbmem_loc = hob_list_ptr; +} + +const void *fsp_get_hob_list(void) +{ + void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); + + return (list_loc) ? (*list_loc) : NULL; +} + +static const +struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, + const uint8_t uuid[16]) +{ + const struct hob_resource *res; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = hob_header_to_resource(hob); + if (uuid_compare(res->owner_guid, uuid)) + return res; + } + return NULL; +} + +void fsp_find_reserved_memory(struct resource *res, const void *hob_list) +{ + const struct hob_resource *fsp_mem; + + memset(res, 0, sizeof(*res)); + + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + + if (!fsp_mem) { + return; + } + + res->base = fsp_mem->addr; + res->size = fsp_mem->length; +} + +/* + * Utilities for printing HOB information + */ + +static void print_guid(const void *base) +{ + uint32_t big; + uint16_t mid[2]; + + const uint8_t *id = base; + big = read32(id + 0); + mid[0] = read16(id + 4); + mid[1] = read16(id + 6); + + printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + big, mid[0], mid[1], + id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); +} + +static void print_resource_descriptor(const void *base) +{ + const struct hob_resource *res; + + res = hob_header_to_resource(base); + + printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + resource_name(res->type), res->attribute_type); + printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + if (!uuid_compare(res->owner_guid, empty_uuid)) { + printk(BIOS_DEBUG, "\tOwner GUID: "); + print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + } +} + + +void fsp_print_memory_resource_hobs(const void *hob_list) +{ + const struct hob_header *hob = hob_list; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) + print_resource_descriptor(hob); + } +} + +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) +{ + const uint8_t *hob_uuid; + const struct hob_header *hob = fsp_get_hob_list(); + + if (!hob) + return NULL; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_GUID_EXTENSION) + continue; + + hob_uuid = hob_header_to_struct(hob); + if (uuid_compare(hob_uuid, uuid)) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + } + + return NULL; +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add Notify Phase API
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13800 -gerrit commit 68172cb0cc4ffa97deaa0f6a1371c16eb66caad4 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:19:07 2016 -0800 drivers/intel/fsp2_0: Add Notify Phase API This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/notify.c | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c new file mode 100644 index 0000000..820bd45 --- /dev/null +++ b/src/drivers/intel/fsp2_0/notify.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +enum fsp_status fsp_notify(enum fsp_notify_phase phase) +{ + fsp_notify_fn fspnotify; + struct fsp_notify_params notify_params = { .phase = phase }; + + if (!fsps_hdr.silicon_init_entry_offset) + return FSP_NOT_FOUND; + + fspnotify = (void*) (fsps_hdr.image_base + + fsps_hdr.notify_phase_entry_offset); + + printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + + return fspnotify(&notify_params); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add SiliconInit API
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13799 -gerrit commit 0fc746fcb0fd9ff47bcb93865d392d230413020f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:17:45 2016 -0800 drivers/intel/fsp2_0: Add SiliconInit API This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/silicon_init.c | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c new file mode 100644 index 0000000..9d6eb46 --- /dev/null +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> + +#define FSPS_OFFSET_S_CONFIG 0x40 + +struct fsp_header fsps_hdr; + +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); + +static enum fsp_status do_silicon_init(struct fsp_header *hdr) +{ + uint8_t *silicon_upd; + struct FSP_S_CONFIG *fsp_s_config; + fsp_silicon_init_fn silicon_init; + enum fsp_status status; + + silicon_upd = (uint8_t *) (hdr->cfg_region_offset + hdr->image_base); + /* UPD region is in RW memory, so it can be modified directly */ + fsp_s_config = (struct FSP_S_CONFIG *) (silicon_upd + + FSPS_OFFSET_S_CONFIG); + + /* Give SoC/mainboard a chance to populate entries */ + platform_fsp_silicon_init_params_cb(fsp_s_config); + + silicon_init = (void *) (hdr->image_base + + hdr->silicon_init_entry_offset); + + status = silicon_init(silicon_upd); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + return status; +} + +enum fsp_status fsp_silicon_init(struct range_entry *range) +{ + /* Load FSP-S and save FSP header. We will need it for Notify */ + if (fsp_load_binary(&fsps_hdr, "blobs/fsps.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_silicon_init(&fsps_hdr); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add MemoryInit API
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798 -gerrit commit c804131044ec8084309ee4610c5265d304fbd00e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:16:33 2016 -0800 drivers/intel/fsp2_0: Add MemoryInit API This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/memory_init.c | 125 +++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c new file mode 100644 index 0000000..06d0b03 --- /dev/null +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +/* offsets for fields in ARCH UPD from the beginning of FSP-M config region */ +#define FSPM_UPD_OFFSET_REVISION 0x20 +#define FSPM_UPD_OFFSET_NVSBUFFER 0x24 +#define FSPM_UPD_OFFSET_STACKBASE 0x28 +#define FSPM_UPD_OFFSET_STACKSIZE 0x2c +#define FSPM_UPD_OFFSET_BLSZ 0x30 +#define FSPM_UPD_OFFSET_BOOTMODE 0x34 +/* + * FSP_M_CONFIG structure start. + * FSP_M_CONFIG contains all SoC-specific parameters. + */ +#define FSPM_UPD_OFFSET_MCONFIG 0x40 + +struct fsp_memory_init_params { + void *nvs_buffer; + void *raminit_upd; + void **hob_list; +} __attribute__ ((__packed__)); + +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (struct fsp_memory_init_params *); + +static struct FSP_M_CONFIG *fspm_parse_upd(void *cfg_region, + struct fsp_m_arch_upd *arch_upd) +{ + uint8_t *raw_hdr = (uint8_t*) cfg_region; + + arch_upd->revision = read8(raw_hdr + FSPM_UPD_OFFSET_REVISION); + arch_upd->nvs_buffer = read32(raw_hdr + FSPM_UPD_OFFSET_NVSBUFFER); + arch_upd->stack_base = read32(raw_hdr + FSPM_UPD_OFFSET_STACKBASE); + arch_upd->stack_size = read32(raw_hdr + FSPM_UPD_OFFSET_STACKSIZE); + arch_upd->bootloader_tolumsz = read32(raw_hdr + FSPM_UPD_OFFSET_BLSZ); + arch_upd->boot_mode = read32(raw_hdr + FSPM_UPD_OFFSET_BOOTMODE); + + return (struct FSP_M_CONFIG *) (raw_hdr + FSPM_UPD_OFFSET_MCONFIG); +} + +static void fspm_update_cfg(void *cfg_region, struct fsp_m_arch_upd *arch_upd) +{ + uint8_t *raw_hdr = (uint8_t*) cfg_region; + + write8(raw_hdr + FSPM_UPD_OFFSET_REVISION, arch_upd->revision); + write32(raw_hdr + FSPM_UPD_OFFSET_NVSBUFFER, arch_upd->nvs_buffer); + write32(raw_hdr + FSPM_UPD_OFFSET_STACKBASE, arch_upd->stack_base); + write32(raw_hdr + FSPM_UPD_OFFSET_STACKSIZE, arch_upd->stack_size); + write32(raw_hdr + FSPM_UPD_OFFSET_BLSZ, arch_upd->bootloader_tolumsz); + write32(raw_hdr + FSPM_UPD_OFFSET_BOOTMODE, arch_upd->boot_mode); +} + +static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, + struct fsp_header *hdr) +{ + enum fsp_status status; + fsp_memory_init_fn fsp_raminit; + struct fsp_memory_init_params raminit_params; + struct fsp_m_arch_upd arch_upd; + struct FSP_M_CONFIG *fsp_m_config; + void *mem_upd; + + post_code(0x34); + /* UPD region resides in CAR. Thus, it can be directly modified. */ + mem_upd = (void *)(hdr->cfg_region_offset + hdr->image_base); + + /* Read default values from arch_upd, perhaps they can be useful. */ + fsp_m_config = fspm_parse_upd(mem_upd, &arch_upd); + + /* Get any board specific changes */ + raminit_params.nvs_buffer = NULL; + raminit_params.raminit_upd = mem_upd; + raminit_params.hob_list = hob_list_ptr; + + /* Give SoC and mainboard a chance to update the UPD */ + platform_fsp_memory_init_params_cb(&arch_upd, fsp_m_config); + + /* Update the actual upd region */ + fspm_update_cfg(mem_upd, &arch_upd); + + /* Call FspMemoryInit */ + fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); + printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", raminit_params.raminit_upd); + printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_raminit(&raminit_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + return status; +} + +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range) +{ + struct fsp_header hdr; + + if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_fsp_memory_init(hob_list, &hdr); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add utility functions
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13797 -gerrit commit c379d93eec9254f49e9aeb885ae7acc4a4eab232 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:15:37 2016 -0800 drivers/intel/fsp2_0: Add utility functions This adds a set of utility functions that help load and identify FSP blobs. Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/util.c | 123 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c new file mode 100644 index 0000000..4fd4f68 --- /dev/null +++ b/src/drivers/intel/fsp2_0/util.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> +#include <memrange.h> +#include <string.h> + +static bool looks_like_fsp_header(const uint8_t *raw_hdr) +{ + if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) { + printk(BIOS_ALERT, "Did not find a valid FSP signature\n"); + return false; + } + + if (read32(raw_hdr + 4) != FSP_HDR_LEN) { + printk(BIOS_ALERT, "FSP header has invalid length\n"); + return false; + } + + return true; +} + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) +{ + const uint8_t *raw_hdr = fsp_blob; + + if (!looks_like_fsp_header(raw_hdr)) + return CB_ERR; + + hdr->revision = read8(raw_hdr + 11); + hdr->fsp_revision = read32(raw_hdr + 12); + memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id)); + hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0'; + hdr->image_size = read32(raw_hdr + 24); + hdr->image_base = read32(raw_hdr + 28); + hdr->image_attribute = read32(raw_hdr + 32); + hdr->cfg_region_offset = read32(raw_hdr + 36); + hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->notify_phase_entry_offset = read32(raw_hdr + 56); + hdr->memory_init_entry_offset = read32(raw_hdr + 60); + hdr->silicon_init_entry_offset = read32(raw_hdr + 68); + + return CB_SUCCESS; +} + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n", + hdr->revision, hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + + if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPM) { + printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", + hdr->memory_init_entry_offset); + } + + if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPS) { + printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", + hdr->silicon_init_entry_offset); + printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n", + hdr->notify_phase_entry_offset); + } + +} + +enum cb_err fsp_load_binary(struct fsp_header *hdr, + const char *name, + struct range_entry *range) +{ + struct cbfsf file_desc; + struct region_device file_data; + void *membase; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); + return CB_ERR; + } + + cbfs_file_data(&file_data, &file_desc); + + /* Map just enough of the file to be able to parse the header. */ + membase = rdev_mmap(&file_data, FSP_HDR_OFFSET, FSP_HDR_LEN); + if (fsp_identify(hdr, membase) != CB_SUCCESS) { + printk(BIOS_ERR, "%s did not have a valid FSP header\n", name); + return CB_ERR; + } + + fsp_print_header_info(hdr); + + /* Check if size specified in the header matches the cbfs file size */ + if (region_device_sz(&file_data) < hdr->image_size) { + printk(BIOS_ERR, "%s size bigger than cbfs file.\n", name); + return CB_ERR; + } + + /* Check if the binary load address is within expected range */ + if (range_entry_base(range) > hdr->image_base || + range_entry_end(range) <= hdr->image_base + hdr->image_size) { + printk(BIOS_ERR, "%s is outside of allowed range\n", name); + return CB_ERR; + } + + /* Load binary into memory. */ + if (rdev_readat(&file_data, (void *)hdr->image_base, 0, hdr->image_size) < 0) + return CB_ERR; + + return CB_SUCCESS; +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add coreboot<->FSP header files
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13796 -gerrit commit 1c19ad0f528e9138fbed14efaa287008c7bc0d0c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Mar 1 16:25:38 2016 -0800 drivers/intel/fsp2_0: Add coreboot<->FSP header files This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/fsp2_0/Kconfig | 6 ++ src/drivers/intel/fsp2_0/Makefile.inc | 11 +++ src/drivers/intel/fsp2_0/include/fsp/api.h | 103 +++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/info_header.h | 70 ++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 42 +++++++++ 7 files changed, 234 insertions(+) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 19986f4..e5525d8 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -14,5 +14,6 @@ ## source src/drivers/intel/fsp1_1/Kconfig +source src/drivers/intel/fsp2_0/Kconfig source src/drivers/intel/gma/Kconfig source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index e54f07b..67c1163 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += gma subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 +subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig new file mode 100644 index 0000000..19e04f7 --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -0,0 +1,6 @@ +config PLATFORM_USES_FSP2_0 + bool + help + Include FSP 2.0 wrappers and functionality + + diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc new file mode 100644 index 0000000..61faefa --- /dev/null +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -0,0 +1,11 @@ +romstage-y += hand_off_block.c +romstage-y += util.c +romstage-y += memory_init.c + +ramstage-y += graphics.c +ramstage-y += hand_off_block.c +ramstage-y += notify.c +ramstage-y += silicon_init.c +ramstage-y += util.c + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h new file mode 100644 index 0000000..0d45df3 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_API_H_ +#define _FSP2_0_API_H_ + +#include <stddef.h> +#include <memrange.h> +#include <fsp/info_header.h> + +enum fsp_status { + FSP_SUCCESS = 0x00000000, + FSP_INVALID_PARAMETER = 0x80000002, + FSP_UNSUPPORTED = 0x80000003, + FSP_NOT_READY = 0x80000006, + FSP_DEVICE_ERROR = 0x80000007, + FSP_OUT_OF_RESOURCES = 0x80000009, + FSP_VOLUME_CORRUPTED = 0x8000000a, + FSP_NOT_FOUND = 0x8000000a, + FSP_TIMEOUT = 0x80000012, + FSP_ABORTED = 0x80000015, + FSP_INCOMPATIBLE_VERSION = 0x80000010, + FSP_SECURITY_VIOLATION = 0x8000001a, + FSP_CRC_ERROR = 0x8000001b, +}; + +enum fsp_notify_phase { + AFTER_PCI_ENUM = 0x20, + READY_TO_BOOT = 0x40 +}; + + +/* Opaque structures. These are platform-specific. */ +struct FSP_M_CONFIG; +struct FSP_S_CONFIG; + +/* Main FSP stages */ +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r); +enum fsp_status fsp_silicon_init(struct range_entry *r); +enum fsp_status fsp_notify(enum fsp_notify_phase phase); + +/* Callbacks for updating stage-specific parameters */ +void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd, + struct FSP_M_CONFIG *mcfg); +void platform_fsp_silicon_init_params_cb(struct FSP_S_CONFIG *silupd); + +/* + * # DOCUMENTATION: + * + * This file defines the interface between coreboot and the FSP 2.0 wrapper + * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry + * points and map 1:1 to the FSP entry points of the same name. + * + * ### fsp_memory_init(): + * - hob_list: retuns a pointer to the HOB storage area created by FSP + * - r: memory range that the binary is allowed to be loaded into + * + * This function is responsible for loading and executing the memory + * initialization code from the FSP-M binary. It expects this binary to reside + * in cbfs as FSP_M_FILE. + * + * The function takes one parameter, which is described below, but does not + * take in memory parameters as an argument. The memory parameters can be filled + * in with platform_fsp_memory_init_params_cb(). This is a callback symbol + * that fsp_memory_init() will call. The platform must provide this symbol. + * + * FSP returns information about the memory layout in a series of structures + * called hand-off-blocks (HOB). The "hob_list" output parameter will point to + * the start of the HOB list. The fsp reserved region will also be described by + * one of the HOBs. For more information on parsing these structures, see + * fsp/util.h + * + * + * ### fsp_silicon_init(): + * - r: memory range that the binary is allowed to be loaded into + * + * This function is responsible for loading and executing the silicon + * initialization code from the FSP-S binary. It expects this binary to reside + * in cbfs as FSP_S_FILE. + * + * Like fsp_memory_init(), it provides a callback to fill in FSP-specific + * parameters, via platform_fsp_silicon_init_params_cb(). The platform must + * also provide this symbol. + * + * + * ### fsp_notify(): + * - phase: Which FSP notification phase + * + * This function is responsible for loading and executing the notify code from + * the FSP-S binary. It expects that fsp_silicon_init() has already been called + * succesfully, and that the FSP-S binary is still loaded into memory. + */ + +#endif /* _FSP2_0_API_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h new file mode 100644 index 0000000..0f25496 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_INFO_HEADER_H_ +#define _FSP2_0_INFO_HEADER_H_ + +#include <rules.h> +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#define FSP_HDR_OFFSET 0x94 +#define FSP_HDR_LEN 0x48 +#define FSP_HDR_SIGNATURE "FSPH" +#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28) +#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28) +#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28) + +struct fsp_header { + uint32_t fsp_revision; + size_t image_size; + uintptr_t image_base; + uint32_t image_attribute; + size_t cfg_region_offset; + size_t cfg_region_size; + size_t notify_phase_entry_offset; + size_t memory_init_entry_offset; + size_t silicon_init_entry_offset; + char image_id[sizeof(uint64_t) + 1]; + uint8_t revision; +}; + +struct fsp_upd_header { + uint64_t signature; + uint8_t revision; +}; + +struct fsp_m_arch_upd { + uint8_t revision; + uintptr_t nvs_buffer; + uintptr_t stack_base; + uint32_t stack_size; + uint32_t bootloader_tolumsz; + uint32_t boot_mode; +}; + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); +void fsp_print_header_info(const struct fsp_header *hdr); +void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); + +#if ENV_RAMSTAGE +/* + * This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains + * both SiliconInit and Notify APIs. When SiliconInit is loaded the + * header is saved so that when Notify is called we do not have to start + * header parsing again. + */ +extern struct fsp_header fsps_hdr; +#endif + +#endif /* _FSP2_0_INFO_HEADER_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h new file mode 100644 index 0000000..69e545e --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_UTIL_H_ +#define _FSP2_0_UTIL_H_ + +#include <boot/coreboot_tables.h> +#include <fsp/info_header.h> +#include <device/resource.h> +#include <memrange.h> + +/* + * Hand-off-block handling functions that depend on CBMEM, and thus can only + * be used after cbmem_initialize(). + */ +void fsp_save_hob_list(void *hob_list_ptr); +const void *fsp_get_hob_list(void); +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +/* + * Hand-off-block utilities which do not depend on CBMEM, but need to be passed + * the HOB list explicitly. + */ +void fsp_find_reserved_memory(struct resource *res, const void *hob_list); +void fsp_print_memory_resource_hobs(const void *hob_list); + +/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */ +enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name, + struct range_entry *r); +/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */ +uintptr_t fsp_load_vbt(void); + +#endif /* _FSP2_0_UTIL_H_ */

1 0

Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Add configuration for memory training
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13870 -gerrit commit 43f0d97fadef01b032007551e9c1c9c4572cd564 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Mar 1 17:03:23 2016 -0800 mainboard/intel/apollolake_rvp: Add configuration for memory training Pass memory training information to MemoryInit, so memory training can be completed. Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/romstage.c | 125 +++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 7cfef9f..c94c6a3 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1 +1,124 @@ -/* Nothing here yet, but this file is needed by the build system */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <fsp/api.h> +#include <fsp/FspmUpd.h> + +static const uint8_t swizzling_rvp1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static const uint8_t swizzling0_rvp2[] = { + 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1, + 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9, +}; + +static const uint8_t swizzling1_rvp2[] = { + 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4, + 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25, +}; + +static const uint8_t swizzling2_rvp2[] = { + 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18, + 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2, +}; + +static const uint8_t swizzling3_rvp2[] = { + 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19, + 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, +}; + +static void rvp1_fill_memory_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Profile = 33; + cfg->DIMM0SPDAddress = 0xa0; + cfg->DIMM1SPDAddress = 0xa4; + cfg->Ch0_RankEnable = 0; + cfg->Ch0_DeviceWidth = 0; + cfg->Ch0_DramDensity = 0; + cfg->Ch0_Option = 3; + cfg->Ch1_RankEnable = 0; + cfg->Ch1_DeviceWidth = 0; + cfg->Ch1_DramDensity = 0; + cfg->Ch1_Option = 3; + cfg->Ch2_RankEnable = 0; + cfg->Ch2_DeviceWidth = 0; + cfg->Ch2_DramDensity = 0; + cfg->Ch2_Option = 3; + cfg->Ch3_RankEnable = 0; + cfg->Ch3_DeviceWidth = 0; + cfg->Ch3_DramDensity = 0; + cfg->Ch3_Option = 3; + memcpy(cfg->Ch0_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); +} + +static void rvp2_fill_memory_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Profile = 5; + cfg->DIMM0SPDAddress = 0; + cfg->DIMM1SPDAddress = 0; + cfg->Ch0_RankEnable = 3; + cfg->Ch0_DeviceWidth = 2; + cfg->Ch0_DramDensity = 0; + cfg->Ch0_Option = 3; + cfg->Ch1_RankEnable = 3; + cfg->Ch1_DeviceWidth = 2; + cfg->Ch1_DramDensity = 0; + cfg->Ch1_Option = 3; + cfg->Ch2_RankEnable = 3; + cfg->Ch2_DeviceWidth = 2; + cfg->Ch2_DramDensity = 0; + cfg->Ch2_Option = 3; + cfg->Ch3_RankEnable = 3; + cfg->Ch3_DeviceWidth = 2; + cfg->Ch3_DramDensity = 0; + cfg->Ch3_Option = 3; + memcpy(cfg->Ch0_Bit_swizzling, swizzling0_rvp2, + sizeof(swizzling0_rvp2)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling1_rvp2, + sizeof(swizzling1_rvp2)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling2_rvp2, + sizeof(swizzling2_rvp2)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling3_rvp2, + sizeof(swizzling3_rvp2)); +} + +void mainboard_memory_init_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Package = 0; + cfg->MemoryDown = 1; + cfg->DDR3LPageSize = 0; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0; + cfg->SliceHashMask = 0; + cfg->InterleavedMode = 0; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 0; + cfg->RmtMode = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) + rvp1_fill_memory_params(cfg); + else + rvp2_fill_memory_params(cfg); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add hand-off-block parsers
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13801 -gerrit commit 546b4684989491248c7270716158860c8684eb8f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Feb 25 14:20:38 2016 -0800 drivers/intel/fsp2_0: Add hand-off-block parsers FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 294 ++++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c new file mode 100644 index 0000000..3bc33af --- /dev/null +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -0,0 +1,294 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <fsp/util.h> +#include <inttypes.h> +#include <lib.h> +#include <string.h> + +#define HOB_HEADER_LEN 8 + +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + +static const char *resource_names[] = { + [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY", + [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO", + [EFI_RESOURCE_IO] = "IO", + [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE", + [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT", + [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED", + [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ +static const uint8_t uuid_owner_bootloader_tolum[16] = { + 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, +}; + +static const uint8_t uuid_owner_fsp[16] = { + 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43, + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, +}; + +static const uint8_t uuid_owner_tseg[16] = { + 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49, + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 +}; + +static const uint8_t empty_uuid[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const struct uuid_name_map { + const void *uuid; + const char *name; +} uuid_names[] = { + { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, + { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, + { uuid_owner_tseg, "TSEG" }, +}; + +static const char *resource_name(enum resource_type type) +{ + if (type >= ARRAY_SIZE(resource_names)) + return "UNKNOWN"; + return resource_names[type]; +} + +/* + * Utilities for walking HOBs + */ + +static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +{ + return !memcmp(uuid1, uuid2, 16); +} + +static const char *uuid_name(const uint8_t uuid[16]) +{ + size_t i; + const struct uuid_name_map *owner_entry; + + for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { + owner_entry = uuid_names + i; + if (uuid_compare(uuid, owner_entry->uuid)) + return owner_entry->name; + } + return "UNKNOWN"; +} + +static const struct hob_header *next_hob(const struct hob_header *parent) +{ + union { + const struct hob_header *hob; + uintptr_t addr; + } hob_walker; + + hob_walker.hob = parent; + hob_walker.addr += parent->length; + return hob_walker.hob; +} + +static const void *hob_header_to_struct(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN; + return hob_walker.hob_descr; +} + +static const void *hob_header_to_extension_hob(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */ + return hob_walker.hob_descr; +} + +static const +struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +{ + return hob_header_to_struct(hob); +} + +/* + * Utilities for locating and identifying HOBs + */ + +void fsp_save_hob_list(void *hob_list_ptr) +{ + void **cbmem_loc; + cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr)); + *cbmem_loc = hob_list_ptr; +} + +const void *fsp_get_hob_list(void) +{ + void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); + + return (list_loc) ? (*list_loc) : NULL; +} + +static const +struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, + const uint8_t uuid[16]) +{ + const struct hob_resource *res; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = hob_header_to_resource(hob); + if (uuid_compare(res->owner_guid, uuid)) + return res; + } + return NULL; +} + +void fsp_find_reserved_memory(struct resource *res, const void *hob_list) +{ + const struct hob_resource *fsp_mem; + + memset(res, 0, sizeof(*res)); + + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + + if (!fsp_mem) { + return; + } + + res->base = fsp_mem->addr; + res->size = fsp_mem->length; +} + +/* + * Utilities for printing HOB information + */ + +static void print_guid(const void *base) +{ + uint32_t big; + uint16_t mid[2]; + + const uint8_t *id = base; + big = read32(id + 0); + mid[0] = read16(id + 4); + mid[1] = read16(id + 6); + + printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + big, mid[0], mid[1], + id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); +} + +static void print_resource_descriptor(const void *base) +{ + const struct hob_resource *res; + + res = hob_header_to_resource(base); + + printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + resource_name(res->type), res->attribute_type); + printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + if (!uuid_compare(res->owner_guid, empty_uuid)) { + printk(BIOS_DEBUG, "\tOwner GUID: "); + print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + } +} + + +void fsp_print_memory_resource_hobs(const void *hob_list) +{ + const struct hob_header *hob = hob_list; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) + print_resource_descriptor(hob); + } +} + +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) +{ + const uint8_t *hob_uuid; + const struct hob_header *hob = fsp_get_hob_list(); + + if (!hob) + return NULL; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_GUID_EXTENSION) + continue; + + hob_uuid = hob_header_to_struct(hob); + if (uuid_compare(hob_uuid, uuid)) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + } + + return NULL; +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add Notify Phase API
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13800 -gerrit commit 1a6d2e70262411ad37ad8d09e73eed5e5268029a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:19:07 2016 -0800 drivers/intel/fsp2_0: Add Notify Phase API This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/notify.c | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c new file mode 100644 index 0000000..820bd45 --- /dev/null +++ b/src/drivers/intel/fsp2_0/notify.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +enum fsp_status fsp_notify(enum fsp_notify_phase phase) +{ + fsp_notify_fn fspnotify; + struct fsp_notify_params notify_params = { .phase = phase }; + + if (!fsps_hdr.silicon_init_entry_offset) + return FSP_NOT_FOUND; + + fspnotify = (void*) (fsps_hdr.image_base + + fsps_hdr.notify_phase_entry_offset); + + printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + + return fspnotify(&notify_params); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add framebuffer graphics support
by Andrey Petrov 02 Mar '16

02 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13802 -gerrit commit ab01a063630f81ea64f61ff31005921917628951 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Feb 25 14:22:03 2016 -0800 drivers/intel/fsp2_0: Add framebuffer graphics support This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 105 ++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c new file mode 100644 index 0000000..1480179 --- /dev/null +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <fsp/util.h> + +enum pixel_format { + pixel_rgbx_8bpc = 0, + pixel_bgrx_8bpc = 1, + pixel_bitmask = 2, /* defined by <rgb>_mask values */ +}; + +static const uint8_t uuid_graphics_info[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +struct hob_graphics_info { + uint64_t framebuffer_base; + uint32_t framebuffer_size; + uint32_t version; + uint32_t horizontal_resolution; + uint32_t vertical_resolution; + uint32_t pixel_format; /* See enum pixel_format */ + uint32_t red_mask; + uint32_t green_mask; + uint32_t blue_mask; + uint32_t reserved_mask; + uint32_t pixels_per_scanline; +} __attribute__((packed)); + +struct pixel { + uint8_t pos; + uint8_t size; +}; + +static const struct fsp_framebuffer { + struct pixel red; + struct pixel green; + struct pixel blue; + struct pixel rsvd; +} fsp_framebuffer_format_map[] = { + [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, + [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, +}; + +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + size_t size; + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; + + ginfo = fsp_find_extension_hob_by_uuid(uuid_graphics_info, &size); + + if (!ginfo) { + printk(BIOS_ALERT, "Graphics hand-off block not found\n"); + return CB_ERR; + } + + if (ginfo->pixel_format > ARRAY_SIZE(fsp_framebuffer_format_map)) { + printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return CB_ERR; + } + + fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; + + framebuffer->physical_address = ginfo->framebuffer_base; + framebuffer->x_resolution = ginfo->horizontal_resolution; + framebuffer->y_resolution = ginfo->vertical_resolution; + framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; + framebuffer->bits_per_pixel = 32; + framebuffer->red_mask_pos = fbinfo->red.pos; + framebuffer->red_mask_size = fbinfo->red.size; + framebuffer->green_mask_pos = fbinfo->green.pos; + framebuffer->green_mask_size = fbinfo->green.size; + framebuffer->blue_mask_pos = fbinfo->blue.pos; + framebuffer->blue_mask_size = fbinfo->blue.size; + framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; + framebuffer->reserved_mask_size = fbinfo->rsvd.pos; + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); + return CB_SUCCESS; +} + +uintptr_t fsp_load_vbt(void) +{ + void *vbt; + + vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); + if (!vbt) + printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + + return (uintptr_t)vbt; +}

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coreboot-gerrit March 2016