coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: buildgcc: Update coreboot's IASL version to 20160212
by Martin Roth 04 Mar '16

04 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12817 -gerrit commit 955e6c186293b08bf69bab63d24b5521424251cf Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Dec 30 15:10:13 2015 -0700 buildgcc: Update coreboot's IASL version to 20160212 Update IASL from 20150619 to 20160212 See release notes at acpica.org Change-Id: Ic7e7b3956378ad611069e984d5a59c78e4cb08b1 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- .../patches/acpica-unix2-20150619_iasl.patch | 12 ---------- .../patches/acpica-unix2-20160212_iasl.patch | 27 ++++++++++++++++++++++ .../sum/acpica-unix2-20160212.tar.gz.cksum | 1 + 4 files changed, 29 insertions(+), 13 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index df9ac4a..05f9846 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ GCC_VERSION=5.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.25 GDB_VERSION=7.9.1 -IASL_VERSION=20150619 +IASL_VERSION=20160212 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch b/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch deleted file mode 100644 index 2c754c9..0000000 --- a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN acpica-unix-20150619/source/compiler/asloptions.c acpica-unix-20150619/source/compiler/asloptions.c ---- acpica-unix2-20150619/source/compiler/asloptions.c 2015-06-19 08:56:19.000000000 -0600 -+++ acpica-unix2-20150619/source/compiler/asloptions.c 2015-12-08 10:44:58.816669240 -0700 -@@ -717,6 +717,7 @@ - case '^': - - printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); -+ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); - exit (0); - - case 'a': - diff --git a/util/crossgcc/patches/acpica-unix2-20160212_iasl.patch b/util/crossgcc/patches/acpica-unix2-20160212_iasl.patch new file mode 100644 index 0000000..63c2958 --- /dev/null +++ b/util/crossgcc/patches/acpica-unix2-20160212_iasl.patch @@ -0,0 +1,27 @@ +Add coreboot toolchain version string +--- acpica-unix2-20160212/source/compiler/asloptions.c ++++ acpica-unix2-20160212/source/compiler/asloptions.c +@@ -169,6 +169,7 @@ + if (argc < 2) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + Usage (); + exit (1); + } +@@ -199,6 +200,7 @@ + if (Gbl_DoSignon) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + if (Gbl_IgnoreErrors) + { + printf ("Ignoring all errors, forcing AML file generation\n\n"); +@@ -743,6 +745,7 @@ + case '^': + + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + exit (0); + + case 'a': diff --git a/util/crossgcc/sum/acpica-unix2-20160212.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160212.tar.gz.cksum new file mode 100644 index 0000000..77f73e7 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20160212.tar.gz.cksum @@ -0,0 +1 @@ +9b4ceb8562952c16bfb70c567429509504f388b8 tarballs/acpica-unix2-20160212.tar.gz

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Patch set updated for coreboot: toolchain.inc: test IASL by version string instead of number
by Martin Roth 04 Mar '16

04 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12847 -gerrit commit 6240d9930e3411afc611da4b32f479df69a7e85a Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 5 16:14:12 2016 -0700 toolchain.inc: test IASL by version string instead of number Test that the coreboot toolchain version of IASL is being used by looking for the string 'coreboot toolchain' instead of a specific version number. While this may cause people to have to rebuild their toolchains again now, it helps to prevent toolchain failures when bisecting in the future. Change-Id: I9913eeae8f29ddc3ec8c70077c05d898595eb283 Signed-off-by: Martin Roth <martinroth(a)google.com> --- toolchain.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index 2289b78..c891193 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -174,7 +174,7 @@ $(foreach arch,$(sort $(foreach stage,\ # If iasl doesn't match the current coreboot version, fail the test # TODO: Figure out if iasl is even needed for the build. $(if $(shell if [ -n "$(IASL)" ]; then \ - $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || \ + $(IASL) -v 2>&1 | grep -q "coreboot toolchain" || \ echo not-coreboot; else echo not-coreboot; fi), \ $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1)\ $(warning The coreboot toolchain version of iasl \

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Patch set updated for coreboot: BuildSystem: Add Memtest86+ as a secondary payload
by Martin Roth 04 Mar '16

04 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13858 -gerrit commit 6dbca6030e6e77db6010f346a8dede6c49b3404b Author: Martin Roth <martinroth(a)google.com> Date: Sun Feb 28 15:56:27 2016 -0800 BuildSystem: Add Memtest86+ as a secondary payload This allows memtest86+ to be added to CBFS as a 'secondary' payload on x86 systems, to be loaded by the main payload if desired. Selecting this option, which defaults to no, builds the memtest86+ payload and adds it to CBFS as `img/memtest` which can then be loaded by for example SeaBIOS or GRUB. Change-Id: Iecf876aaf588ba1df7abdf6668cb26f089bf5f42 Signed-off-by: Martin Roth <martinroth(a)google.com> --- .gitignore | 1 + payloads/Kconfig | 8 ++++++ payloads/external/Makefile.inc | 19 +++++++++++++ payloads/external/Memtest86Plus/Makefile.inc | 42 ++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/.gitignore b/.gitignore index 581c4a4..7b3797f 100644 --- a/.gitignore +++ b/.gitignore @@ -12,6 +12,7 @@ payloads/external/FILO/filo/ payloads/external/GRUB2/grub2/ payloads/external/SeaBIOS/seabios/ payloads/external/U-Boot/u-boot/ +payloads/external/Memtest86Plus/memtest86plus/ util/crossgcc/acpica-unix-*/ util/crossgcc/binutils-*/ util/crossgcc/build-*BINUTILS/ diff --git a/payloads/Kconfig b/payloads/Kconfig index 01bd216..6ae2ecd 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -67,4 +67,12 @@ config COREINFO_SECONDARY_PAYLOAD coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads. +config MEMTEST_SECONDARY_PAYLOAD + bool "Load Memtest86+ as a secondary payload" + default n + depends on ARCH_X86 && !PAYLOAD_NONE + help + Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB, + or any other payload that can load additional payloads. + endmenu diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 6a76020..557de2a 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -82,3 +82,22 @@ payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(top)/$(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot -f Makefile.inc \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) + +cbfs-files-$(CONFIG_MEMTEST_SECONDARY_PAYLOAD) += img/memtest +img/memtest-file := payloads/external/Memtest86Plus/memtest86plus/memtest +img/memtest-type := payload + +ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) + MEMTEST_SERIAL_OPTIONS=SERIAL_CONSOLE_DEFAULT=1 \ + SERIAL_TTY=$(CONFIG_UART_FOR_CONSOLE) \ + SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD) +endif + +payloads/external/Memtest86Plus/memtest86plus/memtest: $(top)/$(DOTCONFIG) + $(MAKE) -C payloads/external/Memtest86Plus -f Makefile.inc all \ + CC="$(CC_x86_32)" \ + LD="$(LD_x86_32)" \ + OBJCOPY="$(OBJCOPY_x86_32)" \ + AS="$(AS_x86_32)" \ + $(MEMTEST_SERIAL_OPTIONS) \ + MFLAGS= MAKEFLAGS= diff --git a/payloads/external/Memtest86Plus/Makefile.inc b/payloads/external/Memtest86Plus/Makefile.inc new file mode 100644 index 0000000..ceb1f5c --- /dev/null +++ b/payloads/external/Memtest86Plus/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +project_name=Memtest86+ +project_dir=$(shell pwd)/memtest86plus +project_git_repo=https://review.coreboot.org/memtest86plus + +all: build + +$(project_dir): + echo " Cloning $(project_name) from Git" + git clone $(project_git_repo) $(project_dir) + +fetch: $(project_dir) + cd $(project_dir); \ + test -e '.git' && \ + git fetch && \ + git checkout origin/master + +build: fetch + echo " MAKE $(project_name)" + $(MAKE) -C $(project_dir) all + +clean: + test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0 + +distclean: + rm -rf $(project_dir) + +.PHONY: all build fetch clean distclean

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Patch merged into coreboot/master: util/futility: trivial - Add distclean target
by gerrit＠coreboot.org 04 Mar '16

04 Mar '16

the following patch was just integrated into master: commit ca55f0a0eaaf92e75345e22791e37af0cf7034f4 Author: Martin Roth <martinroth(a)google.com> Date: Thu Mar 3 12:11:47 2016 -0700 util/futility: trivial - Add distclean target The what-jenkins-does build runs distclean when building the utilities. It doesn't fail the build if distclean fails, but it generates a scary warning. Change-Id: Iac90958951976ed326a89ef2b5f2d9f17f9f2d6b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13888 for details. -gerrit

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Patch set updated for coreboot: tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabled
by Martin Roth 04 Mar '16

04 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13890 -gerrit commit 6ce5a8384321da7c80cb89b437b095dbc33440c4 Author: Martin Roth <martinroth(a)google.com> Date: Thu Mar 3 16:20:53 2016 -0700 tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabled If the TPM code isn't getting built in, the Kconfig symbol CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist. This ends up creating an invalid operating region in the ACPI tables, causing a bluescreen in windows. This should fix this issue: https://ticket.coreboot.org/issues/35 "commit 85a255fb (acpi/tpm: Gracefully handle missing TPM module) breaks Windows" Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/pc80/tpm/acpi/tpm.asl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index de25114..090bf4c 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -15,6 +15,8 @@ /* Trusted Platform Module */ +#if CONFIG_LPC_TPM + Device (TPM) { Name (_HID, EISAID ("PNP0C31")) @@ -41,7 +43,7 @@ Device (TPM) Method (_STA, 0) { -#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE +#if !CONFIG_TPM_DEACTIVATE If (LAnd (LGreater (DVID, 0), LLess (DVID, 0xffffffff))) { Return (0xf) } Else { @@ -213,3 +215,5 @@ Device (TPM) Return (Buffer (1) { 0 }) } } + +#endif /* CONFIG_LPC_TPM */

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Patch set updated for coreboot: sandybridge/gma_lvds: support both Sandy&Ivy on one board
by Iru Cai 04 Mar '16

04 Mar '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12087 -gerrit commit 2af1e17bbe2c75cdf08540aa4bd712039240fde6 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sun Oct 18 23:40:34 2015 +0800 sandybridge/gma_lvds: support both Sandy&Ivy on one board Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. It also merges the {SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 --- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/lenovo/t420s/Kconfig | 2 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/northbridge/intel/sandybridge/Kconfig | 7 +------ src/northbridge/intel/sandybridge/Makefile.inc | 4 ++-- src/northbridge/intel/sandybridge/gma.h | 2 ++ src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 4 ++-- src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c | 5 +++++ util/autoport/sandybridge.go | 2 +- 13 files changed, 20 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 0e23794..197099e 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select IVYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index ce81af7..dc279027 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index cec1b14..4e55eda 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select IVYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 66a5c64..d5cee9e 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f3b378a..257621f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select IVYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index fe25a9e..d30cbdc 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index f644024..3db0338 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select IVYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index f435f85..9b90f36 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -51,12 +51,7 @@ config CACHE_MRC_SIZE_KB int default 512 -config IVYBRIDGE_LVDS - def_bool n - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG - -config SANDYBRIDGE_LVDS +config SANDYBRIDGE_IVYBRIDGE_LVDS def_bool n select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a58d9b1..4a7a854 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -18,8 +18,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDG ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c -ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c +ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c +ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 0832468..534b42e 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -117,5 +117,7 @@ struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); +int i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 pio, u8 *mmio, u32 lfb); #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1d7611f..f6818dd 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -153,8 +153,8 @@ static void enable_port(u8 *mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 piobase, u8 *mmio, u32 lfb) +int i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u8 *mmio, u32 lfb) { int i; u8 edid_data[128]; diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index e18f146..3b4b64c 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -24,6 +24,7 @@ #include <drivers/intel/gma/i915.h> #include "gma.h" #include "chip.h" +#include "sandybridge.h" #include <pc80/vga.h> #include <pc80/vga_io.h> #include <device/pci_def.h> @@ -142,6 +143,10 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) return 0; + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + return i915lightup_ivy(info, physbase, piobase, mmio, lfb); + } + write32(mmio + 0x00070080, 0x00000000); write32(mmio + DSPCNTR(0), 0x00000000); write32(mmio + 0x00071180, 0x00000000); diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 4ef6609..86142e8 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -110,7 +110,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { PutPCIDev(addr, "Host bridge") /* FIXME:XX some configs are unsupported. */ - KconfigBool[i.variant+"BRIDGE_LVDS"] = true + KconfigBool["SANDYBRIDGE_IVYBRIDGE_LVDS"] = true KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true

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New patch to review for coreboot: Hide EC_GOOGLE_CHROMEEC_SPI_BUS.
by Vladimir Serbinenko 04 Mar '16

04 Mar '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13906 -gerrit commit 982cfeae45214956e26df9ef64e657bf4e27af3a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Mar 4 09:31:14 2016 +0100 Hide EC_GOOGLE_CHROMEEC_SPI_BUS. It's mobo architecture, not a user-adjustable setting. Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/google/chromeec/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 59a9781..2e4affc 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -60,7 +60,7 @@ config EC_GOOGLE_CHROMEEC_SPI config EC_GOOGLE_CHROMEEC_SPI_BUS depends on EC_GOOGLE_CHROMEEC_SPI - hex "SPI bus for Google's Chrome EC" + hex config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US depends on EC_GOOGLE_CHROMEEC_SPI

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New patch to review for coreboot: lz4_wrapper: Use __asm__ rather than asm.
by Vladimir Serbinenko 04 Mar '16

04 Mar '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13905 -gerrit commit c4e7e9074d770cb4f2a537292de4e40d458c8f90 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Mar 4 09:29:50 2016 +0100 lz4_wrapper: Use __asm__ rather than asm. __asm__ is more robust to compilation flags. Change-Id: Ic7ca6e38ddd439dcfc4a62ef272ecea62416b4be Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/commonlib/lz4_wrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index bb59f28..772f791 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -54,7 +54,7 @@ static void LZ4_copy8(void *dst, const void *src) ((uint8_t *)dst)[i] = ((uint8_t *)src)[i]; #else uint32_t x0, x1; - asm volatile ( + __asm__ volatile ( "ldr %[x0], [%[src]]\n\t" "ldr %[x1], [%[src], #4]\n\t" "str %[x0], [%[dst]]\n\t"

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New patch to review for coreboot: Kconfig: hide useless options on ARM.
by Vladimir Serbinenko 04 Mar '16

04 Mar '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13904 -gerrit commit cb781012a3445053798f2c487a9cede9cdcb5d36 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Mar 4 09:20:20 2016 +0100 Kconfig: hide useless options on ARM. Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/Kconfig | 1 + src/console/Kconfig | 5 +++++ src/device/Kconfig | 2 ++ src/drivers/sil/3114/Kconfig | 1 + 4 files changed, 9 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 2257cb6..a90b04e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -155,6 +155,7 @@ config ID_SECTION_OFFSET config COMPILE_IN_DSDT bool "compile in DSDT and use that over DSDT in CBFS" + depends on HAVE_ACPI_TABLES default n # 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. diff --git a/src/console/Kconfig b/src/console/Kconfig index 847d17e..90fb426 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -133,6 +133,7 @@ endif # CONSOLE_SERIAL config SPKMODEM bool "spkmodem (console on speaker) console output" default n + depends on ARCH_X86 help Send coreboot debug output through speaker @@ -150,12 +151,14 @@ config CONSOLE_USB config ONBOARD_VGA_IS_PRIMARY bool "Use onboard VGA as primary video device" default n + depends on PCI help If not selected, the last adapter found will be used. config CONSOLE_NE2K bool "Network console over NE2000 compatible Ethernet adapter" default n + depends on PCI help Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP @@ -357,8 +360,10 @@ config POST_DEVICE_NONE bool "None" config POST_DEVICE_LPC bool "LPC" + depends on PCI config POST_DEVICE_PCI_PCIE bool "PCI/PCIe" + depends on PCI endchoice config POST_IO diff --git a/src/device/Kconfig b/src/device/Kconfig index 70a362f..d156d36 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -303,6 +303,7 @@ config SUBSYSTEM_DEVICE_ID config VGA_BIOS bool "Add a VGA BIOS image" + depends on ARCH_X86 help Select this option if you have a VGA BIOS image that you would like to add to your ROM. @@ -352,6 +353,7 @@ config MBI_FILE config PXE_ROM bool "Add a PXE ROM image" + depends on ARCH_X86 help Select this option if you have a PXE ROM image that you would like to add to your ROM. diff --git a/src/drivers/sil/3114/Kconfig b/src/drivers/sil/3114/Kconfig index 25bb202..151636c 100644 --- a/src/drivers/sil/3114/Kconfig +++ b/src/drivers/sil/3114/Kconfig @@ -1,6 +1,7 @@ config DRIVERS_SIL_3114 bool "Silicon Image SIL3114" default n + depends on PCI help It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it.

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Patch set updated for coreboot: nb/intel/sandybridge/gma_lvds: support both Sandy&Ivy on one board
by Iru Cai 04 Mar '16

04 Mar '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12087 -gerrit commit 83f7f52b615c02caafb1fcbd28793c4918ad6536 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sun Oct 18 23:40:34 2015 +0800 nb/intel/sandybridge/gma_lvds: support both Sandy&Ivy on one board Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 --- src/northbridge/intel/sandybridge/Makefile.inc | 2 ++ src/northbridge/intel/sandybridge/gma.h | 2 ++ src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 4 ++-- src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c | 5 +++++ 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a58d9b1..e551728 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -18,8 +18,10 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDG ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c +ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c +ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 0832468..534b42e 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -117,5 +117,7 @@ struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); +int i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 pio, u8 *mmio, u32 lfb); #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1d7611f..f6818dd 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -153,8 +153,8 @@ static void enable_port(u8 *mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 piobase, u8 *mmio, u32 lfb) +int i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u8 *mmio, u32 lfb) { int i; u8 edid_data[128]; diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index e18f146..3b4b64c 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -24,6 +24,7 @@ #include <drivers/intel/gma/i915.h> #include "gma.h" #include "chip.h" +#include "sandybridge.h" #include <pc80/vga.h> #include <pc80/vga_io.h> #include <device/pci_def.h> @@ -142,6 +143,10 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) return 0; + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + return i915lightup_ivy(info, physbase, piobase, mmio, lfb); + } + write32(mmio + 0x00070080, 0x00000000); write32(mmio + DSPCNTR(0), 0x00000000); write32(mmio + 0x00071180, 0x00000000);

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coreboot-gerrit March 2016