coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch set updated for coreboot: drivers/intel/fsp2_0: Add SiliconInit API
by Andrey Petrov 05 Mar '16

05 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13799 -gerrit commit 5e32e293a75ee6d31c9761c66647c7e8e9294555 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:17:45 2016 -0800 drivers/intel/fsp2_0: Add SiliconInit API This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/silicon_init.c | 59 +++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c new file mode 100644 index 0000000..b9c16b0 --- /dev/null +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +struct fsp_header fsps_hdr; + +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); + +static enum fsp_status do_silicon_init(struct fsp_header *hdr) +{ + struct FSPS_UPD upd, *supd; + fsp_silicon_init_fn silicon_init; + enum fsp_status status; + + /* Our header we are compiled with is out of sync with the blob */ + if (hdr->cfg_region_size > sizeof(upd)) { + printk(BIOS_ERR, "FSPS UPD is bigger than the header.\n"); + return FSP_OUT_OF_RESOURCES; + } + + supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); + memcpy(&upd, supd, sizeof(upd)); + + /* Give SoC/mainboard a chance to populate entries */ + platform_fsp_silicon_init_params_cb(&upd); + + silicon_init = (void *) (hdr->image_base + + hdr->silicon_init_entry_offset); + + status = silicon_init(&upd); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + return status; +} + +enum fsp_status fsp_silicon_init(struct range_entry *range) +{ + /* Load FSP-S and save FSP header. We will need it for Notify */ + /* TODO: do not hardcode CBFS file names */ + if (fsp_load_binary(&fsps_hdr, "blobs/fsps.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_silicon_init(&fsps_hdr); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add MemoryInit API
by Andrey Petrov 05 Mar '16

05 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798 -gerrit commit 283b0619e3bc6659ad8042b2cfe99d1f15efa126 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:16:33 2016 -0800 drivers/intel/fsp2_0: Add MemoryInit API This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 11 ++-- src/drivers/intel/fsp2_0/memory_init.c | 88 ++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 7 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 0d45df3..6b11055 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -16,6 +16,8 @@ #include <stddef.h> #include <memrange.h> #include <fsp/info_header.h> +#include <fsp/FspmUpd.h> +#include <fsp/FspsUpd.h> enum fsp_status { FSP_SUCCESS = 0x00000000, @@ -39,19 +41,14 @@ enum fsp_notify_phase { }; -/* Opaque structures. These are platform-specific. */ -struct FSP_M_CONFIG; -struct FSP_S_CONFIG; - /* Main FSP stages */ enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r); enum fsp_status fsp_silicon_init(struct range_entry *r); enum fsp_status fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd, - struct FSP_M_CONFIG *mcfg); -void platform_fsp_silicon_init_params_cb(struct FSP_S_CONFIG *silupd); +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); /* * # DOCUMENTATION: diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c new file mode 100644 index 0000000..73a36cf --- /dev/null +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> +#include <fsp/FspmUpd.h> + +struct fsp_memory_init_params { + void *nvs_buffer; + void *raminit_upd; + void **hob_list; +} __attribute__ ((__packed__)); + +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (struct fsp_memory_init_params *); + +static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, + struct fsp_header *hdr) +{ + enum fsp_status status; + fsp_memory_init_fn fsp_raminit; + struct fsp_memory_init_params raminit_params; + struct FSPM_UPD fspm_upd, *upd; + + post_code(0x34); + + upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + + /* If blob has bigger UPD we are probably out of sync*/ + if (hdr->cfg_region_size > sizeof(fspm_upd)) { + printk(BIOS_ERR, "UPD size bigger than expected header size\n"); + return FSP_OUT_OF_RESOURCES; + } + + /* Copy the default values from the UPD area */ + memcpy(&fspm_upd, upd, sizeof(fspm_upd)); + + /* Get any board specific changes */ + raminit_params.nvs_buffer = NULL; + raminit_params.raminit_upd = &fspm_upd; + raminit_params.hob_list = hob_list_ptr; + + /* Give SoC and mainboard a chance to update the UPD */ + platform_fsp_memory_init_params_cb(&fspm_upd); + + /* Call FspMemoryInit */ + fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); + printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", raminit_params.raminit_upd); + printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_raminit(&raminit_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + return status; +} + +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range) +{ + struct fsp_header hdr; + + /* TODO: do not hardcode CBFS file names */ + if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_fsp_memory_init(hob_list, &hdr); +}

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Patch merged into coreboot/master: Hide EC_GOOGLE_CHROMEEC_SPI_BUS.
by gerrit＠coreboot.org 05 Mar '16

05 Mar '16

the following patch was just integrated into master: commit 42f42ff4501cf0ec345b7f9a3c850934e6f04c00 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Mar 4 09:31:14 2016 +0100 Hide EC_GOOGLE_CHROMEEC_SPI_BUS. It's mobo architecture, not a user-adjustable setting. Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: https://review.coreboot.org/13906 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13906 for details. -gerrit

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Patch merged into coreboot/master: lz4_wrapper: Use __asm__ rather than asm.
by gerrit＠coreboot.org 05 Mar '16

05 Mar '16

the following patch was just integrated into master: commit ca1b2d19a9ba4363fa0586c9d23602a712fc27ea Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Mar 4 09:29:50 2016 +0100 lz4_wrapper: Use __asm__ rather than asm. __asm__ is more robust to compilation flags. Change-Id: Ic7ca6e38ddd439dcfc4a62ef272ecea62416b4be Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: https://review.coreboot.org/13905 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/13905 for details. -gerrit

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Patch merged into coreboot/master: Kconfig: hide useless options on ARM.
by gerrit＠coreboot.org 05 Mar '16

05 Mar '16

the following patch was just integrated into master: commit d51a0896c6c0e995b6a60ee322e04d311bb4b031 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Mar 4 09:20:20 2016 +0100 Kconfig: hide useless options on ARM. Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13904 for details. -gerrit

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Patch set updated for coreboot: intel/fsp_baytrail: use 20K PU/PD for GPIO
by Ben Gardner 04 Mar '16

04 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13907 -gerrit commit ffda10dcd50472dec5e2144648d95f2e6301051d Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Mar 4 16:42:08 2016 -0600 intel/fsp_baytrail: use 20K PU/PD for GPIO The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs. The 10K and 40K values map to 'reserved'. This brings the code closer to the non-FSP baytrail. Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03 Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/include/soc/gpio.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index e1164a3..165443e 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -181,14 +181,14 @@ .is_gpio = 1 } #define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_MMIO, \ .is_gpio = 1 } #define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ @@ -197,7 +197,7 @@ /* Direct / dedicated IRQ input - pass signal directly to apic */ #define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } @@ -247,13 +247,13 @@ .pad_val = PAD_VAL_DEFAULT } /* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 10K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 10K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 10K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 10K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 10K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 10K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) +#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) +#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) +#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) +#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) +#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) +#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) +#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) /* ACPI GPIO routing. Assume everything is externally pulled and negative edge * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ @@ -292,9 +292,9 @@ /* Common default GPIO settings */ #define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_10K -#define GPIO_INPUT_PD GPIO_INPUT_PD_10K -#define GPIO_NC GPIO_INPUT_PU_10K +#define GPIO_INPUT_PU GPIO_INPUT_PU_20K +#define GPIO_INPUT_PD GPIO_INPUT_PD_20K +#define GPIO_NC GPIO_INPUT_PU_20K #define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */

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New patch to review for coreboot: intel/fsp_baytrail: use 20K PU/PD for GPIO
by Ben Gardner 04 Mar '16

04 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13907 -gerrit commit 2c06b590d7b101eea6d0120cdfb67cfb1cf2017b Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Mar 4 16:25:09 2016 -0600 intel/fsp_baytrail: use 20K PU/PD for GPIO The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs. The 10K and 40K values map to 'reserved'. This brings the code closer to the non-FSP baytrail. Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03 Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/include/soc/gpio.h | 42 +++++++++------------------ 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index e1164a3..e8e1fca 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -105,9 +105,7 @@ /* config0[10:9] - Pull str */ #define PAD_PU_2K (0 << 9) -#define PAD_PU_10K (1 << 9) #define PAD_PU_20K (2 << 9) -#define PAD_PU_40K (3 << 9) /* config0[8:7] - Pull assign */ #define PAD_PULL_DISABLE (0 << 7) @@ -152,20 +150,6 @@ #define PAD_VAL_DEFAULT PAD_VAL_INPUT /* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - #define GPIO_INPUT_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ @@ -181,14 +165,14 @@ .is_gpio = 1 } #define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_MMIO, \ .is_gpio = 1 } #define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ @@ -197,7 +181,7 @@ /* Direct / dedicated IRQ input - pass signal directly to apic */ #define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } @@ -247,13 +231,13 @@ .pad_val = PAD_VAL_DEFAULT } /* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 10K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 10K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 10K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 10K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 10K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 10K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) +#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) +#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) +#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) +#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) +#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) +#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) +#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) /* ACPI GPIO routing. Assume everything is externally pulled and negative edge * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ @@ -292,9 +276,9 @@ /* Common default GPIO settings */ #define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_10K -#define GPIO_INPUT_PD GPIO_INPUT_PD_10K -#define GPIO_NC GPIO_INPUT_PU_10K +#define GPIO_INPUT_PU GPIO_INPUT_PU_20K +#define GPIO_INPUT_PD GPIO_INPUT_PD_20K +#define GPIO_NC GPIO_INPUT_PU_20K #define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */

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Patch set updated for coreboot: arch/x86: Add common assembly code for stages that run in CAR
by Andrey Petrov 04 Mar '16

04 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13861 -gerrit commit cd5865118eb0689b247163f3011b516e06042802 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:37:15 2016 -0800 arch/x86: Add common assembly code for stages that run in CAR This adds a few assembly lines that are generic enough to be shared between romstage and verstage that are ran in CAR. The GDT reload is bypassed and the stack is reloaded with the CAR stack defined in car.ld. The entry point for all those stages is car_stage_entry(). Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/assembly_entry.S | 38 +++++++++++++++++++++++++++++++++++++- src/arch/x86/include/arch/cpu.h | 9 +++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 01e91b0..e4d166c 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. + * Copyright 2016 Google Inc. + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,8 @@ * GNU General Public License for more details. */ +#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) + /* This file assembles the start of the romstage program by the order of the * includes. Thus, it's extremely important that one pays very careful * attention to the order of the includes. */ @@ -31,3 +34,36 @@ * cache-as-ram setup files would be here. */ #include <generated/assembly.inc> + +#else + +/* + * This path is for stages that post bootblock when employing + * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc + * as all those settings are cached within the processor. In order to + * continue with C code execution one needs to set stack pointer and clear + * CAR_GLOBAL variables that are stage specific. + */ +.section ".text._start", "ax", @progbits +.global _start +_start: + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + jmp car_stage_entry + +/* This is here for linking purposes. */ +.weak car_stage_entry +car_stage_entry: +1: + jmp 1b +#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 408fa15..f50901f 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -239,4 +239,13 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) #define alwaysinline inline __attribute__((always_inline)) +#ifndef __ROMCC__ +/* + * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() + * is the symbol jumped to for each stage after bootblock using + * cache-as-ram. + */ +void asmlinkage car_stage_entry(void); +#endif + #endif /* ARCH_CPU_H */

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Patch set updated for coreboot: buildgcc: Update coreboot's IASL version to 20160212
by Martin Roth 04 Mar '16

04 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12817 -gerrit commit be601ba6b3313aecc9f7c009493f2bb3238b9731 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Dec 30 15:10:13 2015 -0700 buildgcc: Update coreboot's IASL version to 20160212 Update IASL from 20150619 to 20160212 See release notes at acpica.org Change-Id: Ic7e7b3956378ad611069e984d5a59c78e4cb08b1 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- .../patches/acpica-unix2-20150619_iasl.patch | 12 ---------- .../patches/acpica-unix2-20160212_iasl.patch | 27 ++++++++++++++++++++++ .../sum/acpica-unix2-20160212.tar.gz.cksum | 1 + 4 files changed, 29 insertions(+), 13 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index df9ac4a..05f9846 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ GCC_VERSION=5.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.25 GDB_VERSION=7.9.1 -IASL_VERSION=20150619 +IASL_VERSION=20160212 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch b/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch deleted file mode 100644 index 2c754c9..0000000 --- a/util/crossgcc/patches/acpica-unix2-20150619_iasl.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN acpica-unix-20150619/source/compiler/asloptions.c acpica-unix-20150619/source/compiler/asloptions.c ---- acpica-unix2-20150619/source/compiler/asloptions.c 2015-06-19 08:56:19.000000000 -0600 -+++ acpica-unix2-20150619/source/compiler/asloptions.c 2015-12-08 10:44:58.816669240 -0700 -@@ -717,6 +717,7 @@ - case '^': - - printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); -+ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); - exit (0); - - case 'a': - diff --git a/util/crossgcc/patches/acpica-unix2-20160212_iasl.patch b/util/crossgcc/patches/acpica-unix2-20160212_iasl.patch new file mode 100644 index 0000000..63c2958 --- /dev/null +++ b/util/crossgcc/patches/acpica-unix2-20160212_iasl.patch @@ -0,0 +1,27 @@ +Add coreboot toolchain version string +--- acpica-unix2-20160212/source/compiler/asloptions.c ++++ acpica-unix2-20160212/source/compiler/asloptions.c +@@ -169,6 +169,7 @@ + if (argc < 2) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + Usage (); + exit (1); + } +@@ -199,6 +200,7 @@ + if (Gbl_DoSignon) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + if (Gbl_IgnoreErrors) + { + printf ("Ignoring all errors, forcing AML file generation\n\n"); +@@ -743,6 +745,7 @@ + case '^': + + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + exit (0); + + case 'a': diff --git a/util/crossgcc/sum/acpica-unix2-20160212.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160212.tar.gz.cksum new file mode 100644 index 0000000..77f73e7 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20160212.tar.gz.cksum @@ -0,0 +1 @@ +9b4ceb8562952c16bfb70c567429509504f388b8 tarballs/acpica-unix2-20160212.tar.gz

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Patch merged into coreboot/master: toolchain.inc: test IASL by version string instead of number
by gerrit＠coreboot.org 04 Mar '16

04 Mar '16

the following patch was just integrated into master: commit ab8f923f5372baeacbf1d97c2a44446b0f9d0ddd Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 5 16:14:12 2016 -0700 toolchain.inc: test IASL by version string instead of number Test that the coreboot toolchain version of IASL is being used by looking for the string 'coreboot toolchain' instead of a specific version number. While this may cause people to have to rebuild their toolchains again now, it helps to prevent toolchain failures when bisecting in the future. Change-Id: I9913eeae8f29ddc3ec8c70077c05d898595eb283 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12847 for details. -gerrit

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coreboot-gerrit March 2016