coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: arch/x86: always use _start as entry symbol for all stages
by gerrit＠coreboot.org 04 Mar '16

04 Mar '16

the following patch was just integrated into master: commit 8198c678f7a7b1e3fbb44190903768397951e1f9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 15:26:10 2016 -0600 arch/x86: always use _start as entry symbol for all stages Instead of keeping track of all the combinations of entry points depending on the stage and other options just use _start. That way, there's no need to update the arch/header.ld for complicated cases as _start is always the entry point for a stage. Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13882 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13882 for details. -gerrit

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New patch to review for coreboot: soc/intel/quark: Add the UPD support for SiliconInit
by Leroy P Leahy 04 Mar '16

04 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13897 -gerrit commit c11a074ef6330fda127ae4e13456aaaaa4f57e0a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:52:25 2016 -0800 soc/intel/quark: Add the UPD support for SiliconInit Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 3e11225..eb326d7 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -54,3 +54,30 @@ struct chip_operations soc_intel_quark_ops = { .init = &chip_init, .enable_dev = chip_enable_dev, }; + +void soc_silicon_init_params(SILICON_INIT_UPD *params) +{ + struct soc_intel_quark_config *config; + device_t dev; + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_silicon_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Set the parameters for SiliconInit */ +// printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new) +{ + /* Display the parameters for SiliconInit */ +// printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); +}

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New patch to review for coreboot: soc/intel/quark: Set the UPD values for MemoryInit
by Leroy P Leahy 04 Mar '16

04 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13896 -gerrit commit e5fc9f55ce670758c6f65c4d296cd064ab77de1d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:30:48 2016 -0800 soc/intel/quark: Set the UPD values for MemoryInit Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 14 ++- src/soc/intel/quark/chip.h | 12 +- src/soc/intel/quark/include/soc/pci_devs.h | 5 + src/soc/intel/quark/romstage/romstage.c | 54 +++++++++ src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 139 +++++++++++----------- 5 files changed, 151 insertions(+), 73 deletions(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 52e019b..05edffc 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -16,6 +16,16 @@ chip soc/intel/quark + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdSmmTsegSize" = "0" # SMM Region size in MiB + + ############################################################ + # Enable the devices + ############################################################ + device domain 0 on # EDS Table 3 device pci 00.0 on end # 8086 0958 - Host Bridge @@ -27,8 +37,8 @@ chip soc/intel/quark device pci 14.5 on end # 8086 0936 - HSUART 1 device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0 device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 - device pci 15.0 off end # 8086 0935 - SPI controller 0 - device pci 15.1 off end # 8086 0935 - SPI controller 1 + device pci 15.0 on end # 8086 0935 - SPI controller 0 + device pci 15.1 on end # 8086 0935 - SPI controller 1 device pci 15.2 off end # 8086 0934 - I2C/GPIO controller device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0 device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1 diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 59c8793..fc9890f 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -19,11 +19,21 @@ #define _SOC_CHIP_H_ #include <stdint.h> +#include <fsp/util.h> #include <soc/pci_devs.h> #include <soc/pm.h> struct soc_intel_quark_config { - uint32_t junk; + /* + * MemoryInit: + * + * The following fields come from FspUpdVpd.h and are defined as PCDs + * for the FSP binary. Data for these fields comes from the board's + * devicetree.cb file which gets processed into static.c and then + * built into the coreboot image. The fields below contain retain + * the FSP PCD field name. + */ + UINT16 PcdSmmTsegSize; }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index d776e1e..4f577ce 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,6 +18,7 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ +#include <arch/io.h> #include <device/pci.h> #include <soc/QuarkNcSocId.h> @@ -31,4 +32,8 @@ # define HSUART1_DEV SIO1_DEV # define HSUART1_FUNC 5 +/* Platform Controller Unit */ +# define LPC_DEV_FUNC PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, \ + PCI_FUNCTION_NUMBER_QNC_LPC) + #endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 731e529..a089185 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -13,9 +13,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ #include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> +#include "../chip.h" #include <device/pci_def.h> #include <fsp/car.h> #include <fsp/util.h> @@ -47,3 +50,54 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + char *pdat_file; + size_t pdat_file_len; + const struct soc_intel_quark_config *config; + + /* Locate the pdat.bin file */ + pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW, + &pdat_file_len); + if (!pdat_file) { + printk(BIOS_DEBUG, + "Platform configuration file (pdat.bin) not found."); + pdat_file_len = 0; + } + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Set the parameters for MemoryInit */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); + upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->PcdSmmTsegSize : 0; + upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; + upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + fsp_display_upd_value("PcdSmmTsegSize", 2, + old->PcdSmmTsegSize, new->PcdSmmTsegSize); + fsp_display_upd_value("PcdPlatformDataBaseAddress", 4, + old->PcdPlatformDataBaseAddress, + new->PcdPlatformDataBaseAddress); + fsp_display_upd_value("PcdPlatformDataMaxLen", 4, + old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen); +} diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h index 2a11b20..b6b6cc4 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015-2016, Intel Corporation. All rights reserved. +Copyright (c) 2016, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,139 +33,138 @@ are permitted provided that the following conditions are met: #ifndef __FSPUPDVPD_H__ #define __FSPUPDVPD_H__ -#pragma pack(push, 1) +#pragma pack(1) + + +// +// TODO - Port to fit Quark SoC. +// #define MAX_CHANNELS_NUM 2 #define MAX_DIMMS_NUM 2 typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ } DIMM_INFO; typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; } CHANNEL_INFO; typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; } FSP_SMBIOS_MEMORY_INFO; -/** UPD data structure for FspMemoryInitApi -**/ -typedef struct { + +typedef struct { /** Offset 0x0020 **/ UINT64 Signature; - -/** Offset 0x0028 - Revision - Revision version of the MemoryInitUpd Region +/** Offset 0x0028 **/ UINT8 Revision; +/** Offset 0x0029 + Tseg Size + Size of SMRAM memory reserved. +**/ + UINT8 PcdSmmTsegSize; +/** Offset 0x002A +**/ + UINT32 PcdPlatformDataBaseAddress; +/** Offset 0x002E +**/ + UINT32 PcdPlatformDataMaxLen; +/** Offset 0x0032 +**/ + UINT8 ReservedMemoryInitUpd[14]; } MEMORY_INIT_UPD; -/** UPD data structure for FspSiliconInitApi -**/ typedef struct { - -/** Offset 0x0200 +/** Offset 0x0040 **/ UINT64 Signature; - -/** Offset 0x0208 - Revision - Revision version of the SiliconInitUpd Region +/** Offset 0x0048 **/ UINT8 Revision; +/** Offset 0x0049 +**/ + UINT8 ReservedSiliconInitUpd[183]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ #define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ #define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ -/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. -**/ -typedef struct { - +typedef struct _UPD_DATA_REGION { /** Offset 0x0000 **/ UINT64 Signature; - -/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +/** Offset 0x0008 **/ UINT8 Revision; - /** Offset 0x0009 **/ UINT8 ReservedUpd0[7]; - -/** Offset 0x0010 - MemoryInitUpdOffset - This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +/** Offset 0x0010 **/ UINT32 MemoryInitUpdOffset; - -/** Offset 0x0014 - SiliconInitUpdOffset - This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +/** Offset 0x0014 **/ UINT32 SiliconInitUpdOffset; - /** Offset 0x0018 **/ UINT64 ReservedUpd1; - /** Offset 0x0020 **/ MEMORY_INIT_UPD MemoryInitUpd; - -/** Offset 0x0200 +/** Offset 0x0040 **/ SILICON_INIT_UPD SiliconInitUpd; - -/** Offset 0x03FA - RegionTerminator - This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +/** Offset 0x0100 **/ - UINT16 RegionTerminator; + UINT16 PcdRegionTerminator; } UPD_DATA_REGION; -#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ -#define FSP_IMAGE_REV 0x00000000 /* 0.0 */ - -/** VPD data structure -**/ -typedef struct { +#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ +#define FSP_IMAGE_REV 0x00000000 +typedef struct _VPD_DATA_REGION { /** Offset 0x0000 **/ UINT64 PcdVpdRegionSign; - -/** Offset 0x0008 - PcdImageRevision - This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +/** Offset 0x0008 + PcdImageRevision **/ UINT32 PcdImageRevision; - -/** Offset 0x000C - PcdUpdRegionOffset - This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +/** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[16]; +/** Offset 0x0020 +**/ + UINT32 PcdFspReservedMemoryLength; } VPD_DATA_REGION; -#pragma pack(pop) +#pragma pack() #endif

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New patch to review for coreboot: soc/intel/quark: Split out MTRR support
by Leroy P Leahy 04 Mar '16

04 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13895 -gerrit commit 795d0a5c5b3f37f64c1a6b80cf0389f324c7e59b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 16:48:22 2016 -0800 soc/intel/quark: Split out MTRR support Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/mtrr.c | 201 ++++++++++++++++++++++++++++++ src/soc/intel/quark/romstage/romstage.c | 181 --------------------------- 3 files changed, 202 insertions(+), 181 deletions(-) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 4797266..fc7bd6a 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,6 +16,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-y += mtrr.c romstage-y += report_platform.c romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c new file mode 100644 index 0000000..a0313fb --- /dev/null +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <soc/intel/common/util.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +uint32_t mdr_read(void) +{ + return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); +} + +void mdr_write(uint32_t value) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); +} + +void mea_write(uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) +{ + uint32_t offset; + + /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ + if (index == MTRR_CAP_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; + else if (index == MTRR_DEF_TYPE_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; + else if (index == MTRR_FIX_64K_00000) + offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; + else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) + offset = ((index - MTRR_FIX_16K_80000) << 1) + + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; + else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) + offset = ((index - MTRR_FIX_4K_C0000) << 1) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) + offset = (index - MTRR_PHYS_BASE(0)) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else { + printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + die("Invalid MTRR index specified!\n"); + } + return offset; +} + +msr_t soc_mtrr_read(unsigned long index) +{ + uint32_t offset; + union { + uint64_t u64; + msr_t msr; + } value; + + /* Read the low 32-bits of the register */ + offset = mtrr_index_to_host_bridge_register_offset(index); + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + value.u64 = mdr_read(); + + /* For 64-bit registers, read the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + value.u64 |= mdr_read(); + } + return value.msr; +} + +void soc_mtrr_write(unsigned long index, msr_t msr) +{ + uint32_t offset; + union { + uint32_t u32[2]; + msr_t msr; + } value; + + /* Write the low 32-bits of the register */ + value.msr = msr; + offset = mtrr_index_to_host_bridge_register_offset(index); + mea_write(offset); + mdr_write(value.u32[0]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + + /* For 64-bit registers, write the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mdr_write(value.u32[1]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + } +} + +asmlinkage void *soc_set_mtrrs(void *top_of_stack) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + uint32_t mtrr_count; + uint32_t *mtrr_data; + uint32_t mtrr_reg; + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * top_of_stack --> +0: Number of variable MTRRs to clear + * + * This routine: + * * Clears all of the variable MTRRs + * * Initializes the variable MTRRs with the data passed in + * * Returns the new top of stack after removing all of the + * data passed in. + */ + + /* Clear all of the variable MTRRs (base and mask). */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_data = top_of_stack; + mtrr_count = (*mtrr_data++) * 2; + data.u64 = 0; + while (mtrr_count-- > 0) + soc_mtrr_write(mtrr_reg++, data.msr); + + /* Setup the specified variable MTRRs */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_count = *mtrr_data++; + while (mtrr_count-- > 0) { + data.u32[0] = *mtrr_data++; + data.u32[1] = *mtrr_data++; + soc_mtrr_write(mtrr_reg++, data.msr); /* Base */ + data.u32[0] = *mtrr_data++; + data.u32[1] = *mtrr_data++; + soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */ + } + + /* Remove setup_stack_and_mtrrs data and return the new top_of_stack */ + top_of_stack = mtrr_data; + return top_of_stack; +} + +asmlinkage void soc_enable_mtrrs(void) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + + /* Enable MTRR. */ + data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR); + data.u32[0] |= MTRR_DEF_TYPE_EN; + soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr); +} diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 28d0b03..731e529 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -16,8 +16,6 @@ #include <arch/early_variables.h> #include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <fsp/car.h> #include <fsp/util.h> @@ -49,182 +47,3 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } - -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, - (opcode << QNC_MCR_OP_OFFSET) - | ((uint32_t)port << QNC_MCR_PORT_OFFSET) - | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) - | QNC_MCR_BYTE_ENABLES); -} - -uint32_t mdr_read(void) -{ - return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); -} - -void mdr_write(uint32_t value) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); -} - -void mea_write(uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address - & QNC_MEA_MASK); -} - -static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) -{ - uint32_t offset; - - /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ - if (index == MTRR_CAP_MSR) - offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; - else if (index == MTRR_DEF_TYPE_MSR) - offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; - else if (index == MTRR_FIX_64K_00000) - offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; - else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) - offset = ((index - MTRR_FIX_16K_80000) << 1) - + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; - else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) - offset = ((index - MTRR_FIX_4K_C0000) << 1) - + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; - else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) - offset = (index - MTRR_PHYS_BASE(0)) - + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; - else { - printk(BIOS_DEBUG, "index: 0x%08lx\n", index); - die("Invalid MTRR index specified!\n"); - } - return offset; -} - -msr_t soc_mtrr_read(unsigned long index) -{ - uint32_t offset; - union { - uint64_t u64; - msr_t msr; - } value; - - /* Read the low 32-bits of the register */ - offset = mtrr_index_to_host_bridge_register_offset(index); - mea_write(offset); - mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); - value.u64 = mdr_read(); - - /* For 64-bit registers, read the upper 32-bits */ - if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) - && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { - offset += 1; - mea_write(offset); - mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, - offset); - value.u64 |= mdr_read(); - } - return value.msr; -} - -void soc_mtrr_write(unsigned long index, msr_t msr) -{ - uint32_t offset; - union { - uint32_t u32[2]; - msr_t msr; - } value; - - /* Write the low 32-bits of the register */ - value.msr = msr; - offset = mtrr_index_to_host_bridge_register_offset(index); - mea_write(offset); - mdr_write(value.u32[0]); - mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); - - /* For 64-bit registers, write the upper 32-bits */ - if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) - && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { - offset += 1; - mea_write(offset); - mdr_write(value.u32[1]); - mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, - offset); - } -} - -asmlinkage void *soc_set_mtrrs(void *top_of_stack) -{ - union { - uint32_t u32[2]; - uint64_t u64; - msr_t msr; - } data; - uint32_t mtrr_count; - uint32_t *mtrr_data; - uint32_t mtrr_reg; - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * top_of_stack --> +0: Number of variable MTRRs to clear - * - * This routine: - * * Clears all of the variable MTRRs - * * Initializes the variable MTRRs with the data passed in - * * Returns the new top of stack after removing all of the - * data passed in. - */ - - /* Clear all of the variable MTRRs (base and mask). */ - mtrr_reg = MTRR_PHYS_BASE(0); - mtrr_data = top_of_stack; - mtrr_count = (*mtrr_data++) * 2; - data.u64 = 0; - while (mtrr_count-- > 0) - soc_mtrr_write(mtrr_reg++, data.msr); - - /* Setup the specified variable MTRRs */ - mtrr_reg = MTRR_PHYS_BASE(0); - mtrr_count = *mtrr_data++; - while (mtrr_count-- > 0) { - data.u32[0] = *mtrr_data++; - data.u32[1] = *mtrr_data++; - soc_mtrr_write(mtrr_reg++, data.msr); /* Base */ - data.u32[0] = *mtrr_data++; - data.u32[1] = *mtrr_data++; - soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */ - } - - /* Remove setup_stack_and_mtrrs data and return the new top_of_stack */ - top_of_stack = mtrr_data; - return top_of_stack; -} - -asmlinkage void soc_enable_mtrrs(void) -{ - union { - uint32_t u32[2]; - uint64_t u64; - msr_t msr; - } data; - - /* Enable MTRR. */ - data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR); - data.u32[0] |= MTRR_DEF_TYPE_EN; - soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr); -}

1 0

New patch to review for coreboot: mainboard/intel/galileo: Enable SD flash cards
by Leroy P Leahy 04 Mar '16

04 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13894 -gerrit commit 5b76a6f3653e3cc70f59bc5278947d564c116929 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 29 08:03:53 2016 -0800 mainboard/intel/galileo: Enable SD flash cards Turn on the SD controller to allow it to claim resources. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the SD flash card * The "drivers" command shows an SD host and SD media connection Change-Id: I883dc87270045786ddb931bea83fc36646a128e6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 6b27758..52e019b 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/quark device domain 0 on # EDS Table 3 device pci 00.0 on end # 8086 0958 - Host Bridge - device pci 14.0 off end # 8086 08A7 - SD/SDIO/eMMC controller + device pci 14.0 on end # 8086 08A7 - SD/SDIO/eMMC controller device pci 14.1 off end # 8086 0936 - HSUART 0 device pci 14.2 off end # 8086 0939 - USB 2.0 Device port device pci 14.3 on end # 8086 0939 - USB EHCI Host controller

1 0

New patch to review for coreboot: Documentation/Intel: Add EDK-II links
by Leroy P Leahy 04 Mar '16

04 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13893 -gerrit commit b155d77ea8b091371883f487d45615c5188490c5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 16:08:29 2016 -0800 Documentation/Intel: Add EDK-II links Add a link to the "Driver Writer's Guide" and a link to the "EDK II firmware for Intel Quark SoC X1000" document. TEST=None Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/quark.html | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index 5fe3f5c..47310fe 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -160,6 +160,7 @@ EDK2 Documentation: <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Dr…">V2.1</a></li> <li>DEC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1…">V1.25</a></li> <li>DSC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1…">V1.26</a></li> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer's-Guide">Driver Writer's Guide</a></li> <li>Expression Syntax <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Expression…">V1.1</a></li> <li>FDF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1…">V1.26</a></li> <li>INF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1…">V1.25</a></li> @@ -208,12 +209,13 @@ dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd Documentation: <ul> + <li><a target="_blank" href="https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg">EDK II firmware for Intel® Quark™ SoC X1000 based platforms</a></li> <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1…">UEFI Firmware Writer's Guide</a></li> </ul> <hr> -Modified: 24 February 2016 +Modified: 29 February 2016 </body> </html> \ No newline at end of file

1 0

New patch to review for coreboot: Documentation/Intel: Making a bootable SD card
by Leroy P Leahy 04 Mar '16

04 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13892 -gerrit commit 3e8fb9a18a0cf38d20fcc50df94decaf05e5babe Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 29 08:12:41 2016 -0800 Documentation/Intel: Making a bootable SD card Add a link to "Making a bootable SD card" TEST=None Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/galileo.html | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index ab27177..1cc77dc 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -42,6 +42,7 @@ <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> </ul> </li> + <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li> </ul> <h2>Galileo Gen 2 Board Documentation</h2> @@ -100,6 +101,6 @@ <hr> -Modified: 4 February 2016 +Modified: 29 February 2016 </body> </html>

1 0

Patch set updated for coreboot: arch/x86: document CAR symbols and expose them in symbols.h
by Aaron Durbin 04 Mar '16

04 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13804 -gerrit commit 3decd0c1ecf70a1b5b9894dec5be55c727a00ae5 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 17:22:17 2016 -0800 arch/x86: document CAR symbols and expose them in symbols.h Attempt to better document the symbol usage in car.ld for cache-as-ram usage. Additionally, add _car_region_[start|end] that completely covers the entire cache-as-ram region. The _car_data_[start|end] symbols were renamed to _car_relocatable_data_[start|end] in the hopes of making it clearer that objects within there move. Lastly, all these symbols were added to arch/symbols.h. Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/car.ld | 11 +++--- src/arch/x86/include/arch/early_variables.h | 8 ++--- src/arch/x86/include/arch/symbols.h | 52 +++++++++++++++++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 4 +-- src/cpu/x86/car.c | 10 +++--- 5 files changed, 69 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d19e613..c221fb8 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -18,6 +18,7 @@ /* This file is included inside a SECTIONS block */ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { + _car_region_start = . ; /* Vboot work buffer is completely volatile outside of verstage and * romstage. Appropriate code needs to handle the transition. */ #if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) @@ -36,12 +37,12 @@ * so that multiple stages (romstage and verstage) have a consistent * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) - _car_data_start = .; + _car_relocatable_data_start = .; /* The timestamp implementation relies on this storage to be around * after migration. One of the fields indicates not to use it as the * backing store once cbmem comes online. Therefore, this data needs - * to reside in the migrated area (between _car_data_start and - * _car_data_end). */ + * to reside in the migrated area (between _car_relocatable_data_start + * and _car_relocatable_data_end). */ TIMESTAMP(., 0x100) /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -51,7 +52,9 @@ *(.car.global_data); . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _car_global_end = .; - _car_data_end = .; + _car_relocatable_data_end = .; + + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } /* Global variables are not allowed in romstage diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 16eeacc..e78b846 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -16,6 +16,7 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H +#include <arch/symbols.h> #include <stdlib.h> #include <rules.h> @@ -59,18 +60,15 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) -extern char _car_data_start[]; -extern char _car_data_end[]; - static inline size_t car_data_size(void) { - size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + size_t car_size = _car_relocatable_data_size; return ALIGN(car_size, 64); } static inline size_t car_object_offset(void *ptr) { - return (char *)ptr - &_car_data_start[0]; + return (char *)ptr - &_car_relocatable_data_start[0]; } #else diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h new file mode 100644 index 0000000..e055fa0 --- /dev/null +++ b/src/arch/x86/include/arch/symbols.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_SYMBOLS_H +#define __ARCH_SYMBOLS_H + +/* + * The _car_region_[start|end] covers the entirety of the cache as ram + * region. All other symbols with the _car prefix a subsets of this + * larger region. + */ +extern char _car_region_start[]; +extern char _car_region_end[]; +#define _car_region_size (_car_region_end - _car_region_start) + +/* + * This is the stack used under CONFIG_C_ENVIRONMENT_BOOTBLOCK for + * all stages that execute when cache-as-ram is up. + */ +extern char _car_stack_start[]; +extern char _car_stack_end[]; +#define _car_stack_size (_car_stack_end - _car_stack_start) + +/* + * The _car_relocatable_data_[start|end] symbols cover CAR data which is + * relocatable once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. The _car_global_[start|end] is a subset of the + * relocatable region which excludes the timestamp region because of + * intricacies in the timestamp code. + */ +extern char _car_relocatable_data_start[]; +extern char _car_relocatable_data_end[]; +#define _car_relocatable_data_size \ + (_car_relocatable_data_end - _car_relocatable_data_start) +extern char _car_global_start[]; +extern char _car_global_end[]; +#define _car_global_size (_car_global_end - _car_global_start) + +#endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 7e33d32..0a59696 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -150,11 +150,11 @@ void post_cache_as_ram(void) void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); print_car_debug("Copying data from cache to RAM..."); - memcpy_(migrated_car, &_car_data_start[0], car_size); + memcpy_(migrated_car, _car_relocatable_data_start, car_size); print_car_debug(" Done\n"); print_car_debug("Verifying data integrity in RAM..."); - if (memcmp_(migrated_car, &_car_data_start[0], car_size) == 0) + if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0) print_car_debug(" Done\n"); else print_car_debug(" FAILED\n"); diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index fda3f7d..f9b427a 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -46,8 +46,8 @@ void *car_get_var_ptr(void *var) { char *migrated_base = NULL; int offset; - void * _car_start = &_car_data_start; - void * _car_end = &_car_data_end; + void * _car_start = _car_relocatable_data_start; + void * _car_end = _car_relocatable_data_end; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -84,8 +84,8 @@ void *car_get_var_ptr(void *var) void *car_sync_var_ptr(void *var) { void ** mig_var = car_get_var_ptr(var); - void * _car_start = &_car_data_start; - void * _car_end = &_car_data_end; + void * _car_start = _car_relocatable_data_start; + void * _car_end = _car_relocatable_data_end; /* Not moved or migrated yet. */ if (mig_var == var) @@ -129,7 +129,7 @@ static void do_car_migrate_variables(void) return; } - memcpy(migrated_base, &_car_data_start[0], car_size); + memcpy(migrated_base, _car_relocatable_data_start, car_size); /* Mark that the data has been moved. */ car_migrated = ~0;

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Patch set updated for coreboot: arch/x86: always use _start as entry symbol for all stages
by Aaron Durbin 04 Mar '16

04 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13882 -gerrit commit 06df532fcd1ac2376eeea194d676f917740f6002 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 15:26:10 2016 -0600 arch/x86: always use _start as entry symbol for all stages Instead of keeping track of all the combinations of entry points depending on the stage and other options just use _start. That way, there's no need to update the arch/header.ld for complicated cases as _start is always the entry point for a stage. Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/header.ld | 23 ----------------------- src/cpu/x86/32bit/entry32.inc | 12 ++++++++++-- 2 files changed, 10 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index d7fbf07..77eb187 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -20,27 +20,4 @@ PHDRS to_load PT_LOAD; } -/* - * For CONFIG_SEPARATE_VERSTAGE romstage doesn't have the cache-as-ram setup. - * It only contains the teardown code. The verstage has the cache-as-ram setup - * code. Therefore, it needs the protected_start symbol as its entry point. - * The romstage entry will be named _start for consistency, but it's likely - * to be implemented in the chipset code in order to control the logic flow. - */ -#if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) - #if ENV_RAMSTAGE || ENV_RMODULE || ENV_ROMSTAGE - ENTRY(_start) - #elif ENV_VERSTAGE - ENTRY(protected_start) - #endif -#else - #if ENV_RAMSTAGE || ENV_RMODULE - ENTRY(_start) - #elif ENV_ROMSTAGE - ENTRY(protected_start) - #endif -#endif - -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) && ENV_BOOTBLOCK ENTRY(_start) -#endif diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 9ef3bc1..8c39008 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -2,6 +2,7 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> +#include <rules.h> .code32 @@ -44,10 +45,17 @@ gdt_end: * * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. + * + * In the bootblock there is already a ljmp to __protected_start and + * the reset vector jumps to symbol _start16bit in entry16.inc from + * the reset vectors's symbol which is _start. Therefore, don't + * expose the _start symbol for bootblock. */ .align 4 -.globl protected_start -protected_start: +#if !ENV_BOOTBLOCK +.globl _start +_start: +#endif lgdt %cs:gdtptr ljmp $ROM_CODE_SEG, $__protected_start

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Patch merged into coreboot/master: arch/x86: rename reset_vector -> _start
by gerrit＠coreboot.org 04 Mar '16

04 Mar '16

the following patch was just integrated into master: commit 4330a9c8e52a00bf7b0b9ddd57717b7a39123ecf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 2 15:13:12 2016 -0600 arch/x86: rename reset_vector -> _start In order to align the entry points for the various stages on x86 to _start one needs to rename the reset_vector symbol. The section is the same; it's just a symbol change. Change-Id: I0e6bbf1da04a6e248781a9c222a146725c34268a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13881 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13881 for details. -gerrit

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