coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cpu/x86: Sort some Kconfig options
by Stefan Reinauer 08 Mar '16

08 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10012 -gerrit commit 2b9f203a09bd1368cf6a6ead93287b8c5a304f4f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:40:16 2015 -0700 cpu/x86: Sort some Kconfig options Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/x86/Kconfig | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 94225a3..d8f338d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,7 +1,16 @@ +# TODO These two options look too similar config PARALLEL_CPU_INIT bool default n +config PARALLEL_MP + def_bool n + help + This option uses common MP infrastructure for bringing up APs + in parallel. It additionally provides a more flexible mechanism + for sequencing the steps of bringing up the APs. + + config UDELAY_IO bool default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 @@ -39,11 +48,14 @@ config TSC_MONOTONIC_TIMER help Expose monotonic time using the TSC. -config UDELAY_TIMER2 +# This option is used in code but never selected. +config TSC_CALIBRATE_WITH_IO bool + depends on UDELAY_TSC default n -config TSC_CALIBRATE_WITH_IO +# This option is used in code but never selected. +config UDELAY_TIMER2 bool default n @@ -121,13 +133,6 @@ config PLATFORM_USES_FSP1_0 Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization. -config PARALLEL_MP - def_bool n - help - This option uses common MP infrastructure for bringing up APs - in parallel. It additionally provides a more flexible mechanism - for sequencing the steps of bringing up the APs. - config BACKUP_DEFAULT_SMM_REGION def_bool n help

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Patch set updated for coreboot: coreinfo: Update Makefile to build from coreboot
by Martin Roth 08 Mar '16

08 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13938 -gerrit commit 385ab19bf3836fd490ec24de5a7c5c1f576a1eef Author: Martin Roth <martinroth(a)google.com> Date: Mon Mar 7 16:26:51 2016 -0700 coreinfo: Update Makefile to build from coreboot - Rename obj to coreinfo_obj so it doesn't conflict with the obj variable in libpayload. - Change $(shell pwd) to $(CURDIR) to find the directory without going to the shell - Fix libpayloaddir so it doesn't get installed to libpayload/libpayload - Make all relative paths absolute by prepending $(src) - Remove .xcompile when doing a clean Change-Id: I2ffb06a87e30a5eeff5b0dfc0ba62b5e9ab46e26 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/coreinfo/Makefile | 50 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index c9f5c10..750402b 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -14,18 +14,18 @@ ## GNU General Public License for more details. ## -src := $(shell pwd) +src := $(CURDIR) srctree := $(src) srck := $(src)/../../util/kconfig -obj := $(src)/build +coreinfo_obj := $(src)/build objk := $(src)/build/util/kconfig export KERNELVERSION := 0.1.0 -export KCONFIG_AUTOHEADER := $(obj)/config.h -export KCONFIG_AUTOCONFIG := $(obj)/auto.conf -export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd -export KCONFIG_SPLITCONFIG := $(obj)/config -export KCONFIG_TRISTATE := $(obj)/tristate.conf +export KCONFIG_AUTOHEADER := $(coreinfo_obj)/config.h +export KCONFIG_AUTOCONFIG := $(coreinfo_obj)/auto.conf +export KCONFIG_DEPENDENCIES := $(coreinfo_obj)/auto.conf.cmd +export KCONFIG_SPLITCONFIG := $(coreinfo_obj)/config +export KCONFIG_TRISTATE := $(coreinfo_obj)/tristate.conf export KCONFIG_NEGATIVES := 1 export Kconfig := Kconfig @@ -47,25 +47,25 @@ HOSTCXX ?= g++ HOSTCFLAGS := -I$(srck) -I$(objk) HOSTCXXFLAGS := -I$(srck) -I$(objk) -LIBCONFIG_PATH := ../libpayload -LIBPAYLOAD_DIR := build/libpayload -HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/libpayload/lib/libpayload.a) +LIBCONFIG_PATH := $(src)/../libpayload +LIBPAYLOAD_DIR := $(coreinfo_obj)/libpayload +HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/lib/libpayload.a) LIB_CONFIG ?= defconfig OBJCOPY ?= objcopy -INCLUDES = -I$(obj) -include $(LIBPAYLOAD_DIR)/libpayload/include/kconfig.h +INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_DIR)/include/kconfig.h OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ nvram_module.o bootlog_module.o ramdump_module.o lar_module.o \ multiboot_module.o cbfs_module.o coreinfo.o -OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) -TARGET = $(obj)/coreinfo.elf +OBJS = $(patsubst %,$(coreinfo_obj)/%,$(OBJECTS)) +TARGET = $(coreinfo_obj)/coreinfo.elf all: real-all # in addition to the dependency below, create the file if it doesn't exist # to silence warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) -.xcompile: ../../util/xcompile/xcompile +$(if $(wildcard .xcompile),,$(eval $(shell $(src)/../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) +.xcompile: $(src)/../../util/xcompile/xcompile $< $(XGCCPATH) > $@.tmp \mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@ @@ -78,8 +78,8 @@ CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) OBJCOPY := $(OBJCOPY_$(ARCH-y)) -LPCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc -LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/libpayload/bin/lpas +LPCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc +LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) @@ -87,18 +87,18 @@ ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config real-all: $(TARGET) -$(TARGET): $(src)/.config $(obj)/config.h $(OBJS) libpayload +$(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(shell pwd)/,,$(@)) (LINK)\n" $(LPCC) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ -$(obj)/%.S.o: $(src)/%.S libpayload +$(coreinfo_obj)/%.S.o: $(src)/%.S libpayload printf " LPAS $(subst $(shell pwd)/,,$(@))\n" $(LPAS) -o $@ $< -$(obj)/%.o: $(src)/%.c libpayload +$(coreinfo_obj)/%.o: $(src)/%.c libpayload printf " LPCC $(subst $(shell pwd)/,,$(@))\n" $(LPCC) $(CFLAGS) -c -o $@ $< @@ -116,18 +116,18 @@ libpayload: else libpayload: printf "Building libpayload @ $(LIBCONFIG_PATH).\n" - $(MAKE) -C $(LIBCONFIG_PATH) distclean + $(MAKE) -C $(LIBCONFIG_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp $(MAKE) -C $(LIBCONFIG_PATH) $(LIB_CONFIG) - $(MAKE) -C $(LIBCONFIG_PATH) DESTDIR=$(shell pwd)/$(LIBPAYLOAD_DIR) install + $(MAKE) -C $(LIBCONFIG_PATH) install DESTDIR=$(coreinfo_obj) endif -$(obj)/config.h: +$(coreinfo_obj)/config.h: $(MAKE) oldconfig -$(shell mkdir -p $(obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) +$(shell mkdir -p $(coreinfo_obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) clean: - rm -rf build/*.elf build/*.o + rm -rf build/*.elf build/*.o .xcompile distclean: clean rm -rf build

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Patch merged into coreboot/master: soc/intel/apollolake: Enable using FSP 2.0 driver
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 0d187917554f710ac3af04c59bd18b59837a178c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 18:39:38 2016 -0800 soc/intel/apollolake: Enable using FSP 2.0 driver Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13806 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Add romstage that calls FSP2.0 driver
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit b4831460a5e61e5069021c20d7baf29fde485570 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 17:42:25 2016 -0800 soc/intel/apollolake: Add romstage that calls FSP2.0 driver This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13805 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Add support for memory-mapped boot media
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 5672dcd58c0ae7f7a0d14af0a88ff9c534e0936a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 12 15:12:43 2016 -0800 soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13706 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add framebuffer graphics support
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit fb22ff4c03091c0b84a715df1320cfe74bcea665 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Feb 25 14:22:03 2016 -0800 drivers/intel/fsp2_0: Add framebuffer graphics support This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13802 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13802 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add hand-off-block parsers
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 9b2e9bd1bbbb4ef4f99d420e699b6e9516156749 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Feb 25 14:20:38 2016 -0800 drivers/intel/fsp2_0: Add hand-off-block parsers FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13801 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13801 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add Notify Phase API
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 9de55cce55082d08ed7720aa9c314b63e49d0bf7 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:19:07 2016 -0800 drivers/intel/fsp2_0: Add Notify Phase API This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13800 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add SiliconInit API
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 42c4e886c8c9fe35d38f20e3df7e912a538c4f0f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:17:45 2016 -0800 drivers/intel/fsp2_0: Add SiliconInit API This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13799 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Add MemoryInit API
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 465fc13c0e69ddcf38168b62104fca37b91bdd68 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:16:33 2016 -0800 drivers/intel/fsp2_0: Add MemoryInit API This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13798 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13798 for details. -gerrit

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coreboot-gerrit March 2016