coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: archive: build archive tool with HOSTCC
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit a1bb091d00fb61037301290b1ffc28052cb42167 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Nov 17 13:25:39 2015 -0800 archive: build archive tool with HOSTCC BUG=chromium:502066 BRANCH=tot TEST=Tested on Jerry Change-Id: Ic227287784bd0c76a0c4c20a40c581d37420b98c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1b4e818e91998135288978c6cb68a63288bb20e5 Original-Change-Id: I28f5decabcbaf1e61c9b4e549b11e568dace8c09 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312902 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/12926 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12926 for details. -gerrit

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Patch merged into coreboot/master: util: add archive tool
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit a5ae62e9d25a07538677dd9967bbe3208f324ef8 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Nov 3 15:04:59 2015 -0800 util: add archive tool 'archive' concatenates files into a single binary blob. Files are indexed by the base names. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Iea108160e65c8c7bd34c02af824a77cb075ee64b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 21a9ba860f29599ac029f8d49d32399c4e3a73a8 Original-Change-Id: I46b4efb339e3a1e05772ae752f2861026ca09cfc Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311200 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Reviewed-on: https://review.coreboot.org/12925 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/12925 for details. -gerrit

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Patch set updated for coreboot: util: add archive tool
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12925 -gerrit commit 2d0aa9f9f7b454e7074ffecfeb22a70352ba9f3b Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Nov 3 15:04:59 2015 -0800 util: add archive tool 'archive' concatenates files into a single binary blob. Files are indexed by the base names. See archive.h for the format description. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Iea108160e65c8c7bd34c02af824a77cb075ee64b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 21a9ba860f29599ac029f8d49d32399c4e3a73a8 Original-Change-Id: I46b4efb339e3a1e05772ae752f2861026ca09cfc Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311200 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> --- util/archive/Makefile | 14 +++ util/archive/archive.c | 281 +++++++++++++++++++++++++++++++++++++++++++++++++ util/archive/archive.h | 76 +++++++++++++ 3 files changed, 371 insertions(+) diff --git a/util/archive/Makefile b/util/archive/Makefile new file mode 100644 index 0000000..a592a62 --- /dev/null +++ b/util/archive/Makefile @@ -0,0 +1,14 @@ +PROGRAM = archive +CC ?= gcc + +SRCS = $(PROGRAM).c + +all: $(PROGRAM) + +$(PROGRAM): $(SRCS) + $(CC) -o $@ $^ + +clean: + rm -f $(PROGRAM) *.o + +.PHONY: all clean diff --git a/util/archive/archive.c b/util/archive/archive.c new file mode 100644 index 0000000..36c0ab1 --- /dev/null +++ b/util/archive/archive.c @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2015 The ChromiumOS Authors. All rights reserved. + * written by Daisuke Nojiri <dnojiri(a)chromium.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "archive.h" +#include <endian.h> +#include <errno.h> +#include <libgen.h> +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +static struct directory *archive; + +static void usage(void) +{ + printf("Name:\n"); + printf(" archive - concatenate files and create an archive\n"); + printf("Usage:\n"); + printf(" archive archive_name create file0 file1 ...\n"); +} + +static int get_file_size(const char *file) +{ + FILE *fp = fopen(file, "rb"); + int size; + + if (!fp) { + fprintf(stderr, "Error: failed to open %s\n", file); + return -1; + } + fseek(fp, 0, SEEK_END); + size = ftell(fp); + fclose(fp); + if (size < 0) { + fprintf(stderr, "Error: failed to get file size\n"); + return -1; + } + + return size; +} + +static int set_file_name(const char *path, struct dentry *dest) +{ + struct dentry *entry; + char *name, *copy; + int i; + + copy = strdup(path); + name = basename(copy); + + /* check name length */ + if (strlen(name) > NAME_LENGTH) { + fprintf(stderr, "Error: file name '%s' exceeds %d chars\n", + name, NAME_LENGTH); + free(copy); + return -1; + } + + /* check if there is a duplicate name */ + entry = get_first_dentry(archive); + for (i = 0; i < archive->count && &entry[i] != dest; i++) { + if (!strncmp(entry[i].name, name, NAME_LENGTH)) { + fprintf(stderr, "Error: duplicate name '%s'\n", name); + free(copy); + return -1; + } + } + + /* copy the name to the entry */ + strncpy(dest->name, name, NAME_LENGTH); + free(copy); + + return 0; +} + +/* + * Add a file to the archive in RAM + * + * path: path to the file to be added + * entry: pointer to struct dentry where file header is created + * offset: offset of the file contents from the archive header + * + * return: 0 on success or -1 on error + */ +static int add_file(const char *path, struct dentry *entry, uint32_t offset) +{ + FILE *fp; + int size; + + if (!path || !*path || !entry) { + fprintf(stderr, "Error: invalid path or entry\n"); + return -1; + } + + size = get_file_size(path); + if (size < 0) + return -1; + if (offset + size > archive->size) { + fprintf(stderr, "Error: invalid offset or size\n"); + return -1; + } + + fp = fopen(path, "rb"); + if (!fp) { + fprintf(stderr, "Error: failed to open %s (%d: %s)\n", + path, errno, strerror(errno)); + return -1; + } + if (fread((char *)archive + offset, sizeof(char), size, fp) != size) { + fprintf(stderr, "Error: failed to read %s\n", path); + fclose(fp); + return -1; + } + fclose(fp); + + /* set file name*/ + if (set_file_name(path, entry)) + return -1; + + entry->offset = offset; + entry->size = size; + + return 0; +} + +/* + * Allocate memory for archive + * + * count: number of files to add + * files: pointer to the array of file names + * + * return: 0 on success or -1 on error + */ +static int setup_archive(int count, const char **files) +{ + uint32_t size; + int i, s; + + size = sizeof(*archive); + for (i = 0; i < count; i++) { + s = get_file_size(files[i]); + if (s < 0) + return -1; + size += sizeof(struct dentry); + size += s; + } + + archive = calloc(size, 1); + if (!archive) { + fprintf(stderr, "Error: failed to allocate memory\n"); + return -1; + } + + /* install magic string */ + memcpy(archive->magic, CBAR_MAGIC, sizeof(archive->magic)); + archive->version = VERSION; + archive->size = size; + archive->count = count; + + printf("Set up archive: size=%d count=%d\n", size, count); + + return 0; +} + +/* + * Store files in archive + */ +static int archive_files(const char **files) +{ + struct dentry *entry; + uint32_t offset; + int i; + + entry = get_first_dentry(archive); + offset = get_first_offset(archive); + for (i = 0; i < archive->count; i++) { + if (add_file(files[i], entry, offset)) + return -1; + offset += entry->size; + entry++; + } + + return 0; +} + +static void convert_endian(void) +{ + struct dentry *entry; + int i; + + entry = get_first_dentry(archive); + for (i = 0; i < archive->count; i++) { + entry[i].offset = htole32(entry[i].offset); + entry[i].size = htole32(entry[i].size); + } + + archive->version = htole32(archive->version); + archive->size = htole32(archive->size); + archive->count = htole32(archive->count); +} + +/* + * Write archive to file + */ +static int output_archive(const char *path) +{ + FILE *fp; + + convert_endian(); + + fp = fopen(path, "wb"); + if (!fp) { + fprintf(stderr, "Error: failed to open %s\n", path); + fclose(fp); + return -1; + } + if (fwrite(archive, sizeof(char), archive->size, fp) != archive->size) { + fprintf(stderr, "Error: failed to write to %s\n", path); + fclose(fp); + return -1; + } + fclose(fp); + printf("Wrote archive to %s\n", path); + + return 0; +} + +static int cmd_create(const char *archive_path, int count, const char **files) +{ + if (count < 1 || !files) { + fprintf(stderr, "Error: no input files specified\n"); + return -1; + } + + if (setup_archive(count, files)) + return -1; + + if (archive_files(files)) + return -1; + + if (output_archive(archive_path)) + return -1; + + return 0; +} + +int main(int argc, const char *argv[]) +{ + const char *command; + + if (argc < 3) { + fprintf(stderr, "Error: invalid number of arguments\n"); + usage(); + return -1; + } + + command = argv[2]; + + /* branch by command name */ + if (!strncmp(command, "create", sizeof("create"))) { + if (cmd_create(argv[1], argc - 3, &argv[3])) + return -1; + } else { + fprintf(stderr, "Error: invalid command: %s\n", command); + return -1; + } + + return 0; +} diff --git a/util/archive/archive.h b/util/archive/archive.h new file mode 100644 index 0000000..67c42e2 --- /dev/null +++ b/util/archive/archive.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2015 The ChromiumOS Authors. All rights reserved. + * written by Daisuke Nojiri <dnojiri(a)chromium.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCHIVE_H +#define __ARCHIVE_H + +#include <stdint.h> + +/* + * Archive file layout: + * + * +----------------------------------+ + * | root header | + * +----------------------------------+ + * | file_header[0] | + * +----------------------------------+ + * | file_header[1] | + * +----------------------------------+ + * | ... | + * +----------------------------------+ + * | file_header[count-1] | + * +----------------------------------+ + * | file(0) content | + * +----------------------------------+ + * | file(1) content | + * +----------------------------------+ + * | ... | + * +----------------------------------+ + * | file(count-1) content | + * +----------------------------------+ + */ + +#define VERSION 0 +#define CBAR_MAGIC "CBAR" +#define NAME_LENGTH 32 + +/* Root header */ +struct directory { + char magic[4]; + uint32_t version; /* version of the header. little endian */ + uint32_t size; /* total size of archive. little endian */ + uint32_t count; /* number of files. little endian */ +}; + +/* File header */ +struct dentry { + /* file name. null-terminated if shorter than NAME_LENGTH */ + char name[NAME_LENGTH]; + /* file offset from the root header. little endian */ + uint32_t offset; + /* file size. little endian */ + uint32_t size; +}; + +static inline struct dentry *get_first_dentry(const struct directory *dir) +{ + return (struct dentry *)(dir + 1); +} + +static inline uint32_t get_first_offset(const struct directory *dir) +{ + return sizeof(struct directory) + sizeof(struct dentry) * dir->count; +} + +#endif

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New patch to review for coreboot: crossgcc/buildgcc: Add comment about URLs and jenkins builder
by Martin Roth 08 Mar '16

08 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13955 -gerrit commit 084da09a0b4d17a55b2b3fddb2396ad7edb3f306 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 09:37:14 2016 -0700 crossgcc/buildgcc: Add comment about URLs and jenkins builder Add a comment to try to lower possible confusion later if the jenkins tool builder fails to build a new tool. The URLs for the packages that are downloaded are checked against known locations so that someone can't maliciously download a package from somewhere and run it on the build server. This provides a little bit of security, but could confuse someone if they don't realize it. Change-Id: I7858e3d86fc705b480f6792b6adf3d5349580e01 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index df9ac4a..eef71e5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -47,6 +47,9 @@ CLANG_VERSION=3.7.1 MAKE_VERSION=4.1 # GCC toolchain archive locations +# These are sanitized by the jenkins toolchain test builder, so if +# a completely new URL is added here, it probably needs to be added +# to the jenkins build as well, or the builder won't download it. GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"

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Patch merged into coreboot/master: soc/intel/apollolake: Add cbmem_top() implementation
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 491c016d77fa56461e8669e45796da97bbab3c37 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 2 15:09:27 2016 -0800 soc/intel/apollolake: Add cbmem_top() implementation On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13883 for details. -gerrit

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New patch to review for coreboot: crossgcc/Makefile.inc: Add target for jenkins toolchain test build
by Martin Roth 08 Mar '16

08 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13954 -gerrit commit 44e899ce508c186bf420fd1944f0a485ef730c0d Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 09:27:45 2016 -0700 crossgcc/Makefile.inc: Add target for jenkins toolchain test build We've recently added a jenkins test builder for the coreboot toolchain. This patch allows what it builds to be controlled from the makefiles checked into git instead of by a rule on the builder itself. Change-Id: I65f70bac5ab97ecb27aae93ee370b26a2ab1f9c0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 0f27208..dfa1ec8 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -38,7 +38,8 @@ crossgcc: clean-for-update .PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ - crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 + crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ + jenkins-build-toolchain $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) build_iasl SKIP_GDB=1 @@ -65,3 +66,8 @@ ifeq ($(COMPILER_OUT_OF_DATE),1) else echo "The coreboot toolchain is the current version." endif # ifeq ($(COMPILER_OUT_OF_DATE),1) + +# This target controls what the jenkins builder tests +jenkins-build-toolchain: + $(MAKE) crosstools clang \ + BUILDGCC_OPTIONS='-y --nocolor'

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Patch set updated for coreboot: payloads/seabios: Add "git revision" to the SeaBIOS version menu
by Antonello Dettori 08 Mar '16

08 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13937 -gerrit commit 64a06575477e67c254c9964203622bfce485daa0 Author: Antonello Dettori <dev(a)dettori.io> Date: Mon Mar 7 23:56:57 2016 +0000 payloads/seabios: Add "git revision" to the SeaBIOS version menu Add an option to specify a git revision from which to build SeaBIOS. Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/external/Makefile.inc | 2 ++ payloads/external/SeaBIOS/Kconfig | 16 ++++++++++++++++ payloads/external/SeaBIOS/Makefile.inc | 7 +++++++ 3 files changed, 25 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 557de2a..5eb1062 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -45,6 +45,8 @@ seabios: AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_REVISION=$(CONFIG_SEABIOS_REVISION) \ + CONFIG_SEABIOS_REVISION_ID=$(CONFIG_SEABIOS_REVISION_ID) \ CONFIG_PAYLOAD_CONFIGFILE=$(CONFIG_PAYLOAD_CONFIGFILE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 70f5ce2..8a8d931 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -12,9 +12,25 @@ config SEABIOS_MASTER bool "master" help Newest SeaBIOS version +config SEABIOS_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch + that you want to use as the revision from which to + build SeaBIOS. + + You will be able to specify the name of a branch or a commit id + later. endchoice +config SEABIOS_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on SEABIOS_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e478a09..b6ec2f6 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,6 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_STABLE)=01a84bea2d28a19d2405c1ecac4bdef17683cc0c +TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -15,6 +16,12 @@ seabios: git clone http://review.coreboot.org/p/seabios.git seabios fetch: seabios +ifeq ($(CONFIG_SEABIOS_REVISION),y) +ifeq ($(CONFIG_SEABIOS_REVISION_ID),) + echo "Error: There is no revision specified for SeaBIOS" + false +endif +endif cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi

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New patch to review for coreboot: libpayload: mmu: Assuming that memory 0-4GiB is device memory
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13914 -gerrit commit 8f89004d17f4850895b6267951118825e7331c30 Author: huang lin <hl(a)rock-chips.com> Date: Thu Mar 3 15:29:34 2016 +0800 libpayload: mmu: Assuming that memory 0-4GiB is device memory in some platform(like rk3399), mmio space start 0xf8000000, exceed 2GB, so fix it. Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Signed-off-by: huang lin <hl(a)rock-chips.com> --- payloads/libpayload/arch/arm64/mmu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index f07e4c4..9bb402b 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -260,7 +260,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag) * Desc : Initialize mmu based on the mmu_memrange passed. ttb_buffer is used as * the base address for xlat tables. TTB_DEFAULT_SIZE defines the max number of * tables that can be used - * Assuming that memory 0-2GiB is device memory. + * Assuming that memory 0-4GiB is device memory. */ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) { @@ -275,8 +275,7 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n", (void*)xlat_addr, max_tables); - mmu_config_range(NULL, 0x80000000, TYPE_DEV_MEM); - + mmu_config_range(NULL, 0x100000000, TYPE_DEV_MEM); for (; i < mmu_ranges->used; i++) mmu_config_range((void *)mmu_ranges->entries[i].base, mmu_ranges->entries[i].size,

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Patch set updated for coreboot: rockchip: rk3399: support gpio
by Lin Huang 08 Mar '16

08 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13919 -gerrit commit 9f4f16cb219bcffbe3cb29e1960aac519a2ad0fe Author: huang lin <hl(a)rock-chips.com> Date: Wed Mar 2 17:29:01 2016 +0800 rockchip: rk3399: support gpio Change-Id: I1d213a91ea508997b876441250743671204d7c53 Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/soc/rockchip/rk3399/Makefile.inc | 5 ++ src/soc/rockchip/rk3399/gpio.c | 78 ++++++++++++++++++++++++++++++ src/soc/rockchip/rk3399/include/soc/gpio.h | 66 +++++++++++++++++++++++++ 3 files changed, 149 insertions(+) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index e9093ba..47dc1b8 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -22,6 +22,7 @@ bootblock-y += spi.c bootblock-y += clock.c bootblock-y += mmu_operations.c bootblock-y += i2c.c +bootblock-y += gpio.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif @@ -32,6 +33,7 @@ verstage-y += timer.c verstage-y += spi.c verstage-y += clock.c verstage-y += i2c.c +verstage-y += gpio.c ################################################################################ @@ -42,6 +44,8 @@ romstage-y += spi.c romstage-y += clock.c romstage-y += mmu_operations.c romstage-y += i2c.c +romstage-y += gpio.c + ################################################################################ ramstage-y += cbmem.c @@ -51,6 +55,7 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-y += clock.c ramstage-y += i2c.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c new file mode 100644 index 0000000..0fa5ee4 --- /dev/null +++ b/src/soc/rockchip/rk3399/gpio.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <stdlib.h> + +struct rk3399_gpio_regs *gpio_port[] = { + (struct rk3399_gpio_regs *)GPIO0_BASE, + (struct rk3399_gpio_regs *)GPIO1_BASE, + (struct rk3399_gpio_regs *)GPIO2_BASE, + (struct rk3399_gpio_regs *)GPIO3_BASE, + (struct rk3399_gpio_regs *)GPIO4_BASE, +}; + +enum { + PULLNONE = 0, + PULLUP, + PULLDOWN +}; + +#define PMU_GPIO_PORT0 0 +#define PMU_GPIO_PORT1 1 + +static void __gpio_input(gpio_t gpio, u32 pull) +{ + clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); + if (gpio.port == PMU_GPIO_PORT0 || gpio.port == PMU_GPIO_PORT1) + clrsetbits_le32(&rk3399_pmugrf->gpio0_p[gpio.port][gpio.bank], + 3 << (gpio.idx * 2), pull << (gpio.idx * 2)); + else + write32(&rk3399_grf->gpio2_p[(gpio.port - 2)][gpio.bank], + RK_CLRSETBITS(3 << (gpio.idx * 2), + pull << (gpio.idx * 2))); +} + +void gpio_input(gpio_t gpio) +{ + __gpio_input(gpio, PULLNONE); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + __gpio_input(gpio, PULLDOWN); +} + +void gpio_input_pullup(gpio_t gpio) +{ + __gpio_input(gpio, PULLUP); +} + +int gpio_get(gpio_t gpio) +{ + return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1; +} + +void gpio_output(gpio_t gpio, int value) +{ + setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); + clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); +} diff --git a/src/soc/rockchip/rk3399/include/soc/gpio.h b/src/soc/rockchip/rk3399/include/soc/gpio.h new file mode 100644 index 0000000..cd85be0 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/gpio.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_GPIO_H__ +#define __SOC_ROCKCHIP_RK3399_GPIO_H__ + +#include <types.h> + +#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i}) + +struct rk3399_gpio_regs { + u32 swporta_dr; + u32 swporta_ddr; + u32 reserved0[(0x30 - 0x08) / 4]; + u32 inten; + u32 intmask; + u32 inttype_level; + u32 int_polarity; + u32 int_status; + u32 int_rawstatus; + u32 debounce; + u32 porta_eoi; + u32 ext_porta; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 ls_sync; +}; +check_member(rk3399_gpio_regs, ls_sync, 0x60); + +typedef union { + u32 raw; + struct { + u16 port; + union { + struct { + u16 num:5; + u16 :11; + }; + struct { + u16 idx:3; + u16 bank:2; + u16 :11; + }; + }; + }; +} gpio_t; + +enum { + GPIO_A = 0, + GPIO_B, + GPIO_C, + GPIO_D, +}; + +#endif /* __SOC_ROCKCHIP_RK3399_GPIO_H__ */

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Patch set updated for coreboot: rockchip: rk3399: support i2c
by Lin Huang 08 Mar '16

08 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13918 -gerrit commit e6a8edada0f45fee991232cc56f1cc8d328e7521 Author: huang lin <hl(a)rock-chips.com> Date: Wed Mar 2 18:46:24 2016 +0800 rockchip: rk3399: support i2c Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04 Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/soc/rockchip/rk3399/Makefile.inc | 4 + src/soc/rockchip/rk3399/i2c.c | 297 ++++++++++++++++++++++++++++++ src/soc/rockchip/rk3399/include/soc/i2c.h | 23 +++ 3 files changed, 324 insertions(+) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index c630b26..e9093ba 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-y += clock.c bootblock-y += mmu_operations.c +bootblock-y += i2c.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif @@ -30,6 +31,7 @@ verstage-y += cbmem.c verstage-y += timer.c verstage-y += spi.c verstage-y += clock.c +verstage-y += i2c.c ################################################################################ @@ -39,6 +41,7 @@ romstage-y += timer.c romstage-y += spi.c romstage-y += clock.c romstage-y += mmu_operations.c +romstage-y += i2c.c ################################################################################ ramstage-y += cbmem.c @@ -47,6 +50,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += clock.c +ramstage-y += i2c.c ################################################################################ diff --git a/src/soc/rockchip/rk3399/i2c.c b/src/soc/rockchip/rk3399/i2c.c new file mode 100644 index 0000000..669b16c --- /dev/null +++ b/src/soc/rockchip/rk3399/i2c.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c.h> +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/i2c.h> +#include <soc/clock.h> +#include <stdlib.h> +#include <string.h> + +#define RETRY_COUNT 3 +/* 100000us = 100ms */ +#define I2C_TIMEOUT_US 100000 +#define I2C_BUS_MAX 6 +#define I2C_NOACK 2 +#define I2C_TIMEOUT 3 + +#define i2c_info(x...) do {if (0) printk(BIOS_DEBUG, x); } while (0) + +struct rk3399_i2c_regs { + u32 i2c_con; + u32 i2c_clkdiv; + u32 i2c_mrxaddr; + u32 i2c_mrxraddr; + u32 i2c_mtxcnt; + u32 i2c_mrxcnt; + u32 i2c_ien; + u32 i2c_ipd; + u32 i2c_fcnt; + u32 reserved0[(0x100 - 0x24) / 4]; + u32 txdata[8]; + u32 reserved1[(0x200 - 0x120) / 4]; + u32 rxdata[8]; +}; + +struct rk3399_i2c_regs *i2c_bus[] = { + (struct rk3399_i2c_regs *)I2C0_BASE, + (struct rk3399_i2c_regs *)I2C1_BASE, + (struct rk3399_i2c_regs *)I2C2_BASE, + (struct rk3399_i2c_regs *)I2C3_BASE, + (struct rk3399_i2c_regs *)I2C4_BASE, + (struct rk3399_i2c_regs *)I2C5_BASE, + (struct rk3399_i2c_regs *)I2C6_BASE, + (struct rk3399_i2c_regs *)I2C7_BASE, + (struct rk3399_i2c_regs *)I2C8_BASE, +}; + +/* Con register bits. */ +#define I2C_ACT2NAK (1<<6) +#define I2C_NAK (1<<5) +#define I2C_STOP (1<<4) +#define I2C_START (1<<3) +#define I2C_MODE_TX (0<<1) +#define I2C_MODE_TRX (1<<1) +#define I2C_MODE_RX (2<<1) +#define I2C_EN (1<<0) + +#define I2C_8BIT (1<<24) +#define I2C_16BIT (3<<24) +#define I2C_24BIT (7<<24) + +/* Mtxcnt register bits. */ +#define I2C_CNT(cnt) ((cnt) & 0x3F) + +#define I2C_NAKRCVI (1<<6) +#define I2C_STOPI (1<<5) +#define I2C_STARTI (1<<4) +#define I2C_MBRFI (1<<3) +#define I2C_MBTFI (1<<2) +#define I2C_BRFI (1<<1) +#define I2C_BTFI (1<<0) +#define I2C_CLEANI 0x7F + +static int i2c_send_start(struct rk3399_i2c_regs *reg_addr) +{ + int res = 0; + int timeout = I2C_TIMEOUT_US; + + i2c_info("I2c Start::Send Start bit\n"); + write32(&reg_addr->i2c_ipd, I2C_CLEANI); + write32(&reg_addr->i2c_con, I2C_EN | I2C_START); + while (timeout--) { + if (read32(&reg_addr->i2c_ipd) & I2C_STARTI) + break; + udelay(1); + } + + if (timeout <= 0) { + printk(BIOS_ERR, "I2C Start::Send Start Bit Timeout\n"); + res = I2C_TIMEOUT; + } + + return res; +} + +static int i2c_send_stop(struct rk3399_i2c_regs *reg_addr) +{ + int res = 0; + int timeout = I2C_TIMEOUT_US; + + i2c_info("I2c Stop::Send Stop bit\n"); + write32(&reg_addr->i2c_ipd, I2C_CLEANI); + write32(&reg_addr->i2c_con, I2C_EN | I2C_STOP); + while (timeout--) { + if (read32(&reg_addr->i2c_ipd) & I2C_STOPI) + break; + udelay(1); + } + write32(&reg_addr->i2c_con, 0); + if (timeout <= 0) { + printk(BIOS_ERR, "I2C Stop::Send Stop Bit Timeout\n"); + res = I2C_TIMEOUT; + } + + return res; +} + +static int i2c_read(struct rk3399_i2c_regs *reg_addr, struct i2c_seg segment) +{ + int res = 0; + uint8_t *data = segment.buf; + int timeout; + unsigned int bytes_remaining = segment.len; + unsigned int bytes_transfered; + unsigned int words_transfered; + unsigned int rxdata; + unsigned int con; + unsigned int i, j; + + write32(&reg_addr->i2c_mrxaddr, I2C_8BIT | segment.chip << 1 | 1); + write32(&reg_addr->i2c_mrxraddr, 0); + con = I2C_MODE_TRX | I2C_EN | I2C_ACT2NAK; + while (bytes_remaining) { + bytes_transfered = MIN(bytes_remaining, 32); + bytes_remaining -= bytes_transfered; + if (!bytes_remaining) + con |= I2C_EN | I2C_NAK; + words_transfered = ALIGN_UP(bytes_transfered, 4) / 4; + + write32(&reg_addr->i2c_ipd, I2C_CLEANI); + write32(&reg_addr->i2c_con, con); + write32(&reg_addr->i2c_mrxcnt, bytes_transfered); + + timeout = I2C_TIMEOUT_US; + while (timeout--) { + if (read32(&reg_addr->i2c_ipd) & I2C_NAKRCVI) { + write32(&reg_addr->i2c_mrxcnt, 0); + write32(&reg_addr->i2c_con, 0); + return I2C_NOACK; + } + if (read32(&reg_addr->i2c_ipd) & I2C_MBRFI) + break; + udelay(1); + } + if (timeout <= 0) { + printk(BIOS_ERR, "I2C Read::Recv Data Timeout\n"); + write32(&reg_addr->i2c_mrxcnt, 0); + write32(&reg_addr->i2c_con, 0); + return I2C_TIMEOUT; + } + + for (i = 0; i < words_transfered; i++) { + rxdata = read32(&reg_addr->rxdata[i]); + i2c_info("I2c Read::RXDATA[%d] = 0x%x\n", i, rxdata); + for (j = 0; j < 4; j++) { + if ((i * 4 + j) == bytes_transfered) + break; + *data++ = (rxdata >> (j * 8)) & 0xff; + } + } + con = I2C_MODE_RX | I2C_EN | I2C_ACT2NAK; + } + return res; +} + +static int i2c_write(struct rk3399_i2c_regs *reg_addr, struct i2c_seg segment) +{ + int res = 0; + uint8_t *data = segment.buf; + int timeout; + int bytes_remaining = segment.len + 1; + int bytes_transfered; + int words_transfered; + unsigned int i; + unsigned int j; + u32 txdata = 0; + + txdata |= (segment.chip << 1); + while (bytes_remaining) { + bytes_transfered = MIN(bytes_remaining, 32); + words_transfered = ALIGN_UP(bytes_transfered, 4) / 4; + for (i = 0; i < words_transfered; i++) { + do { + if ((i * 4 + j) == bytes_transfered) + break; + txdata |= (*data++) << (j * 8); + } while (++j < 4); + write32(&reg_addr->txdata[i], txdata); + j = 0; + i2c_info("I2c Write::TXDATA[%d] = 0x%x\n", i, txdata); + txdata = 0; + } + + write32(&reg_addr->i2c_ipd, I2C_CLEANI); + write32(&reg_addr->i2c_con, + I2C_EN | I2C_MODE_TX | I2C_ACT2NAK); + write32(&reg_addr->i2c_mtxcnt, bytes_transfered); + + timeout = I2C_TIMEOUT_US; + while (timeout--) { + if (read32(&reg_addr->i2c_ipd) & I2C_NAKRCVI) { + write32(&reg_addr->i2c_mtxcnt, 0); + write32(&reg_addr->i2c_con, 0); + return I2C_NOACK; + } + if (read32(&reg_addr->i2c_ipd) & I2C_MBTFI) + break; + udelay(1); + } + + if (timeout <= 0) { + printk(BIOS_ERR, "I2C Write::Send Data Timeout\n"); + write32(&reg_addr->i2c_mtxcnt, 0); + write32(&reg_addr->i2c_con, 0); + return I2C_TIMEOUT; + } + + bytes_remaining -= bytes_transfered; + } + return res; +} + +static int i2c_do_xfer(void *reg_addr, struct i2c_seg segment) +{ + int res = 0; + + if (i2c_send_start(reg_addr)) + return I2C_TIMEOUT; + if (segment.read) + res = i2c_read(reg_addr, segment); + else + res = i2c_write(reg_addr, segment); + return i2c_send_stop(reg_addr) || res; +} + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) +{ + int i; + int res = 0; + struct rk3399_i2c_regs *regs = i2c_bus[bus]; + struct i2c_seg *seg = segments; + + for (i = 0; i < seg_count; i++, seg++) { + res = i2c_do_xfer(regs, *seg); + if (res) + break; + } + return res; +} + +void i2c_init(unsigned int bus, unsigned int hz) +{ + unsigned int clk_div; + unsigned int divl; + unsigned int divh; + unsigned int i2c_src_clk = 0; + struct rk3399_i2c_regs *regs = i2c_bus[bus]; + + i2c_src_clk = 24 * 1000 * 1000; + /*SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1) + SCL = PCLK/ SCLK Divisor + */ + clk_div = div_round_up(i2c_src_clk, hz * 8); + divh = clk_div * 3 / 7 - 1; + divl = clk_div - divh - 2; + assert((divh < 65536) && (divl < 65536)); + write32(&regs->i2c_clkdiv, (divh << 16) | (divl << 0)); +} diff --git a/src/soc/rockchip/rk3399/include/soc/i2c.h b/src/soc/rockchip/rk3399/include/soc/i2c.h new file mode 100644 index 0000000..271febd --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/i2c.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_I2C_H__ +#define __SOC_ROCKCHIP_RK3399_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); +void software_i2c_attach(unsigned bus); +void software_i2c_detach(unsigned bus); + +#endif

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coreboot-gerrit March 2016