coreboot-gerrit March 2016

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Patch set updated for coreboot: rockchip: rk3399: add grf define
by Lin Huang 08 Mar '16

08 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13917 -gerrit commit e841e132f1b62b2b78c45d84b6d15849c98bcd8b Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Mar 7 18:43:12 2016 +0800 rockchip: rk3399: add grf define add grf define, we can do iomux and secure setting Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/mainboard/google/gru/bootblock.c | 14 ++ src/soc/rockchip/rk3399/bootblock.c | 13 ++ src/soc/rockchip/rk3399/include/soc/grf.h | 295 ++++++++++++++++++++++++++++++ 3 files changed, 322 insertions(+) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index bdc75dd..ce6f7c0 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -14,12 +14,26 @@ * */ +#include <arch/io.h> +#include <assert.h> #include <bootblock_common.h> +#include <soc/grf.h> +#include <soc/spi.h> +#include <console/console.h> void bootblock_mainboard_early_init(void) { + if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); + write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C); + + /* grf soc_con7[11:10] use for uart2 select*/ + write32(&rk3399_grf->soc_con7, UART2C_SEL); + } } void bootblock_mainboard_init(void) { + write32(&rk3399_grf->iomux_spi2, IOMUX_SPI2); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); } diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index dc604a1..03075ab 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -18,10 +18,23 @@ #include <arch/mmu.h> #include <bootblock_common.h> #include <console/console.h> +#include <soc/grf.h> #include <soc/mmu_operations.h> #include <symbols.h> void bootblock_soc_init(void) { + /* all ddr range non-secure */ + write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); + + /* tzma_rosize = 0, all sram non-serure */ + write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0); + + /* emmc master secure*/ + write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7); + + /* glb_slv_secure_bypass */ + write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1); + rockchip_mmu_init(); } diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h new file mode 100644 index 0000000..96c2fed --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ +#define __SOC_ROCKCHIP_RK3399_GRF_H__ + +#include <soc/addressmap.h> +#include <soc/soc.h> +#include <types.h> + +struct rk3399_grf_regs { + u32 reserved[0x800]; + u32 usb3_perf_con0; + u32 usb3_perf_con1; + u32 usb3_perf_con2; + u32 usb3_perf_rd_max_latency_num; + u32 usb3_perf_rd_latency_samp_num; + u32 usb3_perf_rd_latency_acc_num; + u32 usb3_perf_rd_axi_total_byte; + u32 usb3_perf_wr_axi_total_byte; + u32 usb3_perf_working_cnt; + u32 reserved1[0x103]; + u32 usb3otg0_con0; + u32 usb3otg0_con1; + u32 reserved2[2]; + u32 usb3otg1_con0; + u32 usb3otg1_con1; + u32 reserved3[2]; + u32 usb3otg0_status_lat0; + u32 usb3otg0_status_lat1; + u32 usb3otg0_status_cb; + u32 reserved4; + u32 usb3otg1_status_lat0; + u32 usb3otg1_status_lat1; + u32 usb3ogt1_status_cb; + u32 reserved5[0x6e5]; + u32 pcie_perf_con0; + u32 pcie_perf_con1; + u32 pcie_perf_con2; + u32 pcie_perf_rd_max_latency_num; + u32 pcie_perf_rd_latency_samp_num; + u32 pcie_perf_rd_laterncy_acc_num; + u32 pcie_perf_rd_axi_total_byte; + u32 pcie_perf_wr_axi_total_byte; + u32 pcie_perf_working_cnt; + u32 reserved6[0x37]; + u32 usb20_host0_con0; + u32 usb20_host0_con1; + u32 reserved7[2]; + u32 usb20_host1_con0; + u32 usb20_host1_con1; + u32 reserved8[2]; + u32 hsic_con0; + u32 hsic_con1; + u32 reserved9[6]; + u32 grf_usbhost0_status; + u32 grf_usbhost1_Status; + u32 grf_hsic_status; + u32 reserved10[0xc9]; + u32 hsicphy_con0; + u32 reserved11[3]; + u32 usbphy0_ctrl[26]; + u32 reserved12[6]; + u32 usbphy1[26]; + u32 reserved13[0x72f]; + u32 soc_con9; + u32 reserved14[0x0a]; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 soc_con23; + u32 soc_con24; + u32 soc_con25; + u32 soc_con26; + u32 reserved15[0xf65]; + u32 cpu_con[4]; + u32 reserved16[0x1c]; + u32 cpu_status[6]; + u32 reserved17[0x1a]; + u32 a53_perf_con[4]; + u32 a53_perf_rd_mon_st; + u32 a53_perf_rd_mon_end; + u32 a53_perf_wr_mon_st; + u32 a53_perf_wr_mon_end; + u32 a53_perf_rd_max_latency_num; + u32 a53_perf_rd_latency_samp_num; + u32 a53_perf_rd_laterncy_acc_num; + u32 a53_perf_rd_axi_total_byte; + u32 a53_perf_wr_axi_total_byte; + u32 a53_perf_working_cnt; + u32 a53_perf_int_status; + u32 reserved18[0x31]; + u32 a72_perf_con[4]; + u32 a72_perf_rd_mon_st; + u32 a72_perf_rd_mon_end; + u32 a72_perf_wr_mon_st; + u32 a72_perf_wr_mon_end; + u32 a72_perf_rd_max_latency_num; + u32 a72_perf_rd_latency_samp_num; + u32 a72_perf_rd_laterncy_acc_num; + u32 a72_perf_rd_axi_total_byte; + u32 a72_perf_wr_axi_total_byte; + u32 a72_perf_working_cnt; + u32 a72_perf_int_status; + u32 reserved19[0x7f6]; + u32 soc_con5; + u32 soc_con6; + u32 reserved20[0x779]; + u32 gpio2a_iomux; + union { + u32 iomux_spi2; + u32 gpio2b_iomux; + }; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 gpio4a_iomux; + union { + u32 iomux_uart2a; + u32 gpio4b_iomux; + }; + union { + u32 iomux_uart2b; + u32 iomux_uart2c; + u32 gpio4c_iomux; + }; + u32 gpio4d_iomux; + u32 reserved21[4]; + u32 gpio2_p[3][4]; + u32 reserved22[4]; + u32 gpio2_sr[3][4]; + u32 reserved23[4]; + u32 gpio2_smt[3][4]; + u32 reserved24[0x44]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5_pcie; + u32 reserved25; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9_pcie; + u32 reserved26[0x1e]; + u32 soc_status[6]; + u32 reserved27[0x32]; + u32 ddrc0_con0; + u32 ddrc0_con1; + u32 ddrc1_con0; + u32 ddrc1_con1; +}; +check_member(rk3399_grf_regs, ddrc1_con1, 0xe38c); + +struct rk3399_pmugrf_regs { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 reserved0[2]; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 reserved1[8]; + u32 gpio0_p[2][4]; + u32 reserved3[8]; + u32 gpio0a_e; + u32 reserved4; + u32 gpio0b_e; + u32 reserved5[5]; + u32 gpio1a_e; + u32 reserved6; + u32 gpio1b_e; + u32 reserved7; + u32 gpio1c_e; + u32 reserved8; + u32 gpio1d_e; + u32 reserved9[0x11]; + u32 gpio0l_sr; + u32 reserved10; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 reserved11[4]; + u32 gpio0a_smt; + u32 gpio0b_smt; + u32 reserved12[2]; + u32 gpio1a_smt; + u32 gpio1b_smt; + u32 gpio1c_smt; + u32 gpio1d_smt; + u32 reserved13[8]; + u32 gpio0l_he; + u32 reserved14; + u32 gpio1l_he; + u32 gpio1h_he; + u32 reserved15[4]; + u32 soc_con0; + u32 reserved16[9]; + u32 soc_con10; + u32 soc_con11; + u32 reserved17[0x24]; + u32 pmupvtm_con0; + u32 pmupvtm_con1; + u32 pmupvtm_status0; + u32 pmupvtm_status1; + u32 grf_osc_e; + u32 reserved18[0x2b]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; +}; +check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); + +struct rk3399_pmusgrf_regs { + u32 ddr_rgn_con[35]; + u32 reserved[0x1fe5]; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 reserved1[3]; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 reserved2[0x29]; + u32 perilp_con[9]; + u32 reserved4[7]; + u32 perilp_status; + u32 reserved5[0xfaf]; + u32 soc_con0; + u32 soc_con1; + u32 reserved6[0x3e]; + u32 pmu_con[9]; + u32 reserved7[0x17]; + u32 fast_boot_addr; + u32 reserved8[0x1f]; + u32 efuse_prg_mask; + u32 efuse_read_mask; + u32 reserved9[0x0e]; + u32 pmu_slv_con0; + u32 pmu_slv_con1; + u32 reserved10[0x771]; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 reserved11[8]; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 reserved12[0xdd]; + u32 slv_secure_con0; + u32 slv_secure_con1; + u32 reserved13; + u32 slv_secure_con2; + u32 slv_secure_con3; + u32 slv_secure_con4; +}; +check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); + +static struct rk3399_grf_regs * const rk3399_grf = (void *)GRF_BASE; +static struct rk3399_pmugrf_regs * const rk3399_pmugrf = (void *)PMUGRF_BASE; +static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE; + +#define UART2A_SEL RK_CLRSETBITS(3 << 10, 0 << 10) +#define UART2B_SEL RK_CLRSETBITS(3 << 10, 1 << 10) +#define UART2C_SEL RK_CLRSETBITS(3 << 10, 2 << 10) + +#define IOMUX_UART2A RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0) +#define IOMUX_UART2B RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0) +#define IOMUX_UART2C RK_CLRSETBITS(3 << 8 | 3 << 6, 1 << 8 | 1 << 6) +#define IOMUX_SPI2 RK_CLRSETBITS(0xff << 2, 1 << 8 | 1 << 6 | 1 << 4 | 1 << 2) + +#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */

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Patch set updated for coreboot: rockchip: rk3399: enable mmu
by Lin Huang 08 Mar '16

08 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13916 -gerrit commit ebc56e845694baf4fb57f1425f206b6890b454cc Author: huang lin <hl(a)rock-chips.com> Date: Thu Mar 3 14:47:30 2016 +0800 rockchip: rk3399: enable mmu Change-Id: I66bfde396036d7a66b29517937a28f0767635066 Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/mainboard/google/gru/romstage.c | 9 ++++++ src/soc/rockchip/rk3399/Makefile.inc | 3 +- src/soc/rockchip/rk3399/bootblock.c | 2 ++ .../rockchip/rk3399/include/soc/mmu_operations.h | 31 +++++++++++++++++++ src/soc/rockchip/rk3399/mmu_operations.c | 36 ++++++++++++++++++++++ 5 files changed, 80 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 4786937..93eb41a 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -18,17 +18,26 @@ #include <arch/cpu.h> #include <arch/exception.h> #include <arch/io.h> +#include <arch/mmu.h> #include <cbfs.h> #include <console/console.h> #include <delay.h> #include <program_loading.h> #include <romstage_handoff.h> #include <symbols.h> +#include <soc/mmu_operations.h> + +static const uint64_t dram_size = (uint64_t)CONFIG_DRAM_SIZE_MB * MiB; void main(void) { console_init(); exception_init(); + + /*TODO: need implement sdram init */ + + mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); cbmem_initialize_empty(); run_ramstage(); } diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 2067404..c630b26 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += bootblock.c bootblock-y += timer.c bootblock-y += spi.c bootblock-y += clock.c +bootblock-y += mmu_operations.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif @@ -37,7 +38,7 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += spi.c romstage-y += clock.c - +romstage-y += mmu_operations.c ################################################################################ ramstage-y += cbmem.c diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index ae41a08..dc604a1 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -18,8 +18,10 @@ #include <arch/mmu.h> #include <bootblock_common.h> #include <console/console.h> +#include <soc/mmu_operations.h> #include <symbols.h> void bootblock_soc_init(void) { + rockchip_mmu_init(); } diff --git a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h new file mode 100644 index 0000000..9772ea3 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SOC_ROCKCHIP_RK3399_MMU_H__ +#define __SOC_ROCKCHIP_RK3399_MMU_H__ + +#include <arch/mmu.h> + +enum { + DEV_MEM = MA_DEV | MA_S | MA_RW, + CACHED_MEM = MA_MEM | MA_NS | MA_RW, + SECURE_MEM = MA_MEM | MA_S | MA_RW, + UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, +}; + +void rockchip_mmu_init(void); +#endif + diff --git a/src/soc/rockchip/rk3399/mmu_operations.c b/src/soc/rockchip/rk3399/mmu_operations.c new file mode 100644 index 0000000..2c2ef2c --- /dev/null +++ b/src/soc/rockchip/rk3399/mmu_operations.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/io.h> +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <soc/mmu_operations.h> +#include <symbols.h> + +void rockchip_mmu_init(void) +{ + mmu_init(); + + /* Set 0x0 to end of dram as device memory */ + mmu_config_range((void *)0, (uintptr_t)8192 * MiB, DEV_MEM); + + mmu_config_range(_sram, _sram_size, SECURE_MEM); + + /* set ttb as secure */ + mmu_config_range(_ttb, _ttb_size, SECURE_MEM); + mmu_enable(); +}

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Patch set updated for coreboot: coreboot: rk3399: Add a stub implementation of the rk3399 SOC
by Lin Huang 08 Mar '16

08 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13915 -gerrit commit fe8bad03338ea617c290a947ed45fdb74bd6c93a Author: huang lin <hl(a)rock-chips.com> Date: Wed Mar 2 18:38:40 2016 +0800 coreboot: rk3399: Add a stub implementation of the rk3399 SOC Most things still needs to be filled in, but this will allow us to build boards which use this SOC Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/mainboard/google/gru/Kconfig | 67 ++++++ src/mainboard/google/gru/Kconfig.name | 2 + src/mainboard/google/gru/Makefile.inc | 34 +++ src/mainboard/google/gru/boardid.c | 28 +++ src/mainboard/google/gru/bootblock.c | 25 ++ src/mainboard/google/gru/chromeos.c | 41 ++++ src/mainboard/google/gru/devicetree.cb | 18 ++ src/mainboard/google/gru/mainboard.c | 36 +++ src/mainboard/google/gru/memlayout.ld | 1 + src/mainboard/google/gru/romstage.c | 34 +++ src/soc/rockchip/rk3399/Kconfig | 28 +++ src/soc/rockchip/rk3399/Makefile.inc | 59 +++++ src/soc/rockchip/rk3399/bootblock.c | 25 ++ src/soc/rockchip/rk3399/cbmem.c | 23 ++ src/soc/rockchip/rk3399/clock.c | 21 ++ src/soc/rockchip/rk3399/include/soc/addressmap.h | 58 +++++ src/soc/rockchip/rk3399/include/soc/clock.h | 21 ++ src/soc/rockchip/rk3399/include/soc/memlayout.ld | 36 +++ src/soc/rockchip/rk3399/include/soc/soc.h | 26 ++ src/soc/rockchip/rk3399/include/soc/spi.h | 195 +++++++++++++++ src/soc/rockchip/rk3399/include/soc/timer.h | 39 +++ src/soc/rockchip/rk3399/soc.c | 51 ++++ src/soc/rockchip/rk3399/spi.c | 288 +++++++++++++++++++++++ src/soc/rockchip/rk3399/timer.c | 45 ++++ src/soc/rockchip/rk3399/uart.c | 168 +++++++++++++ 25 files changed, 1369 insertions(+) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig new file mode 100644 index 0000000..9f80e2f --- /dev/null +++ b/src/mainboard/google/gru/Kconfig @@ -0,0 +1,67 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_GOOGLE_GRU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select SOC_ROCKCHIP_RK3399 + select BOARD_ROMSIZE_KB_4096 + #select RAM_CODE_SUPPORT + select CHROMEOS_VBNV_FLASH + #select EC_GOOGLE_CHROMEEC + #select EC_GOOGLE_CHROMEEC_SPI + #select EC_SOFTWARE_SYNC + #select MAINBOARD_HAS_NATIVE_VGA_INIT + #select MAINBOARD_DO_NATIVE_VGA_INIT + select VIRTUAL_DEV_SWITCH + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND + select MOCK_TPM + select VBOOT2_MOCK_SECDATA +config MAINBOARD_DIR + string + default google/gru + +config MAINBOARD_PART_NUMBER + string + default "gru" + +config MAINBOARD_VENDOR + string + default "Google" + +config DRAM_SIZE_MB + int + default 2048 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0 + +config BOOT_MEDIA_SPI_BUS + int + default 1 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0xFF1A0000 + +endif # BOARD_GOOGLE_GRU diff --git a/src/mainboard/google/gru/Kconfig.name b/src/mainboard/google/gru/Kconfig.name new file mode 100644 index 0000000..7511903 --- /dev/null +++ b/src/mainboard/google/gru/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_GRU + bool "Gru" diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc new file mode 100644 index 0000000..36a854f --- /dev/null +++ b/src/mainboard/google/gru/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-y += memlayout.ld +bootblock-y += chromeos.c +bootblock-y += boardid.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c +verstage-y += boardid.c + +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += memlayout.ld +romstage-y += boardid.c + +ramstage-y += mainboard.c +ramstage-y += chromeos.c +ramstage-y += memlayout.ld +ramstage-y += boardid.c + diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c new file mode 100644 index 0000000..f62fe97 --- /dev/null +++ b/src/mainboard/google/gru/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <console/console.h> +#include <stdlib.h> + +uint8_t board_id(void) +{ + return 0; +} + +uint32_t ram_code(void) +{ + return 0; +} diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c new file mode 100644 index 0000000..bdc75dd --- /dev/null +++ b/src/mainboard/google/gru/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_early_init(void) +{ +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c new file mode 100644 index 0000000..6f9380d --- /dev/null +++ b/src/mainboard/google/gru/chromeos.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb new file mode 100644 index 0000000..b349888 --- /dev/null +++ b/src/mainboard/google/gru/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/rockchip/rk3399 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c new file mode 100644 index 0000000..9e83660 --- /dev/null +++ b/src/mainboard/google/gru/mainboard.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <boardid.h> +#include <boot/coreboot_tables.h> +#include <device/device.h> +#include <console/console.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "gru", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/gru/memlayout.ld b/src/mainboard/google/gru/memlayout.ld new file mode 100644 index 0000000..ead7f47 --- /dev/null +++ b/src/mainboard/google/gru/memlayout.ld @@ -0,0 +1 @@ +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c new file mode 100644 index 0000000..4786937 --- /dev/null +++ b/src/mainboard/google/gru/romstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/cache.h> +#include <arch/cpu.h> +#include <arch/exception.h> +#include <arch/io.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <program_loading.h> +#include <romstage_handoff.h> +#include <symbols.h> + +void main(void) +{ + console_init(); + exception_init(); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig new file mode 100644 index 0000000..34d072a --- /dev/null +++ b/src/soc/rockchip/rk3399/Kconfig @@ -0,0 +1,28 @@ +config SOC_ROCKCHIP_RK3399 + bool + default n + select ARM64_A53_ERRATUM_843419 + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select HAVE_UART_SPECIAL + #select SPI_ATOMIC_SEQUENCING + select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY + select HAS_PRECBMEM_TIMESTAMP_REGION + select UNCOMPRESSED_RAMSTAGE + #select GENERIC_GPIO_LIB + #select RTC + select VBOOT_STARTS_IN_BOOTBLOCK + select SEPARATE_VERSTAGE + select RETURN_FROM_VERSTAGE + +if SOC_ROCKCHIP_RK3399 + +config PMIC_BUS + int + default -1 + +endif diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc new file mode 100644 index 0000000..2067404 --- /dev/null +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_ROCKCHIP_RK3399),y) + +IDBTOOL = util/rockchip/make_idb.py +bootblock-y += bootblock.c +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += clock.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_DRIVERS_UART) += uart.c +endif + +verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += cbmem.c +verstage-y += timer.c +verstage-y += spi.c +verstage-y += clock.c + +################################################################################ + +romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += spi.c +romstage-y += clock.c + +################################################################################ + +ramstage-y += cbmem.c +ramstage-y += soc.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += clock.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/rockchip/rk3399/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + @$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK33 + +endif diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c new file mode 100644 index 0000000..ae41a08 --- /dev/null +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/io.h> +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <symbols.h> + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/rockchip/rk3399/cbmem.c b/src/soc/rockchip/rk3399/cbmem.c new file mode 100644 index 0000000..3292515 --- /dev/null +++ b/src/soc/rockchip/rk3399/cbmem.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <stddef.h> +#include <symbols.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t) _dram + (CONFIG_DRAM_SIZE_MB << 20)); +} diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c new file mode 100644 index 0000000..cb7b400 --- /dev/null +++ b/src/soc/rockchip/rk3399/clock.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <soc/clock.h> + +void rkclk_configure_spi(unsigned int bus, unsigned int hz) +{ +} diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h new file mode 100644 index 0000000..6ddf7aa --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ +#define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ + +#define PMUGRF_BASE 0xff320000 +#define PMUSGRF_BASE 0xff330000 +#define CRU_BASE 0xff760000 +#define GRF_BASE 0xff770000 +#define TIMER0_BASE 0xff850000 +#define EMMC_BASE 0xfe330000 +#define SDMMC_BASE 0xfe320000 + +#define GPIO0_BASE 0xff720000 +#define GPIO1_BASE 0xff730000 +#define GPIO2_BASE 0xff780000 +#define GPIO3_BASE 0xff788000 +#define GPIO4_BASE 0xff790000 + +#define I2C0_BASE 0xff3c0000 +#define I2C1_BASE 0xff110000 +#define I2C2_BASE 0xff120000 +#define I2C3_BASE 0xff130000 +#define I2C4_BASE 0xff3d0000 +#define I2C5_BASE 0xff140000 +#define I2C6_BASE 0xff150000 +#define I2C7_BASE 0xff160000 +#define I2C8_BASE 0xff3e0000 + +#define UART0_BASE 0xff180000 +#define UART1_BASE 0xff190000 +#define UART2_BASE 0xff1a0000 +#define UART3_BASE 0xff1b0000 +#define UART4_BASE 0xff370000 + +#define SPI0_BASE 0xff1c0000 +#define SPI1_BASE 0xff1d0000 +#define SPI2_BASE 0xff1e0000 +#define SPI3_BASE 0xff350000 +#define SPI4_BASE 0xff1f0000 +#define SPI5_BASE 0xff200000 + +#define TSADC_BASE 0xff260000 + +#endif /* __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h new file mode 100644 index 0000000..c0ba52c --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__ +#define __SOC_ROCKCHIP_RK3399_CLOCK_H__ + +void rkclk_configure_spi(unsigned int bus, unsigned int hz); + +#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld new file mode 100644 index 0000000..edb246d --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + POSTRAM_CBFS_CACHE(0x00100000, 1M) + RAMSTAGE(0x00300000, 256K) + DMA_COHERENT(0x10000000, 2M) + + SRAM_START(0xFF8C0000) + BOOTBLOCK(0xFF8C2004, 32K - 4) + PRERAM_CBFS_CACHE(0xFF8CA000, 4K) + PRERAM_CBMEM_CONSOLE(0xFF8CB000, 4K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 64K) + VBOOT2_WORK(0XFF8DC000, 12K) + TTB(0xFF8DF000, 32K) + TIMESTAMP(0xFF8E7000, 1K) + STACK(0xFF8E7400, 24K) + SRAM_END(0xFF8F0000) +} diff --git a/src/soc/rockchip/rk3399/include/soc/soc.h b/src/soc/rockchip/rk3399/include/soc/soc.h new file mode 100644 index 0000000..71f9adb --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/soc.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_CPU_H__ +#define __SOC_ROCKCHIP_RK3399_CPU_H__ + +#include <arch/io.h> +#include <symbols.h> + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) + +#endif diff --git a/src/soc/rockchip/rk3399/include/soc/spi.h b/src/soc/rockchip/rk3399/include/soc/spi.h new file mode 100644 index 0000000..b2b2427 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/spi.h @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_SPI_H__ +#define __SOC_ROCKCHIP_RK3399_SPI_H__ + +/* This driver serves as a CBFS media source. */ +#include <spi-generic.h> +#include <types.h> + +struct rockchip_spi { + u32 ctrlr0; + u32 ctrlr1; + u32 spienr; + u32 ser; + u32 baudr; + u32 txftlr; + u32 rxftlr; + u32 txflr; + u32 rxflr; + u32 sr; + u32 ipr; + u32 imr; + u32 isr; + u32 risr; + u32 icr; + u32 dmacr; + u32 damtdlr; + u32 damrdlr; + u32 reserved[(0x400-0x48)/4]; + u32 txdr[0x100]; + u32 rxdr[0x100]; +}; +check_member(rockchip_spi, rxdr, 0x800); + + +#define SF_READ_DATA_CMD 0x3 + +/* --------Bit fields in CTRLR0--------begin */ + +#define SPI_DFS_OFFSET 0 /* Data Frame Size */ +#define SPI_DFS_MASK 0x3 +#define SPI_DFS_4BIT 0x00 +#define SPI_DFS_8BIT 0x01 +#define SPI_DFS_16BIT 0x02 +#define SPI_DFS_RESV 0x03 + +/* Control Frame Size */ +#define SPI_CFS_OFFSET 2 +#define SPI_CFS_MASK 0xF + +/* Serial Clock Phase */ +#define SPI_SCPH_OFFSET 6 +#define SPI_SCPH_MASK 0x1 + +/* Serial clock toggles in middle of first data bit */ +#define SPI_SCPH_TOGMID 0 + +/* Serial clock toggles at start of first data bit */ +#define SPI_SCPH_TOGSTA 1 + +/* Serial Clock Polarity */ +#define SPI_SCOL_OFFSET 7 +#define SPI_SCOL_MASK 0x1 + +/* Inactive state of clock serial clock is low */ +#define SPI_SCOL_LOW 0 + +/* Inactive state of clock serial clock is high */ +#define SPI_SCOL_HIGH 1 + +/* Chip Select Mode */ +#define SPI_CSM_OFFSET 8 +#define SPI_CSM_MASK 0x3 + +/* ss_n keep low after every frame data is transferred */ +#define SPI_CSM_KEEP 0x00 + +/* + * ss_n be high for half sclk_out cycles after + * every frame data is transferred + */ +#define SPI_CSM_HALF 0x01 + +/* ss_n be high for one sclk_out cycle after every frame data is transferred */ +#define SPI_CSM_ONE 0x02 +#define SPI_CSM_RESV 0x03 + +/* SSN to Sclk_out delay */ +#define SPI_SSN_DELAY_OFFSET 10 +#define SPI_SSN_DELAY_MASK 0x1 +/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ +#define SPI_SSN_DELAY_HALF 0x00 +/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ +#define SPI_SSN_DELAY_ONE 0x01 + +/* Serial Endian Mode */ +#define SPI_SEM_OFFSET 11 +#define SPI_SEM_MASK 0x1 +/* little endian */ +#define SPI_SEM_LITTLE 0x00 +/* big endian */ +#define SPI_SEM_BIG 0x01 + +/* First Bit Mode */ +#define SPI_FBM_OFFSET 12 +#define SPI_FBM_MASK 0x1 +/* first bit in MSB */ +#define SPI_FBM_MSB 0x00 +/* first bit in LSB */ +#define SPI_FBM_LSB 0x01 + +/* Byte and Halfword Transform */ +#define SPI_HALF_WORLD_TX_OFFSET 13 +#define SPI_HALF_WORLD_MASK 0x1 +/* apb 16bit write/read, spi 8bit write/read */ +#define SPI_APB_16BIT 0x00 +/* apb 8bit write/read, spi 8bit write/read */ +#define SPI_APB_8BIT 0x01 + +/* Rxd Sample Delay */ +#define SPI_RXDSD_OFFSET 14 +#define SPI_RXDSD_MASK 0x3 + +/* Frame Format */ +#define SPI_FRF_OFFSET 16 +#define SPI_FRF_MASK 0x3 +/* motorola spi */ +#define SPI_FRF_SPI 0x00 +/* Texas Instruments SSP*/ +#define SPI_FRF_SSP 0x01 +/* National Semiconductors Microwire */ +#define SPI_FRF_MICROWIRE 0x02 +#define SPI_FRF_RESV 0x03 + +/* Transfer Mode */ +#define SPI_TMOD_OFFSET 18 +#define SPI_TMOD_MASK 0x3 +/* xmit & recv */ +#define SPI_TMOD_TR 0x00 +/* xmit only */ +#define SPI_TMOD_TO 0x01 +/* recv only */ +#define SPI_TMOD_RO 0x02 +#define SPI_TMOD_RESV 0x03 + +/* Operation Mode */ +#define SPI_OMOD_OFFSET 20 +#define SPI_OMOD_MASK 0x1 +/* Master Mode */ +#define SPI_OMOD_MASTER 0x00 +/* Slave Mode */ +#define SPI_OMOD_SLAVE 0x01 + +/* --------Bit fields in CTRLR0--------end */ +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f +#define SR_BUSY (1 << 0) +#define SR_TF_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define SPI_INT_TXEI (1 << 0) +#define SPI_INT_TXOI (1 << 1) +#define SPI_INT_RXUI (1 << 2) +#define SPI_INT_RXOI (1 << 3) +#define SPI_INT_RXFI (1 << 4) + +/* Bit fields in DMACR */ +#define SPI_DMACR_TX_ENABLE (1 << 1) +#define SPI_DMACR_RX_ENABLE (1 << 0) + +/* Bit fields in ICR */ +#define SPI_CLEAR_INT_ALL (1 << 0) +#define SPI_CLEAR_INT_RXUI (1 << 1) +#define SPI_CLEAR_INT_RXOI (1 << 2) +#define SPI_CLEAR_INT_TXOI (1 << 3) + +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif diff --git a/src/soc/rockchip/rk3399/include/soc/timer.h b/src/soc/rockchip/rk3399/include/soc/timer.h new file mode 100644 index 0000000..8513cfa --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/timer.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_TIMER_H__ +#define __SOC_ROCKCHIP_RK3399_TIMER_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> +#include <timer.h> + +static const u32 clocks_per_usec = (24 * 1000 * 1000) / USECS_PER_SEC; + +struct rk3399_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_cur_value0; + u32 timer_cur_value1; + u32 timer_load_count2; + u32 timer_load_count3; + u32 timer_int_status; + u32 timer_ctrl_reg; +}; + +static struct rk3399_timer * const timer0_ptr = (void *)TIMER0_BASE; +#define TIMER_LOAD_VAL 0xffffffff + +#endif /* __SOC_ROCKCHIP_RK3399_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c new file mode 100644 index 0000000..aa21038 --- /dev/null +++ b/src/soc/rockchip/rk3399/soc.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/cpu.h> +#include <console/console.h> +#include <device/device.h> +#include <stdlib.h> +#include <stddef.h> +#include <string.h> +#include <symbols.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, + CONFIG_DRAM_SIZE_MB * KiB); +} + +static void soc_init(device_t dev) +{ + /* reserve bl31 image, which define in + * arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h + */ + mmio_resource(dev, 1, (0x500000 / KiB), (0x80000 / KiB)); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_rockchip_rk3399_ops = { + CHIP_NAME("SOC Rockchip RK3399\n") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/rockchip/rk3399/spi.c b/src/soc/rockchip/rk3399/spi.c new file mode 100644 index 0000000..6b788c2 --- /dev/null +++ b/src/soc/rockchip/rk3399/spi.c @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <endian.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/spi.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <stdlib.h> +#include <timer.h> + +struct rockchip_spi_slave { + struct spi_slave slave; + struct rockchip_spi *regs; +}; + +#define SPI_TIMEOUT_US 1000 +#define SPI_SRCCLK_HZ (99*MHz) +#define SPI_FIFO_DEPTH 32 + +static struct rockchip_spi_slave rockchip_spi_slaves[3] = { + { + .slave = { + .bus = 0, + .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, + }, + .regs = (void *)SPI0_BASE, + }, + { + .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, + .regs = (void *)SPI1_BASE, + }, + { + .slave = { + .bus = 2, + .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, + }, + .regs = (void *)SPI2_BASE, + }, + +}; + +static struct rockchip_spi_slave *to_rockchip_spi(struct spi_slave *slave) +{ + return container_of(slave, struct rockchip_spi_slave, slave); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + assert(bus >= 0 && bus < 3); + return &(rockchip_spi_slaves[bus].slave); +} + +static void spi_cs_activate(struct spi_slave *slave) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + + setbits_le32(&regs->ser, 1); +} + +static void spi_cs_deactivate(struct spi_slave *slave) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + clrbits_le32(&regs->ser, 1); +} + +static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) +{ + if (enable == 1) + write32(&regs->spienr, 1); + else + write32(&regs->spienr, 0); +} + +static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) +{ + unsigned short clk_div = SPI_SRCCLK_HZ / hz; + assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1)); + write32(&regs->baudr, clk_div); +} + +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) +{ + struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; + unsigned int ctrlr0 = 0; + + rkclk_configure_spi(bus, SPI_SRCCLK_HZ); + rockchip_spi_enable_chip(regs, 0); + rockchip_spi_set_clk(regs, speed_hz); + + /* Operation Mode */ + ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); + + /* Data Frame Size */ + ctrlr0 |= SPI_DFS_8BIT << SPI_DFS_OFFSET; + + /* Chip Select Mode */ + ctrlr0 |= (SPI_CSM_KEEP << SPI_CSM_OFFSET); + + /* SSN to Sclk_out delay */ + ctrlr0 |= (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET); + + /* Serial Endian Mode */ + ctrlr0 |= (SPI_SEM_LITTLE << SPI_SEM_OFFSET); + + /* First Bit Mode */ + ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET); + + /* Byte and Halfword Transform */ + ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); + + /* Rxd Sample Delay */ + ctrlr0 |= (0 << SPI_RXDSD_OFFSET); + + /* Frame Format */ + ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); + + write32(&regs->ctrlr0, ctrlr0); + + /* fifo depth */ + write32(&regs->txftlr, SPI_FIFO_DEPTH / 2 - 1); + write32(&regs->rxftlr, SPI_FIFO_DEPTH / 2 - 1); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + spi_cs_activate(slave); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + spi_cs_deactivate(slave); +} + +static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_US); + do { + if (!(read32(&regs->sr) & SR_BUSY)) + return 0; + } while (!stopwatch_expired(&sw)); + + printk(BIOS_DEBUG, + "RK SPI: Status keeps busy for 1000us after a read/write!\n"); + return -1; +} + +static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) +{ + clrsetbits_le32(&regs->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + tmod << SPI_TMOD_OFFSET); +} + +static void set_transfer_mode(struct rockchip_spi *regs, + unsigned int sout, unsigned int sin) +{ + if (!sin && !sout) + return; + else if (sin && sout) + set_tmod(regs, SPI_TMOD_TR); /* tx and rx */ + else if (!sin) + set_tmod(regs, SPI_TMOD_TO); /* tx only */ + else if (!sout) + set_tmod(regs, SPI_TMOD_RO); /* rx only */ +} + +/* returns 0 to indicate success, <0 otherwise */ +static int do_xfer(struct spi_slave *slave, const void *dout, + unsigned int *bytes_out, void *din, unsigned int *bytes_in) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + uint8_t *in_buf = din; + uint8_t *out_buf = (uint8_t *)dout; + unsigned int min_xfer; + + if (*bytes_out == 0) + min_xfer = *bytes_in; + else if (*bytes_in == 0) + min_xfer = *bytes_out; + else + min_xfer = MIN(*bytes_in, *bytes_out); + + while (min_xfer) { + uint32_t sr = read32(&regs->sr); + int xferred = 0; /* in either (or both) directions */ + + if (*bytes_out && !(sr & SR_TF_FULL)) { + write32(&regs->txdr, *out_buf); + out_buf++; + *bytes_out -= 1; + xferred = 1; + } + + if (*bytes_in && !(sr & SR_RF_EMPT)) { + *in_buf = read32(&regs->rxdr) & 0xff; + in_buf++; + *bytes_in -= 1; + xferred = 1; + } + + min_xfer -= xferred; + } + + if (rockchip_spi_wait_till_not_busy(regs)) { + printk(BIOS_ERR, "Timed out waiting on SPI transfer\n"); + return -1; + } + + return 0; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(65535, buf_len); +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bytes_out, void *din, unsigned int bytes_in) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + int ret = 0; + + /* + * RK3288 SPI controller can transfer up to 65536 data frames (bytes + * in our case) continuously. Break apart large requests as necessary. + * + * FIXME: And by 65536, we really mean 65535. If 0xffff is written to + * ctrlr1, all bytes that we see in rxdr end up being 0x00. 0xffff - 1 + * seems to work fine. + */ + while (bytes_out || bytes_in) { + unsigned int in_now = MIN(bytes_in, 0xffff); + unsigned int out_now = MIN(bytes_out, 0xffff); + unsigned int in_rem, out_rem; + + rockchip_spi_enable_chip(regs, 0); + + /* Enable/disable transmitter and receiver as needed to + * avoid sending or reading spurious bits. */ + set_transfer_mode(regs, bytes_out, bytes_in); + + /* MAX() in case either counter is 0 */ + write32(&regs->ctrlr1, MAX(in_now, out_now) - 1); + + rockchip_spi_enable_chip(regs, 1); + + in_rem = in_now; + out_rem = out_now; + ret = do_xfer(slave, dout, &out_rem, din, &in_rem); + if (ret < 0) + break; + + if (bytes_out) { + unsigned int sent = out_now - out_rem; + bytes_out -= sent; + dout += sent; + } + + if (bytes_in) { + unsigned int received = in_now - in_rem; + bytes_in -= received; + din += received; + } + } + + rockchip_spi_enable_chip(regs, 0); + return ret < 0 ? ret : 0; +} diff --git a/src/soc/rockchip/rk3399/timer.c b/src/soc/rockchip/rk3399/timer.c new file mode 100644 index 0000000..96cf540 --- /dev/null +++ b/src/soc/rockchip/rk3399/timer.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <delay.h> +#include <soc/timer.h> +#include <stdint.h> +#include <timer.h> + +static uint64_t timer_raw_value(void) +{ + uint64_t value0; + uint64_t value1; + + value0 = (uint64_t)read32(&timer0_ptr->timer_cur_value0); + value1 = (uint64_t)read32(&timer0_ptr->timer_cur_value1); + + return value0 | value1<<32; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec); +} + +void init_timer(void) +{ + write32(&timer0_ptr->timer_load_count0, TIMER_LOAD_VAL); + write32(&timer0_ptr->timer_load_count1, TIMER_LOAD_VAL); + write32(&timer0_ptr->timer_load_count2, 0); + write32(&timer0_ptr->timer_load_count3, 0); + write32(&timer0_ptr->timer_ctrl_reg, 1); +} diff --git a/src/soc/rockchip/rk3399/uart.c b/src/soc/rockchip/rk3399/uart.c new file mode 100644 index 0000000..6cd763e --- /dev/null +++ b/src/soc/rockchip/rk3399/uart.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> +#include <stdint.h> + +/* + * TODO: Use DRIVERS_UART_8250MEM driver instead. + * There is an issue in the IO call functions where x86 and ARM + * ordering is reversed. This 8250MEM driver uses the x86 convention. + * This driver can be replaced once the IO calls are sorted. + */ + +struct rk3399_uart { + union { + uint32_t thr; /* Transmit holding register. */ + uint32_t rbr; /* Receive buffer register. */ + uint32_t dll; /* Divisor latch lsb. */ + }; + union { + uint32_t ier; /* Interrupt enable register. */ + uint32_t dlm; /* Divisor latch msb. */ + }; + union { + uint32_t iir; /* Interrupt identification register. */ + uint32_t fcr; /* FIFO control register. */ + }; + uint32_t lcr; /* Line control register. */ + uint32_t mcr; /* Modem control register. */ + uint32_t lsr; /* Line status register. */ + uint32_t msr; /* Modem status register. */ + uint32_t scr; + uint32_t reserved1[(0x30 - 0x20) / 4]; + uint32_t srbr[(0x70 - 0x30) / 4]; + uint32_t far; + uint32_t tfr; + uint32_t rfw; + uint32_t usr; + uint32_t tfl; + uint32_t rfl; + uint32_t srr; + uint32_t srts; + uint32_t sbcr; + uint32_t sdmam; + uint32_t sfe; + uint32_t srt; + uint32_t stet; + uint32_t htx; + uint32_t dmasa; + uint32_t reserver2[(0xf4 - 0xac) / 4]; + uint32_t cpr; + uint32_t ucv; + uint32_t ctr; +} __attribute__ ((packed)); + + +static struct rk3399_uart * const uart_ptr = + (void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + +static void rk3399_uart_tx_flush(void); +static int rk3399_uart_tst_byte(void); + +static void rk3399_uart_init(void) +{ + /* FIXME: Use a hardcoded divisor for now. + * uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(), + * uart_platform_refclk(), 16) + */ + const unsigned divisor = 13; + const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 + + rk3399_uart_tx_flush(); + + /* Disable interrupts. */ + write32(&uart_ptr->ier, 0); + + /* Force DTR and RTS to high. */ + write32(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); + + /* Set line configuration, access divisor latches. */ + write32(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); + + /* Set the divisor. */ + write32(&uart_ptr->dll, divisor & 0xff); + write32(&uart_ptr->dlm, (divisor >> 8) & 0xff); + + /* Hide the divisor latches. */ + write32(&uart_ptr->lcr, line_config); + + /* Enable FIFOs, and clear receive and transmit. */ + write32(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); +} + +static void rk3399_uart_tx_byte(unsigned char data) +{ + while (!(read32(&uart_ptr->lsr) & UART8250_LSR_THRE)); + write32(&uart_ptr->thr, data); +} + +static void rk3399_uart_tx_flush(void) +{ + while (!(read32(&uart_ptr->lsr) & UART8250_LSR_TEMT)); +} + +static unsigned char rk3399_uart_rx_byte(void) +{ + if (!rk3399_uart_tst_byte()) + return 0; + return read32(&uart_ptr->rbr); +} + +static int rk3399_uart_tst_byte(void) +{ + return (read32(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; +} + + + +void uart_init(int idx) +{ + rk3399_uart_init(); +} + +unsigned char uart_rx_byte(int idx) +{ + return rk3399_uart_rx_byte(); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + rk3399_uart_tx_byte(data); +} + +void uart_tx_flush(int idx) +{ + rk3399_uart_tx_flush(); +} + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + serial.baud = default_baudrate(); + serial.regwidth = 1; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

1 0

Patch set updated for coreboot: rockchip: update make_idb.py
by Lin Huang 08 Mar '16

08 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13913 -gerrit commit abc62fd9c1f3bd454bbc8f9c389d392a055142e7 Author: huang lin <hl(a)rock-chips.com> Date: Wed Mar 2 16:02:45 2016 +0800 rockchip: update make_idb.py make_idb.py only support RK3288 before, add chip parameter, so we can support RK3399 either. Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5 Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/soc/rockchip/rk3288/Makefile.inc | 2 +- util/rockchip/make_idb.py | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 0ce6425..0df7eb7 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -74,6 +74,6 @@ CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" @mkdir -p $(dir $@) - @$(IDBTOOL) --from=$< --to=$@ --enable-align + @$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK32 endif diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12ef83c..1ffb910 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -29,7 +29,7 @@ class IDBTool: k = (S[i] + S[j]) % 256 buf[x] = struct.pack('B', ord(buf[x]) ^ S[k]) - def makeIDB(self, from_file, to_file, rc4_flag = False, align_flag = False): + def makeIDB(self, chip, from_file, to_file, rc4_flag = False, align_flag = False): try: fin = open(from_file, 'rb') except: @@ -52,7 +52,7 @@ class IDBTool: sectors = pages * PAGE_ALIGN; buf = [B'\0'] * sectors * SECTOR_SIZE - buf[:4] = "RK32" + buf[:4] = chip buf[4 : 4+data_len] = data idblock = [B'\0'] * 4 * SECTOR_SIZE @@ -95,11 +95,13 @@ class IDBTool: print "DONE" def usage(): - print "Usage: make_idb.py [--enable-rc4] [--enable-align] [--to=out] --from=in" + print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" + print " --chip: default is RK32" if __name__ == '__main__': rc4_flag = align_flag = False to_file = "IDBlock.bin" + chip = "RK32" for para in sys.argv[1:]: if (para == "--enable-rc4"): @@ -110,6 +112,8 @@ if __name__ == '__main__': to_file = para.split('=')[1] elif (para.startswith("--from=")): from_file = para.split('=')[1] + elif (para.startswith("--chip=")): + chip = para.split('=')[1] elif (para == "--help" or para == "-h"): usage() sys.exit() @@ -121,4 +125,4 @@ if __name__ == '__main__': sys.exit() idbtool = IDBTool() - idbtool.makeIDB(from_file, to_file, rc4_flag, align_flag) + idbtool.makeIDB(chip, from_file, to_file, rc4_flag, align_flag)

1 0

Patch set updated for coreboot: payloads/seabios: Add "git revision" to the SeaBIOS version menu
by Antonello Dettori 08 Mar '16

08 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13937 -gerrit commit a3b3a648a52a8785a2af4da437b797c12e4306ff Author: Antonello Dettori <dev(a)dettori.io> Date: Mon Mar 7 23:56:57 2016 +0000 payloads/seabios: Add "git revision" to the SeaBIOS version menu Adds an option to specify a git revision from which to build SeaBIOS. Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/external/Makefile.inc | 2 ++ payloads/external/SeaBIOS/Kconfig | 16 ++++++++++++++++ payloads/external/SeaBIOS/Makefile.inc | 7 +++++++ 3 files changed, 25 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 557de2a..5eb1062 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -45,6 +45,8 @@ seabios: AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_REVISION=$(CONFIG_SEABIOS_REVISION) \ + CONFIG_SEABIOS_REVISION_ID=$(CONFIG_SEABIOS_REVISION_ID) \ CONFIG_PAYLOAD_CONFIGFILE=$(CONFIG_PAYLOAD_CONFIGFILE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 70f5ce2..8a8d931 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -12,9 +12,25 @@ config SEABIOS_MASTER bool "master" help Newest SeaBIOS version +config SEABIOS_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch + that you want to use as the revision from which to + build SeaBIOS. + + You will be able to specify the name of a branch or a commit id + later. endchoice +config SEABIOS_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on SEABIOS_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e478a09..b6ec2f6 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,6 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_STABLE)=01a84bea2d28a19d2405c1ecac4bdef17683cc0c +TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -15,6 +16,12 @@ seabios: git clone http://review.coreboot.org/p/seabios.git seabios fetch: seabios +ifeq ($(CONFIG_SEABIOS_REVISION),y) +ifeq ($(CONFIG_SEABIOS_REVISION_ID),) + echo "Error: There is no revision specified for SeaBIOS" + false +endif +endif cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi

1 0

Patch merged into coreboot/master: Kconfig: Remove unneeded UDELAY_IO redeclaration
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 41aa8bc9abd8ce29a716d283c481fd74e9ac9567 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 10:48:40 2016 -0800 Kconfig: Remove unneeded UDELAY_IO redeclaration UDELAY_IO is defined in src/cpu/x86/Kconfig, so it does not need to be redefined in the AMD cpu or board Kconfigs. Change-Id: I6676881c0ba5d1634230fc3d3c37da3afbc6fceb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13780 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13780 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/x86/mtrr: add helper function to detect variable MTRRs
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit e63be8971bac14c50b97602aedcc2a85b7e5f540 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:05:36 2016 -0600 cpu/x86/mtrr: add helper function to detect variable MTRRs The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13935 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13935 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Add the UPD support for SiliconInit
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit e99e2b65cfc594ecfa56cb12660f731a6f88a57a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:52:25 2016 -0800 soc/intel/quark: Add the UPD support for SiliconInit Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13897 for details. -gerrit

1 0

Patch merged into coreboot/master: crossgcc: Build make per default
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit f466ea97bf716d47b4765d3c2df24ec14572a699 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 6 02:18:47 2016 -0800 crossgcc: Build make per default Build make with the rest of the toolchain, since the targets using a Chromium EC need make 4.x Change-Id: I7efb0c25f605f16c2d9a1e7c4b203f3bcdae671b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13923 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13923 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/x86: Sort some Kconfig options
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 9d5e36e839382920e2b5b9f138bd03c3d40276f5 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:40:16 2015 -0700 cpu/x86: Sort some Kconfig options Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/10012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/10012 for details. -gerrit

1 0

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