coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

New patch to review for coreboot: drivers/intel/fsp2_0: add TODOs to fix deficiencies
by Aaron Durbin 08 Mar '16

08 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13959 -gerrit commit ec0da82c3c42be597d1c6db6909020a72c1b8546 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 8 11:20:53 2016 -0600 drivers/intel/fsp2_0: add TODOs to fix deficiencies The FSP 2.0 implementation doesn't handle FSP modules for SoCs that are required to be XIP. There is no notion of "loading" in that situation where one should be copying anything anywhere. Additionally, the loading code does not handle overlaps within the current running program which is doing the loading. Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp2_0/util.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index da8aa9c..a234a7c 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -78,6 +78,7 @@ void fsp_print_header_info(const struct fsp_header *hdr) } +/* TODO: this won't work for SoC's that need to XIP certain modules. */ enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name, struct range_entry *range) @@ -118,6 +119,7 @@ enum cb_err fsp_load_binary(struct fsp_header *hdr, } /* Check if the binary load address is within expected range */ + /* TODO: this doesn't check the current running program footprint. */ if (range_entry_base(range) > hdr->image_base || range_entry_end(range) <= hdr->image_base + hdr->image_size) { printk(BIOS_ERR, "%s is outside of allowed range\n", name);

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New patch to review for coreboot: drivers/intel/fsp2_0: don't leak resources
by Aaron Durbin 08 Mar '16

08 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13958 -gerrit commit ce91643627525bb4fd569eb98df55cd71271c8a9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 8 11:01:17 2016 -0600 drivers/intel/fsp2_0: don't leak resources rdev_mmap() was not followed by rdev_munmap(), thus leaking resources. Fix the leak. Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp2_0/util.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 4fd4f68..da8aa9c 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -95,11 +95,20 @@ enum cb_err fsp_load_binary(struct fsp_header *hdr, /* Map just enough of the file to be able to parse the header. */ membase = rdev_mmap(&file_data, FSP_HDR_OFFSET, FSP_HDR_LEN); + + if (membase == NULL) { + printk(BIOS_ERR, "Could not mmap() '%s' FSP header.\n", name); + return CB_ERR; + } + if (fsp_identify(hdr, membase) != CB_SUCCESS) { + rdev_munmap(&file_data, membase); printk(BIOS_ERR, "%s did not have a valid FSP header\n", name); return CB_ERR; } + rdev_munmap(&file_data, membase); + fsp_print_header_info(hdr); /* Check if size specified in the header matches the cbfs file size */

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New patch to review for coreboot: soc/intel/apollolake: correct comment to reference top of CAR
by Aaron Durbin 08 Mar '16

08 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13957 -gerrit commit 9c565ab075a87bda2a5157cc64d1452552cba821 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 8 10:59:46 2016 -0600 soc/intel/apollolake: correct comment to reference top of CAR The memory provided to MemoryInit() for its own usage is at the top of the CAR region. Change-Id: I8685b5ab138182e24123b14cac6f7b32e5e784d2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 499417e..29a966e 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -142,7 +142,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) mupd->FspmConfig.FitTablePtr = read32((void*) FIT_POINTER); /* Reserve enough memory under TOLUD to save CBMEM header */ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); - /* Let FSPM use memory right at the bottom of CAR */ + /* Let FSPM use memory right at the top of CAR */ /* TODO: Add checks to see if we collide with other areas */ mupd->FspmArchUpd.StackBase = _car_region_end - CONFIG_FSPM_STACK_SIZE; mupd->FspmArchUpd.StackSize = CONFIG_FSPM_STACK_SIZE;

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New patch to review for coreboot: lib/memrange: add function to initialize range_entry
by Aaron Durbin 08 Mar '16

08 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13956 -gerrit commit 4d252e6c06782a7d0739ae5191752228d85d9680 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 8 10:47:18 2016 -0600 lib/memrange: add function to initialize range_entry In order to enforce the semantics of struct range_entry provide an init function, range_entry_init(), which performs the field initialization to adhere to the internal struture's assumptions. Change-Id: I24b9296e5bcf4775974c9a8d6326717608190215 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index a4f7742..759f8f5 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -37,6 +37,18 @@ struct range_entry { struct range_entry *next; }; +/* Initialize a range_entry with inclusive beginning address and exclusive + * end address along with the appropriate tag. */ +static inline void range_entry_init(struct range_entry *re, + resource_t incl_begin, resource_t excl_end, + unsigned long tag) +{ + re->begin = incl_begin; + re->end = excl_end - 1; + re->tag = tag; + re->next = NULL; +} + /* Return inclusive base address of memory range. */ static inline resource_t range_entry_base(const struct range_entry *r) {

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Patch set updated for coreboot: x86 chipsets: utilize x86_setup_mtrrs_with_detect()
by Aaron Durbin 08 Mar '16

08 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13936 -gerrit commit f655d0be4438e60b5c1d79761ab5fccb445d8ade Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:23:47 2016 -0600 x86 chipsets: utilize x86_setup_mtrrs_with_detect() For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 5 +---- src/cpu/intel/haswell/haswell_init.c | 3 +-- src/cpu/intel/model_2065x/model_2065x_init.c | 5 +---- src/cpu/intel/model_206ax/model_206ax_init.c | 5 +---- src/soc/intel/baytrail/cpu.c | 3 +-- src/soc/intel/braswell/cpu.c | 3 +-- src/soc/intel/broadwell/cpu.c | 3 +-- src/soc/intel/skylake/cpu.c | 3 +-- 8 files changed, 8 insertions(+), 22 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index f6e352e..da1ea2b 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -366,7 +366,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -381,9 +380,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5c34a30..b4bff83 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -717,8 +717,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d724842..4005b3d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -358,7 +358,6 @@ static void intel_cores_init(struct device *cpu) static void model_2065x_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -374,9 +373,7 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ()); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index ae2332e4..7575603 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -552,7 +552,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -567,9 +566,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9c69d16..6188689 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,8 +83,7 @@ void baytrail_init_cpus(device_t dev) void *default_smm_area; /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index feb9d9b..71af487 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -89,8 +89,7 @@ void soc_init_cpus(device_t dev) __FILE__, __func__, dev_name(dev)); /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 4a94c1d..5f3fb15 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -573,8 +573,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 327bee9..d154f0e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -343,8 +343,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }

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Patch set updated for coreboot: soc/intel/apollolake: Add chip initialization
by Andrey Petrov 08 Mar '16

08 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13911 -gerrit commit b2b0eedebbdb4340364dc34a71ba003282212db0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 4 21:41:13 2016 -0800 soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 110 ++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 32 ++++++++++ 3 files changed, 143 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b31f12..1b2efdf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += cpu.c +ramstage-y += chip.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c new file mode 100644 index 0000000..b464db0 --- /dev/null +++ b/src/soc/intel/apollolake/chip.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <soc/cpu.h> +#include <soc/pci_devs.h> + +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = apollolake_init_cpus, + .scan_bus = NULL, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + /* pretty liberal allowed range for now */ + struct range_entry range = {.begin=0x200000, .end=0xffffffff}; + fsp_silicon_init(&range); +} + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ + struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; + static struct soc_intel_apollolake_config *cfg; + + /* Load VBT before devicetree-specific config. */ + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + + struct device *dev = NB_DEVFN_ROOT; + if (!dev && !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; + silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; + silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; + silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; + silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; + silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; +} + +struct chip_operations soc_intel_apollolake_ops = { + CHIP_NAME("Intel Apollolake SOC") + .enable_dev = &enable_dev, + .init = &soc_init +}; + +static void fsp_notify_dummy(void *arg) +{ + + enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; + + if (fsp_notify(ph) != FSP_SUCCESS) + printk(BIOS_CRIT, "FspNotify failed!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h new file mode 100644 index 0000000..026fdda --- /dev/null +++ b/src/soc/intel/apollolake/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CHIP_H_ +#define _SOC_APOLLOLAKE_CHIP_H_ + +#define CLKREQ_DISABLED 0xf + +struct soc_intel_apollolake_config { + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + uint8_t pcie_rp0_clkreq_pin; + uint8_t pcie_rp1_clkreq_pin; + uint8_t pcie_rp2_clkreq_pin; + uint8_t pcie_rp3_clkreq_pin; + uint8_t pcie_rp4_clkreq_pin; + uint8_t pcie_rp5_clkreq_pin; +}; + +#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch set updated for coreboot: soc/intel/apollolake: Add chip initialization
by Andrey Petrov 08 Mar '16

08 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13911 -gerrit commit 385e76a0fb6fa6f4056adc6dbf5b4ee72b5c044c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 4 21:41:13 2016 -0800 soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 109 ++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 32 ++++++++++ 3 files changed, 142 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b31f12..1b2efdf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += cpu.c +ramstage-y += chip.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c new file mode 100644 index 0000000..3d11d79 --- /dev/null +++ b/src/soc/intel/apollolake/chip.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <soc/cpu.h> + +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = apollolake_init_cpus, + .scan_bus = NULL, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + /* pretty liberal allowed range for now */ + struct range_entry range = {.begin=0x200000, .end=0xffffffff}; + fsp_silicon_init(&range); +} + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ + struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; + static struct soc_intel_apollolake_config *cfg; + + /* Load VBT before devicetree-specific config. */ + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + + struct device *dev = NB_DEVFN_ROOT; + if (!dev && !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; + silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; + silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; + silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; + silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; + silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; +} + +struct chip_operations soc_intel_apollolake_ops = { + CHIP_NAME("Intel Apollolake SOC") + .enable_dev = &enable_dev, + .init = &soc_init +}; + +static void fsp_notify_dummy(void *arg) +{ + + enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; + + if (fsp_notify(ph) != FSP_SUCCESS) + printk(BIOS_CRIT, "FspNotify failed!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h new file mode 100644 index 0000000..026fdda --- /dev/null +++ b/src/soc/intel/apollolake/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CHIP_H_ +#define _SOC_APOLLOLAKE_CHIP_H_ + +#define CLKREQ_DISABLED 0xf + +struct soc_intel_apollolake_config { + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + uint8_t pcie_rp0_clkreq_pin; + uint8_t pcie_rp1_clkreq_pin; + uint8_t pcie_rp2_clkreq_pin; + uint8_t pcie_rp3_clkreq_pin; + uint8_t pcie_rp4_clkreq_pin; + uint8_t pcie_rp5_clkreq_pin; +}; + +#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch set updated for coreboot: crossgcc/buildgcc: Add comment about URLs and jenkins builder
by Martin Roth 08 Mar '16

08 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13955 -gerrit commit 2ac2d130379c0cc58b1e7d553d826b230451e52d Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 09:37:14 2016 -0700 crossgcc/buildgcc: Add comment about URLs and jenkins builder Add a comment to try to lower possible confusion later if the jenkins tool builder fails to build a new tool. The URLs for the packages that are downloaded are checked against known locations so that someone can't maliciously download a package from somewhere and run it on the build server. This provides a little bit of security, but could confuse someone if they don't realize it. Change-Id: I7858e3d86fc705b480f6792b6adf3d5349580e01 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index df9ac4a..eef71e5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -47,6 +47,9 @@ CLANG_VERSION=3.7.1 MAKE_VERSION=4.1 # GCC toolchain archive locations +# These are sanitized by the jenkins toolchain test builder, so if +# a completely new URL is added here, it probably needs to be added +# to the jenkins build as well, or the builder won't download it. GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"

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Patch merged into coreboot/master: soc/intel/quark: Set the UPD values for MemoryInit
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit d76d60bf56520ba64898b3fbc4953fc768fef7e8 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:30:48 2016 -0800 soc/intel/quark: Set the UPD values for MemoryInit Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13896 for details. -gerrit

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Patch set updated for coreboot: soc/intel/quark: Set the UPD values for MemoryInit
by Leroy P Leahy 08 Mar '16

08 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13896 -gerrit commit 123f4a8dbdacc50aa8159a253635319c994c4ff9 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:30:48 2016 -0800 soc/intel/quark: Set the UPD values for MemoryInit Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 10 ++ src/soc/intel/quark/chip.h | 12 +- src/soc/intel/quark/include/soc/pci_devs.h | 5 + src/soc/intel/quark/romstage/romstage.c | 54 +++++++++ src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 139 +++++++++++----------- 5 files changed, 149 insertions(+), 71 deletions(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 52e019b..c171aa0 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -16,6 +16,16 @@ chip soc/intel/quark + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdSmmTsegSize" = "0" # SMM Region size in MiB + + ############################################################ + # Enable the devices + ############################################################ + device domain 0 on # EDS Table 3 device pci 00.0 on end # 8086 0958 - Host Bridge diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 59c8793..fc9890f 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -19,11 +19,21 @@ #define _SOC_CHIP_H_ #include <stdint.h> +#include <fsp/util.h> #include <soc/pci_devs.h> #include <soc/pm.h> struct soc_intel_quark_config { - uint32_t junk; + /* + * MemoryInit: + * + * The following fields come from FspUpdVpd.h and are defined as PCDs + * for the FSP binary. Data for these fields comes from the board's + * devicetree.cb file which gets processed into static.c and then + * built into the coreboot image. The fields below contain retain + * the FSP PCD field name. + */ + UINT16 PcdSmmTsegSize; }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index d776e1e..4f577ce 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,6 +18,7 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ +#include <arch/io.h> #include <device/pci.h> #include <soc/QuarkNcSocId.h> @@ -31,4 +32,8 @@ # define HSUART1_DEV SIO1_DEV # define HSUART1_FUNC 5 +/* Platform Controller Unit */ +# define LPC_DEV_FUNC PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, \ + PCI_FUNCTION_NUMBER_QNC_LPC) + #endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 731e529..a089185 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -13,9 +13,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ #include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> +#include "../chip.h" #include <device/pci_def.h> #include <fsp/car.h> #include <fsp/util.h> @@ -47,3 +50,54 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + char *pdat_file; + size_t pdat_file_len; + const struct soc_intel_quark_config *config; + + /* Locate the pdat.bin file */ + pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW, + &pdat_file_len); + if (!pdat_file) { + printk(BIOS_DEBUG, + "Platform configuration file (pdat.bin) not found."); + pdat_file_len = 0; + } + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Set the parameters for MemoryInit */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); + upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->PcdSmmTsegSize : 0; + upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; + upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + fsp_display_upd_value("PcdSmmTsegSize", 2, + old->PcdSmmTsegSize, new->PcdSmmTsegSize); + fsp_display_upd_value("PcdPlatformDataBaseAddress", 4, + old->PcdPlatformDataBaseAddress, + new->PcdPlatformDataBaseAddress); + fsp_display_upd_value("PcdPlatformDataMaxLen", 4, + old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen); +} diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h index 2a11b20..b6b6cc4 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,139 +33,138 @@ are permitted provided that the following conditions are met: #ifndef __FSPUPDVPD_H__ #define __FSPUPDVPD_H__ -#pragma pack(push, 1) +#pragma pack(1) + + +// +// TODO - Port to fit Quark SoC. +// #define MAX_CHANNELS_NUM 2 #define MAX_DIMMS_NUM 2 typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ } DIMM_INFO; typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; } CHANNEL_INFO; typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; } FSP_SMBIOS_MEMORY_INFO; -/** UPD data structure for FspMemoryInitApi -**/ -typedef struct { + +typedef struct { /** Offset 0x0020 **/ UINT64 Signature; - -/** Offset 0x0028 - Revision - Revision version of the MemoryInitUpd Region +/** Offset 0x0028 **/ UINT8 Revision; +/** Offset 0x0029 + Tseg Size + Size of SMRAM memory reserved. +**/ + UINT8 PcdSmmTsegSize; +/** Offset 0x002A +**/ + UINT32 PcdPlatformDataBaseAddress; +/** Offset 0x002E +**/ + UINT32 PcdPlatformDataMaxLen; +/** Offset 0x0032 +**/ + UINT8 ReservedMemoryInitUpd[14]; } MEMORY_INIT_UPD; -/** UPD data structure for FspSiliconInitApi -**/ typedef struct { - -/** Offset 0x0200 +/** Offset 0x0040 **/ UINT64 Signature; - -/** Offset 0x0208 - Revision - Revision version of the SiliconInitUpd Region +/** Offset 0x0048 **/ UINT8 Revision; +/** Offset 0x0049 +**/ + UINT8 ReservedSiliconInitUpd[183]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ #define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ #define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ -/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. -**/ -typedef struct { - +typedef struct _UPD_DATA_REGION { /** Offset 0x0000 **/ UINT64 Signature; - -/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +/** Offset 0x0008 **/ UINT8 Revision; - /** Offset 0x0009 **/ UINT8 ReservedUpd0[7]; - -/** Offset 0x0010 - MemoryInitUpdOffset - This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +/** Offset 0x0010 **/ UINT32 MemoryInitUpdOffset; - -/** Offset 0x0014 - SiliconInitUpdOffset - This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +/** Offset 0x0014 **/ UINT32 SiliconInitUpdOffset; - /** Offset 0x0018 **/ UINT64 ReservedUpd1; - /** Offset 0x0020 **/ MEMORY_INIT_UPD MemoryInitUpd; - -/** Offset 0x0200 +/** Offset 0x0040 **/ SILICON_INIT_UPD SiliconInitUpd; - -/** Offset 0x03FA - RegionTerminator - This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +/** Offset 0x0100 **/ - UINT16 RegionTerminator; + UINT16 PcdRegionTerminator; } UPD_DATA_REGION; -#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ -#define FSP_IMAGE_REV 0x00000000 /* 0.0 */ - -/** VPD data structure -**/ -typedef struct { +#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ +#define FSP_IMAGE_REV 0x00000000 +typedef struct _VPD_DATA_REGION { /** Offset 0x0000 **/ UINT64 PcdVpdRegionSign; - -/** Offset 0x0008 - PcdImageRevision - This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +/** Offset 0x0008 + PcdImageRevision **/ UINT32 PcdImageRevision; - -/** Offset 0x000C - PcdUpdRegionOffset - This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +/** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[16]; +/** Offset 0x0020 +**/ + UINT32 PcdFspReservedMemoryLength; } VPD_DATA_REGION; -#pragma pack(pop) +#pragma pack() #endif

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coreboot-gerrit March 2016