coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch set updated for coreboot: mediatek/mt8173: Enable ARM trusted firmware integration
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13968 -gerrit commit 8759da59603a3b1b5fb63814ad8814b3c6a7fd04 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 8 21:42:00 2016 +0100 mediatek/mt8173: Enable ARM trusted firmware integration In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 91a8d4f..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8173 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING if SPI_FLASH

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Patch set updated for coreboot: google/oak: add event log
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13104 -gerrit commit 8fb18d9642d51765ad22786852086e429a1966f1 Author: CC Ma <cc.ma(a)mediatek.com> Date: Tue Sep 15 17:33:38 2015 +0800 google/oak: add event log BRANCH=none BUG=none TEST=boot to shell on Rev3 Change-Id: Ifca80705e392ce171ef33bf98ef787e3cd5ffd6b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56 Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b Original-Signed-off-by: CC Ma <cc.ma(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303207 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 1545418..544041f 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -20,6 +20,7 @@ #include <delay.h> #include <device/device.h> +#include <elog.h> #include <gpio.h> #include <soc/bl31_plat_params.h> #include <soc/mt6391.h> @@ -27,6 +28,7 @@ #include <soc/pinmux.h> #include <soc/pll.h> #include <soc/usb.h> +#include <vendorcode/google/chromeos/chromeos.h> static void register_da9212_to_bl31(void) { @@ -170,6 +172,9 @@ static void mainboard_init(device_t dev) configure_backlight(); configure_usb(); configure_bl31(); + + elog_init(); + elog_add_boot_reason(); } static void mainboard_enable(device_t dev)

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Patch set updated for coreboot: mediatek/mt8173: Provide I2C bus initialization API
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13107 -gerrit commit ee61810f17d93b84d59147409210100114be4abb Author: jun.gao <jun.gao(a)mediatek.com> Date: Thu Dec 17 16:59:55 2015 +0800 mediatek/mt8173: Provide I2C bus initialization API BRANCH=none BUG=none TEST=build pass and boot to oak kernel Change-Id: I8aa9ca0fce804cc1682947b7e184781dd5d437f7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9 Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9 Original-Signed-off-by: jun.gao <jun.gao(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319031 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Makefile.inc | 3 ++- src/soc/mediatek/mt8173/i2c.c | 30 ++++++++++++++++++++---------- src/soc/mediatek/mt8173/include/soc/i2c.h | 2 ++ 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 7b6dc75..e23ccb9 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -17,6 +17,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c +bootblock-y += i2c.c bootblock-y += pll.c bootblock-y += spi.c bootblock-y += timer.c @@ -64,7 +65,7 @@ ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c mtcmos.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c -ramstage-y += pmic_wrap.c mt6391.c +ramstage-y += pmic_wrap.c mt6391.c i2c.c ramstage-y += gpio.c ramstage-y += wdt.c ramstage-y += pll.c diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 52b1fb2..6c04ec3 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -88,6 +88,26 @@ static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs) udelay(50); } +void mtk_i2c_bus_init(uint8_t bus) +{ + uint8_t sample_div; + uint8_t step_div; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(i2c)); + + /* Calculate i2c frequency */ + sample_div = 1; + step_div = div_round_up(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); + assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 | + (step_div - 1)); +} + static inline void mtk_i2c_dump_info(uint8_t bus) { struct mt8173_i2c_regs *regs; @@ -127,9 +147,6 @@ static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_seg *seg, uint32_t read_len = 0; uint8_t *write_buffer = NULL; uint8_t *read_buffer = NULL; - uint8_t sample_div; - uint8_t step_div; - uint32_t i2c_freq; struct mt8173_i2c_regs *regs; struct mt8173_i2c_dma_regs *dma_regs; struct stopwatch sw; @@ -163,13 +180,6 @@ static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_seg *seg, break; } - /* Calculate i2c frequency */ - sample_div = 1; - step_div = div_round_up(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); - i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); - assert(sample_div < 8 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz); - write32(&regs->timing, (sample_div - 1) << 8 | (step_div - 1)); - /* Clear interrupt status */ write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | I2C_HS_NACKERR); diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index 2d8a5db..5f46e9c 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -127,4 +127,6 @@ enum { I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 }; +void mtk_i2c_bus_init(uint8_t bus); + #endif /* SOC_MEDIATEK_MT8173_I2C_H */

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Patch set updated for coreboot: google/oak: Initialize DRAM
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13106 -gerrit commit 14e7e7114ad8c11c715f2af2345b9448ea0c7960 Author: Peter Kao <peter.kao(a)mediatek.com> Date: Fri Jul 31 17:11:14 2015 +0800 google/oak: Initialize DRAM BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6 Original-Signed-off-by: Peter Kao <peter.kao(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292692 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Makefile.inc | 2 +- src/mainboard/google/oak/romstage.c | 8 ++ src/mainboard/google/oak/sdram_configs.c | 49 +++++++++ .../oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 116 +++++++++++++++++++++ .../oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 116 +++++++++++++++++++++ .../google/oak/sdram_inf/sdram-unused.inc | 3 + 6 files changed, 293 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index c7f0401..f0bbb7b 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -22,7 +22,7 @@ verstage-y += chromeos.c verstage-y += memlayout.ld romstage-y += chromeos.c -romstage-y += romstage.c +romstage-y += romstage.c sdram_configs.c romstage-y += memlayout.ld romstage-y += boardid.c diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index a60a50d..d72693f 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -19,6 +19,7 @@ #include <arch/mmu.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <delay.h> #include <program_loading.h> @@ -26,6 +27,7 @@ #include <symbols.h> #include <timestamp.h> +#include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/rtc.h> @@ -39,7 +41,13 @@ void main(void) rtc_boot(); + /* init memory */ + mt_mem_init(get_sdram_config()); + mt8173_mmu_after_dram(); + /* should be called after memory init */ + cbmem_initialize_empty(); + run_ramstage(); } diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c new file mode 100644 index 0000000..f2b5362 --- /dev/null +++ b/src/mainboard/google/oak/sdram_configs.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <console/console.h> +#include <soc/emi.h> +#include <stdlib.h> + +static const struct mt8173_sdram_params sdram_configs[] = { +#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0000 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */ +}; + +const struct mt8173_sdram_params *get_sdram_config(void) +{ + u32 ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) + || sdram_configs[ramcode].type == TYPE_INVALID) + die("Invalid RAMCODE."); + + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc new file mode 100644 index 0000000..4e728e3 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -0,0 +1,116 @@ +{ /* 2GB (8Gb + 8Gb) for single rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 19, + + .ca_train = { + [CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2}, + [CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3} + }, + + .ca_train_center = { + [CHANNEL_A] = 2, + [CHANNEL_B] = 0 + }, + + .wr_level = { + [CHANNEL_A] = { 5, 6, 5, 6}, + [CHANNEL_B] = { 6, 6, 6, 4} + }, + + .gating_win = { + [CHANNEL_A] = { + { 28, 56}, + { 0, 0} + }, + [CHANNEL_B] = { + { 28, 56}, + { 0, 0} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x110e0b0b, + [CHANNEL_B] = 0x12100d0d + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01040302, + 0x04010300, + 0x02040300, + 0x04030302, + 0x04070400, + 0x07070707, + 0x05070808, + 0x00010404 + }, + [CHANNEL_B] = { + 0x05060604, + 0x04010400, + 0x05070300, + 0x05030504, + 0x07090500, + 0x08090707, + 0x080a0a0a, + 0x02000604 + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c0, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0x20102017, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc new file mode 100644 index 0000000..4c58286 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -0,0 +1,116 @@ +{ /* 2GB (8Gb + 8Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0}, + [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7} + }, + + .ca_train_center = { + [CHANNEL_A] = 3, + [CHANNEL_B] = 3 + }, + + .wr_level = { + [CHANNEL_A] = { 8, 10, 6, 8}, + [CHANNEL_B] = { 9, 9, 7, 6} + }, + + .gating_win = { + [CHANNEL_A] = { + { 27, 64}, + { 27, 72} + }, + [CHANNEL_B] = { + { 27, 72}, + { 27, 72} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x08080908, + [CHANNEL_B] = 0x0b0b060b + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01010300, + 0x06030002, + 0x01010201, + 0x03020002, + 0x00010103, + 0x02010201, + 0x02040200, + 0x02020201 + }, + [CHANNEL_B] = { + 0x00020202, + 0x02020202, + 0x01020201, + 0x01010100, + 0x01010101, + 0x01000002, + 0x02000201, + 0x00010101, + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0x50535057, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, diff --git a/src/mainboard/google/oak/sdram_inf/sdram-unused.inc b/src/mainboard/google/oak/sdram_inf/sdram-unused.inc new file mode 100644 index 0000000..21b2859 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-unused.inc @@ -0,0 +1,3 @@ +{ + .type = TYPE_INVALID, +},

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Patch set updated for coreboot: google/oak: Initialize i2c bus timing register for TPM and external buck
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13108 -gerrit commit b19fb3cfee1835190269554ac2e7ec78e9ddb317 Author: jun.gao <jun.gao(a)mediatek.com> Date: Thu Dec 17 16:59:55 2015 +0800 google/oak: Initialize i2c bus timing register for TPM and external buck BRANCH=none BUG=none TEST=build pass and boot to oak kernel Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9 Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9 Original-Signed-off-by: jun.gao <jun.gao(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319031 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/bootblock.c | 4 ++++ src/mainboard/google/oak/mainboard.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index efb489f..49cf5dd 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <delay.h> #include <soc/gpio.h> +#include <soc/i2c.h> #include <soc/mt6391.h> #include <soc/pericfg.h> #include <soc/pinmux.h> @@ -78,6 +79,9 @@ void bootblock_mainboard_init(void) /* set nor related GPIO */ nor_set_gpio_pinmux(); + /* Init i2c bus 2 Timing register for TPM */ + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); setup_chromeos_gpios(); diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 544041f..1713c9b 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -23,6 +23,7 @@ #include <elog.h> #include <gpio.h> #include <soc/bl31_plat_params.h> +#include <soc/i2c.h> #include <soc/mt6391.h> #include <soc/mtcmos.h> #include <soc/pinmux.h> @@ -53,6 +54,9 @@ static void register_da9212_to_bl31(void) }, }; register_bl31_param(&param_da9212.h); + + /* Init i2c bus Timing register for da9212 */ + mtk_i2c_bus_init(param_da9212.i2c_bus); #endif } @@ -66,6 +70,9 @@ static void register_mt6311_to_bl31(void) .i2c_bus = 1, }; register_bl31_param(&param_mt6311.h); + + /* Init i2c bus Timing register for mt6311 */ + mtk_i2c_bus_init(param_mt6311.i2c_bus); #endif } @@ -119,6 +126,9 @@ static void configure_audio(void) mt6391_gpio_output(MT6391_KP_COL4, 1); mt6391_gpio_output(MT6391_KP_COL5, 1); + /* Init i2c bus Timing register for audio codecs */ + mtk_i2c_bus_init(0); + /* set I2S clock to 48KHz */ mt_pll_set_aud_div(48 * KHz); }

1 0

Patch set updated for coreboot: nyan: Fix timestamps and CBFS SPI integration
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13832 -gerrit commit 4a9efea0105ce9d982f40ae1017f9843ecde4121 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Feb 17 16:12:46 2016 -0800 nyan: Fix timestamps and CBFS SPI integration Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/nyan/Kconfig | 3 + src/mainboard/google/nyan_big/Kconfig | 3 + src/mainboard/google/nyan_blaze/Kconfig | 3 + src/soc/nvidia/tegra124/bootblock.c | 3 + src/soc/nvidia/tegra124/include/soc/memlayout.ld | 3 +- src/soc/nvidia/tegra124/spi.c | 92 ------------------------ 6 files changed, 14 insertions(+), 93 deletions(-) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 8f0c9de..a5ecf84 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_NVIDIA_TEGRA124 select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select TEGRA124_MODEL_CD570M @@ -26,6 +27,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index b6f84f6..fdd40f6 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_NVIDIA_TEGRA124 select MAINBOARD_HAS_CHROMEOS select BOARD_ID_AUTO + select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select TEGRA124_MODEL_CD570M @@ -27,6 +28,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 0fd763d..f28fb24 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARM select BOARD_ID_AUTO + select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select SOC_NVIDIA_TEGRA124 @@ -28,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cebe405..2a526a7 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -24,6 +24,7 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <soc/pinmux.h> #include <soc/power.h> +#include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> static void run_next_stage(void *entry) @@ -81,6 +82,8 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); + timestamp_init(0); + run_romstage(); } diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index c3f5f4e..5bab362 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -33,7 +33,8 @@ SECTIONS STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 24K) VERSTAGE(0x40016000, 72K) - ROMSTAGE(0x40028000, 96K) + ROMSTAGE(0x40028000, 95K) + TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) DRAM_START(0x80000000) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5f7861..d5be4a6 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -798,69 +798,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return ret; } -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -#define JEDEC_FAST_READ_DUAL 0x3b -#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05 - -static struct spi_slave *boot_slave; - -static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest, - size_t offset, size_t count) -{ - u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE]; - unsigned int read_cmd_bytes; - int ret = count; - struct tegra_spi_channel *channel; - - channel = to_tegra_spi(boot_slave->bus); - - if (channel->dual_mode) { - /* - * Command 0x3b will interleave data only, command 0xbb will - * interleave the address as well. It's nice to see the address - * plainly when debugging, and we're mostly concerned with - * large transfers so the optimization of using 0xbb isn't - * really worthwhile. - */ - spi_read_cmd[0] = JEDEC_FAST_READ_DUAL; - spi_read_cmd[4] = 0x00; /* dummy byte */ - read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE; - } else { - spi_read_cmd[0] = JEDEC_READ; - read_cmd_bytes = JEDEC_READ_OUTSIZE; - } - spi_read_cmd[1] = (offset >> 16) & 0xff; - spi_read_cmd[2] = (offset >> 8) & 0xff; - spi_read_cmd[3] = offset & 0xff; - - spi_claim_bus(boot_slave); - - if (spi_xfer(boot_slave, spi_read_cmd, - read_cmd_bytes, NULL, 0) < 0) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", - __func__, sizeof(spi_read_cmd)); - goto tegra_spi_cbfs_read_exit; - } - - if (channel->dual_mode) { - setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - } - if (spi_xfer(boot_slave, NULL, 0, dest, count)) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", - __func__, count); - } - if (channel->dual_mode) - clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - -tegra_spi_cbfs_read_exit: - /* de-assert /CS */ - spi_release_bus(boot_slave); - return ret; -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct tegra_spi_channel *channel = to_tegra_spi(bus); @@ -869,32 +806,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) return &channel->slave; } - -static const struct region_device_ops tegra_spi_ops = { - .mmap = mmap_helper_rdev_mmap, - .munmap = mmap_helper_rdev_munmap, - .readat = tegra_spi_readat, -}; - -static struct mmap_helper_region_device mdev = - MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} - -void boot_device_init(void) -{ - struct tegra_spi_channel *boot_chan; - - boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1]; - boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT; - -#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1 - boot_chan->dual_mode = 1; -#endif - boot_slave = &boot_chan->slave; - - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); -}

1 0

New patch to review for coreboot: mediatek/mt8173: Enable ARM trusted firmware integration
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13968 -gerrit commit 8804491cf80877411ce58780572d048f8a116b42 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 8 21:42:00 2016 +0100 mediatek/mt8173: Enable ARM trusted firmware integration In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 91a8d4f..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8173 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING if SPI_FLASH

1 0

Patch set updated for coreboot: mediatek/mt8173: Add soc ARM Trusted Firmware support
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13100 -gerrit commit bd2a12b77a9cc01bd57f14ff84ced5493528d399 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Fri Jul 31 17:11:00 2015 +0800 mediatek/mt8173: Add soc ARM Trusted Firmware support We define a mechanism to pass board specific parameters to BL31. The idea is BL31 doesn't need to have the board revision knowledge, it only needs to process the board specific parameters to initialize and control specific hardware. In this way, we can support different boards with same BL31 binary. [pg: add the code, but don't actually enable the support yet, because it relies on code that still needs to be merged to arm-trusted-firmware.] BRANCH=none BUG=none TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got different board arguments in ARM TF Change-Id: I9ea3ce6c8f79dd427be67f30bc940d2038173b81 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292678 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Makefile.inc | 5 ++++ src/soc/mediatek/mt8173/bl31_plat_params.c | 30 ++++++++++++++++++++++ .../mediatek/mt8173/include/soc/bl31_plat_params.h | 24 +++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index e23ccb9..b35e1f6 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -73,6 +73,11 @@ ramstage-y += rtc.c ramstage-y += usb.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c + +BL31_MAKEARGS += PLAT=mt8173 MEDIATEK_MEM_CONFIG=SRAM_192K MEDIATEK_DA9212=1 \ + MEDIATEK_MT6311=1 + ################################################################################ # Generate the actual coreboot bootblock code diff --git a/src/soc/mediatek/mt8173/bl31_plat_params.c b/src/soc/mediatek/mt8173/bl31_plat_params.c new file mode 100644 index 0000000..025c202 --- /dev/null +++ b/src/soc/mediatek/mt8173/bl31_plat_params.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arm_tf.h> +#include <assert.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = (void *)plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + return (void *)plat_params; +} diff --git a/src/soc/mediatek/mt8173/include/soc/bl31_plat_params.h b/src/soc/mediatek/mt8173/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..c1ea885 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/bl31_plat_params.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#if IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) +#include <arm-trusted-firmware/plat/mediatek/mt8173/include/plat_params.h> + +void register_bl31_param(struct bl31_plat_param *param); +#endif + +#endif /* __BL31_PLAT_PARAMS_H__ */

1 0

Patch set updated for coreboot: google/oak: Add soc ARM Trusted Firmware support
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13101 -gerrit commit c7a7df62b5d3629b840ae9e17afe73596d8b7ec1 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Fri Jul 31 17:11:00 2015 +0800 google/oak: Add soc ARM Trusted Firmware support We define a mechanism to pass board specific parameters to BL31. The idea is BL31 doesn't need to have the board revision knowledge, it only needs to process the board specific parameters to initialize and control specific hardware. In this way, we can support different boards with same BL31 binary. BRANCH=none BUG=none TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got different board arguments in ARM TF Change-Id: I0df2c6d7d1ffac7d443511c3317c142efeb5701e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292678 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 52d6bd4..1545418 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -21,12 +21,65 @@ #include <device/device.h> #include <gpio.h> +#include <soc/bl31_plat_params.h> #include <soc/mt6391.h> #include <soc/mtcmos.h> #include <soc/pinmux.h> #include <soc/pll.h> #include <soc/usb.h> +static void register_da9212_to_bl31(void) +{ +#if IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) + static struct bl31_da9212_param param_da9212 = { + .h = { + .type = PARAM_CLUSTER1_DA9212, + }, + .i2c_bus = 1, + .ic_en = { + .type = PARAM_GPIO_SOC, + .polarity = PARAM_GPIO_ACTIVE_HIGH, + .index = PAD_UCTS2, + }, + .en_a = { + .type = PARAM_GPIO_MT6391, + .polarity = PARAM_GPIO_ACTIVE_HIGH, + .index = MT6391_KP_ROW4, + }, + .en_b = { + .type = PARAM_GPIO_NONE, + }, + }; + register_bl31_param(&param_da9212.h); +#endif +} + +static void register_mt6311_to_bl31(void) +{ +#if IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) + static struct bl31_mt6311_param param_mt6311 = { + .h = { + .type = PARAM_CLUSTER1_MT6311, + }, + .i2c_bus = 1, + }; + register_bl31_param(&param_mt6311.h); +#endif +} + +static void configure_bl31(void) +{ + switch (board_id()) { + case 2: + register_da9212_to_bl31(); + break; + default: + /* rev-3 and rev-4 use mt6311 as external buck */ + register_mt6311_to_bl31(); + break; + } +} + static void configure_audio(void) { mtcmos_audio_power_on(); @@ -116,6 +169,7 @@ static void mainboard_init(device_t dev) configure_audio(); configure_backlight(); configure_usb(); + configure_bl31(); } static void mainboard_enable(device_t dev)

1 0

Patch set updated for coreboot: mt8173: add SPI NOR support
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13102 -gerrit commit 536df77509448cb68095ec2ff69e17350ce3c04d Author: mtk05962 <bayi.cheng(a)mediatek.com> Date: Fri Oct 16 13:42:49 2015 +0800 mt8173: add SPI NOR support BRANCH=none BUG=none TEST=boot oak to kernel on rev1 Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18 Original-Signed-off-by: mtk05962 <bayi.cheng(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292693 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 8 +- src/mainboard/google/oak/bootblock.c | 31 ++++ src/soc/mediatek/mt8173/Makefile.inc | 8 +- src/soc/mediatek/mt8173/cbfs.c | 21 --- src/soc/mediatek/mt8173/flash_controller.c | 184 +++++++++++++++++++++ .../mediatek/mt8173/include/soc/flash_controller.h | 80 +++++++++ src/soc/mediatek/mt8173/spi.c | 8 + 7 files changed, 314 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index cc64ab9..ce783f3 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -20,14 +20,16 @@ config BOARD_SPECIFIC_OPTIONS select SOC_MEDIATEK_MT8173 select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 + select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select SPI_FLASH config CHROMEOS - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_FLASH select EC_SOFTWARE_SYNC select VIRTUAL_DEV_SWITCH @@ -55,6 +57,10 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config BOOT_MEDIA_SPI_BUS + int + default 9 + config EC_GOOGLE_CHROMEEC_BOARDNAME string default "oak" diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 3d78551..efb489f 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -33,6 +33,34 @@ static void i2c_set_gpio_pinmux(void) gpio_set_mode(PAD_SCL4, PAD_SCL4_FUNC_SCL4); } +static void nor_set_gpio_pinmux(void) +{ + /* Set driving strength of EINT4~EINT9 to 8mA + * 0: 2mA + * 1: 4mA + * 2: 8mA + * 3: 16mA + */ + /* EINT4: 0x10005B20[14:13] */ + clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); + /* EINT5~EINT9: 0x10005B30[2:1] */ + clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), + + gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(PAD_EINT6, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(PAD_EINT7, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(PAD_EINT8, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(PAD_EINT9, GPIO_PULL_ENABLE, GPIO_PULL_UP); + + gpio_set_mode(PAD_EINT4, PAD_EINT4_FUNC_SFWP_B); + gpio_set_mode(PAD_EINT5, PAD_EINT5_FUNC_SFOUT); + gpio_set_mode(PAD_EINT6, PAD_EINT6_FUNC_SFCS0); + gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SFHOLD); + gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SFIN); + gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SFCK); +} + void bootblock_mainboard_early_init(void) { /* Clear UART0 power down signal */ @@ -47,6 +75,9 @@ void bootblock_mainboard_init(void) /* set i2c related gpio */ i2c_set_gpio_pinmux(); + /* set nor related GPIO */ + nor_set_gpio_pinmux(); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); setup_chromeos_gpios(); diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index cbc9855..97053a5 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -16,7 +16,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c -bootblock-y += cbfs.c +bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-y += pll.c bootblock-y += spi.c bootblock-y += timer.c @@ -38,11 +38,11 @@ verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += timer.c verstage-y += wdt.c -verstage-y += cbfs.c +verstage-$(CONFIG_SPI_FLASH) += flash_controller.c ################################################################################ -romstage-y += cbfs.c +romstage-$(CONFIG_SPI_FLASH) += flash_controller.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c @@ -57,7 +57,7 @@ romstage-y += rtc.c ramstage-y += cbmem.c ramstage-y += spi.c -ramstage-y += cbfs.c +ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c mtcmos.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/mediatek/mt8173/cbfs.c b/src/soc/mediatek/mt8173/cbfs.c deleted file mode 100644 index 25348fc..0000000 --- a/src/soc/mediatek/mt8173/cbfs.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -const struct region_device *boot_device_ro(void) -{ - return NULL; -} diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c new file mode 100644 index 0000000..3cd81a2 --- /dev/null +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <timer.h> +#include <soc/flash_controller.h> + +#define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff) + +static int polling_cmd(u32 val) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + + while ((read32(&mt8173_nor->cmd) & val) != 0) { + if (stopwatch_expired(&sw)) + return -1; + } + + return 0; +} + +static int mt8173_nor_execute_cmd(u8 cmdval) +{ + u8 val = cmdval & ~(SFLASH_AUTOINC); + + write8(&mt8173_nor->cmd, cmdval); + return polling_cmd(val); +} + +static int sflashhw_read_flash_status(u8 *value) +{ + if (mt8173_nor_execute_cmd(SFLASH_READSTATUS)) + return -1; + + *value = read8(&mt8173_nor->rdsr); + return 0; +} + +static int wait_for_write_done(void) +{ + struct stopwatch sw; + u8 reg; + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + + while (sflashhw_read_flash_status(&reg) == 0) { + if (!(reg & SFLASH_WRITE_IN_PROGRESS)) + return 0; + if (stopwatch_expired(&sw)) + return -1; + } + + return -1; +} + +/* set serial flash program address */ +static void set_sfpaddr(u32 addr) +{ + write8(&mt8173_nor->radr[2], get_nth_byte(addr, 2)); + write8(&mt8173_nor->radr[1], get_nth_byte(addr, 1)); + write8(&mt8173_nor->radr[0], get_nth_byte(addr, 0)); +} + +static int sector_erase(int offset) +{ + if (wait_for_write_done()) + return -1; + + write8(&mt8173_nor->prgdata[5], SFLASH_OP_WREN); + write8(&mt8173_nor->cnt, 8); + mt8173_nor_execute_cmd(SFLASH_PRG_CMD); + + write8(&mt8173_nor->prgdata[5], SECTOR_ERASE_CMD); + write8(&mt8173_nor->prgdata[4], get_nth_byte(offset, 2)); + write8(&mt8173_nor->prgdata[3], get_nth_byte(offset, 1)); + write8(&mt8173_nor->prgdata[2], get_nth_byte(offset, 0)); + write8(&mt8173_nor->cnt, 32); + mt8173_nor_execute_cmd(SFLASH_PRG_CMD); + + if (wait_for_write_done()) + return -1; + + return 0; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(65535, buf_len); +} + +static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) +{ + u8 *buffer = (u8 *)buf; + + set_sfpaddr(addr); + while (len) { + if (mt8173_nor_execute_cmd(SFLASH_RD_TRIGGER | SFLASH_AUTOINC)) + return -1; + + *buffer++ = read8(&mt8173_nor->rdata); + len--; + } + return 0; +} + +static int nor_write(struct spi_flash *flash, u32 addr, size_t len, + const void *buf) +{ + const u8 *buffer = (const u8 *)buf; + + set_sfpaddr(addr); + while (len) { + write8(&mt8173_nor->wdata, *buffer); + if (mt8173_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC)) + return -1; + + if (wait_for_write_done()) + return -1; + buffer++; + len--; + } + return 0; +} + +static int nor_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + int sector_start = offset; + int sector_num = (u32)len / flash->sector_size; + + while (sector_num) { + if (!sector_erase(sector_start)) { + sector_start += flash->sector_size; + sector_num--; + } else { + printk(BIOS_WARNING, "Erase failed at 0x%x!\n", + sector_start); + return -1; + } + } + return 0; +} + +struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi) +{ + static struct spi_flash flash = {0}; + + if (flash.spi) + return &flash; + + write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE); + flash.spi = spi; + flash.name = "mt8173 flash controller"; + flash.write = nor_write; + flash.erase = nor_erase; + flash.read = nor_read; + flash.status = 0; + flash.sector_size = 0x1000; + flash.erase_cmd = SECTOR_ERASE_CMD; + flash.size = CONFIG_ROM_SIZE; + return &flash; +} diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h new file mode 100644 index 0000000..2527d6b --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ +#define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ + +#include <cbfs.h> +#include <spi-generic.h> +#include <stdint.h> +#include <soc/addressmap.h> + +enum { + SFLASH_POLLINGREG_US = 500000, + SFLASH_WRBUF_SIZE = 128, + SFLASHNAME_LENGTH = 16, + SFLASH_WRITE_IN_PROGRESS = 1, + SFLASH_COMMAND_ENABLE = 0x30, + + /* NOR flash controller commands */ + SFLASH_RD_TRIGGER = 1 << 0, + SFLASH_READSTATUS = 1 << 1, + SFLASH_PRG_CMD = 1 << 2, + SFLASH_WR_TRIGGER = 1 << 4, + SFLASH_WRITESTATUS = 1 << 5, + SFLASH_AUTOINC = 1 << 7, + /* NOR flash commands */ + SFLASH_OP_WREN = 0x6, + SECTOR_ERASE_CMD = 0x20, + SFLASH_UNPROTECTED = 0x0 +}; + +/* register Offset */ +struct mt8173_nor_regs { + u32 cmd; + u32 cnt; + u32 rdsr; + u32 rdata; + u32 radr[3]; + u32 wdata; + u32 prgdata[6]; + u32 shreg[10]; + u32 cfg[2]; + u32 shreg10; + u32 status[5]; + u32 timing; + u32 flash_cfg; + u32 reserved2[3]; + u32 sf_time; + u32 reserved3; + u32 diff_addr; + u32 del_sel[2]; + u32 intrstus; + u32 intren; + u32 pp_ctl; + u32 cfg3; + u32 chksum_ctl; + u32 chksum; + u32 aaicmd; + u32 wrprot; + u32 radr3; + u32 read_dual; + u32 delsel[3]; +}; +check_member(mt8173_nor_regs, delsel[2], 0xD8); +static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE; + +struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi); +#endif /* __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index c3c71c3..dc674f3 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -23,6 +23,7 @@ #include <string.h> #include <timer.h> #include <soc/addressmap.h> +#include <soc/flash_controller.h> #include <soc/gpio.h> #include <soc/pinmux.h> #include <soc/pll.h> @@ -161,6 +162,7 @@ static void mtk_spi_dump_data(const char *name, const uint8_t *data, struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct mtk_spi_bus *eslave; + static struct spi_slave slave; switch (bus) { case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: @@ -168,6 +170,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) assert(read32(&eslave->regs->spi_cfg0_reg) != 0); spi_sw_reset(eslave->regs); return &eslave->slave; + case CONFIG_BOOT_MEDIA_SPI_BUS: + slave.bus = bus; + slave.cs = cs; + slave.force_programmer_specific = 1; + slave.programmer_specific_probe = &mt8173_nor_flash_probe; + return &slave; default: die ("wrong bus number.\n"); };

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coreboot-gerrit March 2016