coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Add a driver for the parade ps8640
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13981 -gerrit commit e78fbb5cda71c338ccc8212035d094d588c8b73d Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Fri Jan 8 15:59:46 2016 +0800 Add a driver for the parade ps8640 BRANCH=none BUG=none TEST=none Change-Id: Icf397ce2ffdaed5048367daf2086c067984fea0a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b5a88793ccfc46af196300791a300be67b70f5b1 Original-Change-Id: I75adf2688c9c8b9a2338f7dee5d0ac10e7181529 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321056 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/parade/Kconfig | 1 + src/drivers/parade/Makefile.inc | 1 + src/drivers/parade/ps8640/Kconfig | 20 +++++++++ src/drivers/parade/ps8640/Makefile.inc | 16 +++++++ src/drivers/parade/ps8640/ps8640.c | 79 ++++++++++++++++++++++++++++++++++ src/drivers/parade/ps8640/ps8640.h | 45 +++++++++++++++++++ 6 files changed, 162 insertions(+) diff --git a/src/drivers/parade/Kconfig b/src/drivers/parade/Kconfig index be80bb8..7fe74df 100644 --- a/src/drivers/parade/Kconfig +++ b/src/drivers/parade/Kconfig @@ -14,3 +14,4 @@ ## source src/drivers/parade/ps8625/Kconfig +source src/drivers/parade/ps8640/Kconfig diff --git a/src/drivers/parade/Makefile.inc b/src/drivers/parade/Makefile.inc index 0470763..06367c1 100644 --- a/src/drivers/parade/Makefile.inc +++ b/src/drivers/parade/Makefile.inc @@ -14,3 +14,4 @@ ## subdirs-$(CONFIG_DRIVER_PARADE_PS8625) += ps8625/ +subdirs-$(CONFIG_DRIVER_PARADE_PS8640) += ps8640/ diff --git a/src/drivers/parade/ps8640/Kconfig b/src/drivers/parade/ps8640/Kconfig new file mode 100644 index 0000000..f0d71bb --- /dev/null +++ b/src/drivers/parade/ps8640/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config DRIVER_PARADE_PS8640 + bool + default n + help + Parade PS8640 MIPI DSI to eDP Converter diff --git a/src/drivers/parade/ps8640/Makefile.inc b/src/drivers/parade/ps8640/Makefile.inc new file mode 100644 index 0000000..9bfe1e7 --- /dev/null +++ b/src/drivers/parade/ps8640/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += ps8640.c diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c new file mode 100644 index 0000000..08de2ee --- /dev/null +++ b/src/drivers/parade/ps8640/ps8640.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <device/i2c.h> +#include <edid.h> +#include <console/console.h> +#include <timer.h> + +#include "ps8640.h" + +int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + int ret; + u8 edid[EDID_LENGTH * 2]; + u32 edid_size; + + i2c_writeb(bus, chip + 2, PAGE2_I2C_BYPASS, + EDID_I2C_ADDR | I2C_BYPASS_EN); + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0, edid, EDID_LENGTH); + + if (ret != 0) { + printk(BIOS_INFO, "Failed to read EDID.\n"); + return -1; + } + + /* check if edid have extension flag, and read additional EDID data */ + if (edid[EDID_EXTENSION_FLAG]) { + edid_size += EDID_LENGTH; + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, + &edid[EDID_LENGTH], EDID_LENGTH); + if (ret != 0) { + printk(BIOS_INFO, "Failed to read EDID ext block.\n"); + return -1; + } + } + + if (decode_edid(edid, edid_size, out)) { + printk(BIOS_INFO, "Failed to decode EDID.\n"); + return -1; + } + + return 0; +} + +int ps8640_init(uint8_t bus, uint8_t chip) +{ + u8 set_vdo_done; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, 350); + + do { + i2c_readb(bus, chip + 2, PAGE2_GPIO_H, &set_vdo_done); + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Failed to init ps8640.\n"); + return -1; + } + } while ((set_vdo_done & PS_GPIO9) != PS_GPIO9); + + i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); + i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_DIS); + i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); + i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_EN); + + return 0; +} diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h new file mode 100644 index 0000000..9e483b6 --- /dev/null +++ b/src/drivers/parade/ps8640/ps8640.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <edid.h> +#include <types.h> + +#ifndef _PS8640_H_ +#define _PS8640_H_ + +enum { + PAGE2_GPIO_L = 0xa6, + PAGE2_GPIO_H = 0xa7, + PAGE2_I2C_BYPASS = 0xea, + PS_GPIO9 = BIT(1), + I2C_BYPASS_EN = BIT(7), + + PAGE3_SET_ADD = 0xfe, + PAGE3_SET_VAL = 0xff, + VDO_CTL_ADD = 0x13, + VDO_DIS = 0x18, + VDO_EN = 0x1c, +}; + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +int ps8640_init(uint8_t bus, uint8_t chip); +int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out); +#endif +

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Patch set updated for coreboot: mediatek/mt8173: Enable ARM trusted firmware integration
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13968 -gerrit commit 5dfce9f383b59c885e724e1b533b94e787f26bd9 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 8 21:42:00 2016 +0100 mediatek/mt8173: Enable ARM trusted firmware integration In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 91a8d4f..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8173 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING if SPI_FLASH

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Patch set updated for coreboot: Makefile: Add build-time overlap check for programs loaded after coreboot
by Julius Werner 08 Mar '16

08 Mar '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13949 -gerrit commit 2534e7f5b571e0139e1d77a34ddb082ddeff9027 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Mar 7 17:55:43 2016 -0800 Makefile: Add build-time overlap check for programs loaded after coreboot On non-x86 platforms, coreboot uses the memlayout.ld mechanism to statically allocate the different memory regions it needs and guarantees at build time that there are no dangerous overlaps between them. At the end of its (ramstage) execution, however, it usually loads a payload (and possibly other platform-specific components) that is not integrated into the coreboot build system and therefore cannot provide the same overlap guarantees through memlayout.ld. This creates a dangerous memory hazard where a new component could be loaded over memory areas that are still in use by the code-loading ramstage and lead to arbitrary memory corruption bugs. This patch fills this gap in our build-time correctness guarantees by adding the necessary checks as a new intermediate Makefile target on route to assembling the final image. It will parse the memory footprint information of the payload (and other platform-specific post-ramstage components) from CBFS and compare it to a list of memory areas known to be still in use during late ramstage, generating a build failure in case of a possible hazard. BUG=chrome-os-partner:48008 TEST=Built Oak while moving critical regions in the way of BL31 or the payload, observing the desired build-time errors. Built Nyan, Jerry and Falco without issues for good measure. Change-Id: I3ebd2c1caa4df959421265e26f9cab2c54909b68 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- Makefile.inc | 46 +++++++++++++++++++++++++++++++++++++++++++++ src/arch/arm/Makefile.inc | 4 ++++ src/arch/arm64/Makefile.inc | 8 ++++++++ src/arch/mips/Makefile.inc | 4 ++++ src/arch/riscv/Makefile.inc | 4 ++++ 5 files changed, 66 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 68012d9..0849d65 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -842,6 +842,52 @@ board_id-type := raw $(obj)/board_id: printf $(CONFIG_BOARD_ID_STRING) > $@ +# Ensure that no payload segment overlaps with memory regions used by ramstage +# (not for x86 since it can relocate itself in that case) +ifneq ($(CONFIG_ARCH_X86),y) +check-ramstage-overlap-regions := ramstage +check-ramstage-overlap-files := +ifneq ($(CONFIG_PAYLOAD_NONE),y) +check-ramstage-overlap-files += $(CONFIG_CBFS_PREFIX)/payload +endif + +# will output one or more lines of "<load address in hex> <memlen in decimal>" +cbfs-get-segments-cmd = $(CBFSTOOL) $(obj)/coreboot.pre print -v | sed -n \ + '\%$(1)%,\%^[^ ]\{4\}%s% .*load: $0x[0-9a-fA-F]*$,.*length: [0-9]*/$[0-9]*$.*%\1 \2%p' + +ramstage-symbol-addr-cmd = $(OBJDUMP_ramstage) -t $(objcbfs)/ramstage.elf | \ + sed -n '/ $(1)$$/s/^$[0-9a-fA-F]*$ .*/0x\1/p' + +check-ramstage-overlaps: $(obj)/coreboot.pre + programs=$$($(foreach file,$(check-ramstage-overlap-files), \ + $(call cbfs-get-segments-cmd,$(file)) ; )) ; \ + regions=$$($(foreach region,$(check-ramstage-overlap-regions), \ + echo $(region) ; \ + $(call ramstage-symbol-addr-cmd,_$(region)) ; \ + $(call ramstage-symbol-addr-cmd,_e$(region)) ; )) ; \ + pstart= ; pend= ; \ + for x in $$programs; do \ + if [ -z $$pstart ]; then pstart=$$(($$x)) ; continue ; fi ; \ + pend=$$(($$pstart + $$x)) ; \ + rname= ; rstart= ; rend= ; \ + for y in $$regions ; do \ + if [ -z $$rname ]; then rname=$$y ; continue ; fi ; \ + if [ -z $$rstart ]; then rstart=$$(($$y)) ; continue ; fi ; \ + rend=$$(($$y)) ; \ + if [ $$pstart -lt $$rend -a $$rstart -lt $$pend ]; then \ + echo "ERROR: Ramstage region _$$rname overlapped by:" \ + $(check-ramstage-overlap-files) ; \ + exit 1 ; \ + fi ; \ + rname= ; rstart= ; rend= ; \ + done ; \ + pstart= ; pend= ; \ + done + +INTERMEDIATE+=check-ramstage-overlaps +PHONY+=check-ramstage-overlaps +endif + junit.xml: echo "Building $(UTIL)" echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index b04a3db..d9c88c0 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) CBFSTOOL_PRE1_OPTS = -m arm -s $(CONFIG_CBFS_SIZE) endif +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y) +check-ramstage-overlap-regions += postram_cbfs_cache stack ttb +endif + ifeq ($(CONFIG_ARCH_ARM),y) subdirs-y += libgcc/ subdirs-y += armv4/ armv7/ diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index f44ee51..dffdd9c 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -33,6 +33,10 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) CBFSTOOL_PRE1_OPTS = -m arm64 -s $(CONFIG_CBFS_SIZE) endif +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) +check-ramstage-overlap-regions += postram_cbfs_cache stack ttb +endif + ################################################################################ # bootblock ################################################################################ @@ -182,6 +186,8 @@ $(BL31_CBFS)-type := stage $(BL31_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(BL31_CBFS) +check-ramstage-overlap-files += $(BL31_CBFS) + ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y) SECURE_OS_FILE := $(CONFIG_ARM64_SECURE_OS_FILE) @@ -190,6 +196,8 @@ $(SECURE_OS_FILE_CBFS)-file := $(SECURE_OS_FILE) $(SECURE_OS_FILE_CBFS)-type := stage cbfs-files-y += $(SECURE_OS_FILE_CBFS) +check-ramstage-overlap-files += $(SECURE_OS_FILE_CBFS) + endif # CONFIG_ARM64_USE_SECURE_OS endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index a037525..0901388 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -22,6 +22,10 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) CBFSTOOL_PRE1_OPTS = -m mips -s $(CONFIG_CBFS_SIZE) endif +ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) +check-ramstage-overlap-regions += stack +endif + ############################################################################### # bootblock ############################################################################### diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 2d4d7e6..4abaf58 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -19,6 +19,10 @@ riscv_flags = -I$(src)/arch/riscv/ riscv_asm_flags = +ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) +check-ramstage-overlap-regions += stack +endif + ################################################################################ ## bootblock ################################################################################

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Patch set updated for coreboot: payloads: Enable building depthcharge as part of the coreboot build
by Stefan Reinauer 08 Mar '16

08 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10924 -gerrit commit 0f016d262dce87de72be7547adb1ac740f5a4fb7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 15 10:24:18 2015 -0700 payloads: Enable building depthcharge as part of the coreboot build For CHROMEOS builds, depthcharge can be built automatically. This dependency exists because depthcharge without vboot and subsequent signing of the image doesn't work very well, and both are keyed to that flag as well. Change-Id: Id0195bd3b4e454f382782106d6512469106daac5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/external/Makefile.inc | 8 +++++ payloads/external/depthcharge/Kconfig | 7 ++++ payloads/external/depthcharge/Kconfig.name | 8 +++++ payloads/external/depthcharge/Makefile.inc | 52 ++++++++++++++++++++++++++++++ 4 files changed, 75 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 557de2a..a2020da 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -25,6 +25,9 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) PAYLOAD_CONFIG=payloads/external/FILO/filo/.config PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h endif +ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) +# TODO: fill in config and version +endif cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_config payload_config-file := $(PAYLOAD_CONFIG) @@ -57,6 +60,11 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf: seabios payloads/external/SeaBIOS/seabios/.config: seabios payloads/external/SeaBIOS/seabios/out/autoversion.h: seabios +depthcharge: + $(MAKE) -C payloads/external/depthcharge -f Makefile.inc + +payloads/external/depthcharge/depthcharge/build/depthcharge.elf: depthcharge + filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig new file mode 100644 index 0000000..84b36e5 --- /dev/null +++ b/payloads/external/depthcharge/Kconfig @@ -0,0 +1,7 @@ +if PAYLOAD_DEPTHCHARGE + +config PAYLOAD_FILE + string + default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" + +endif diff --git a/payloads/external/depthcharge/Kconfig.name b/payloads/external/depthcharge/Kconfig.name new file mode 100644 index 0000000..bc564ec --- /dev/null +++ b/payloads/external/depthcharge/Kconfig.name @@ -0,0 +1,8 @@ +config PAYLOAD_DEPTHCHARGE + bool "Depthcharge" + depends on CHROMEOS + help + Select this option if you want to build a coreboot image + with a depthcharge payload. + + See http://coreboot.org/Payloads for more information. diff --git a/payloads/external/depthcharge/Makefile.inc b/payloads/external/depthcharge/Makefile.inc new file mode 100644 index 0000000..f3a4ca3 --- /dev/null +++ b/payloads/external/depthcharge/Makefile.inc @@ -0,0 +1,52 @@ +TAG-y=origin/master + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES +unexport src srck obj objk + +BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR)) + +all: build + +depthcharge: + echo " Cloning depthcharge from Git" + git clone https://chromium.googlesource.com/chromiumos/platform/depthcharge + +fetch: depthcharge + cd depthcharge; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + then echo " Fetching new commits from the depthcharge git repo"; git fetch; fi + +checkout: fetch + echo " Checking out depthcharge revision $(TAG-y)" + cd depthcharge; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + +config: checkout + echo " CONFIG depthcharge $(TAG-y)" + cp depthcharge/board/$(BOARD)/defconfig depthcharge/.config + yes "" | $(MAKE) -C depthcharge oldconfig + +build: config + echo " MAKE depthcharge $(TAG-y)" + cp ../../libpayload/configs/defconfig.$(BOARD) ../../libpayload/.config + yes "" | $(MAKE) -C ../../libpayload oldconfig + $(MAKE) -C ../../libpayload + $(MAKE) -C ../../libpayload install DESTDIR=installed + export VERSION=$$(cd depthcharge && \ + git describe --tags --long --dirty 2>/dev/null || \ + echo "unknown") ; \ + cd depthcharge && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(abspath ../../libpayload/installed/libpayload) \ + VB_SOURCE=3rdparty/vboot defconfig + cd depthcharge && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(abspath ../../libpayload/installed/libpayload) \ + VB_SOURCE=../../../../3rdparty/vboot build/depthcharge.elf + +clean: + test -d depthcharge/out && rm -rf depthcharge/out || exit 0 + +distclean: + rm -rf depthcharge + +.PHONY: checkout config build clean distclean clone fetch

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Patch set updated for coreboot: payloads: Enable building depthcharge as part of the coreboot build
by Martin Roth 08 Mar '16

08 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10924 -gerrit commit 467faead8b7786ee4af4dc58b6ac503b2e2df659 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 15 10:24:18 2015 -0700 payloads: Enable building depthcharge as part of the coreboot build For CHROMEOS builds, depthcharge can be built automatically. This dependency exists because depthcharge without vboot and subsequent signing of the image doesn't work very well, and both are keyed to that flag as well. Change-Id: Id0195bd3b4e454f382782106d6512469106daac5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/external/Makefile.inc | 8 +++++ payloads/external/depthcharge/Kconfig | 7 ++++ payloads/external/depthcharge/Kconfig.name | 8 +++++ payloads/external/depthcharge/Makefile.inc | 52 ++++++++++++++++++++++++++++++ 4 files changed, 75 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 557de2a..a2020da 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -25,6 +25,9 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) PAYLOAD_CONFIG=payloads/external/FILO/filo/.config PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h endif +ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) +# TODO: fill in config and version +endif cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_config payload_config-file := $(PAYLOAD_CONFIG) @@ -57,6 +60,11 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf: seabios payloads/external/SeaBIOS/seabios/.config: seabios payloads/external/SeaBIOS/seabios/out/autoversion.h: seabios +depthcharge: + $(MAKE) -C payloads/external/depthcharge -f Makefile.inc + +payloads/external/depthcharge/depthcharge/build/depthcharge.elf: depthcharge + filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig new file mode 100644 index 0000000..84b36e5 --- /dev/null +++ b/payloads/external/depthcharge/Kconfig @@ -0,0 +1,7 @@ +if PAYLOAD_DEPTHCHARGE + +config PAYLOAD_FILE + string + default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" + +endif diff --git a/payloads/external/depthcharge/Kconfig.name b/payloads/external/depthcharge/Kconfig.name new file mode 100644 index 0000000..bc564ec --- /dev/null +++ b/payloads/external/depthcharge/Kconfig.name @@ -0,0 +1,8 @@ +config PAYLOAD_DEPTHCHARGE + bool "Depthcharge" + depends on CHROMEOS + help + Select this option if you want to build a coreboot image + with a depthcharge payload. + + See http://coreboot.org/Payloads for more information. diff --git a/payloads/external/depthcharge/Makefile.inc b/payloads/external/depthcharge/Makefile.inc new file mode 100644 index 0000000..00cca0c --- /dev/null +++ b/payloads/external/depthcharge/Makefile.inc @@ -0,0 +1,52 @@ +TAG-y=origin/master + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES +unexport src srck obj objk + +BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR)) + +all: build + +depthcharge: + echo " Cloning depthcharge from Git" + git clone https://chromium.googlesource.com/chromiumos/platform/depthcharge + +fetch: depthcharge + cd depthcharge; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + then echo " Fetching new commits from the depthcharge git repo"; git fetch; fi + +checkout: fetch + echo " Checking out depthcharge revision $(TAG-y)" + cd depthcharge; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + +config: checkout + echo " CONFIG depthcharge $(TAG-y)" + cp depthcharge/board/$(BOARD)/defconfig depthcharge/.config + yes "" | $(MAKE) -C depthcharge oldconfig + +build: config + echo " MAKE depthcharge $(TAG-y)" + cp ../../libpayload/configs/defconfig.$(BOARD) ../../libpayload/.config + yes "" | $(MAKE) -C ../../libpayload oldconfig + $(MAKE) -C ../../libpayload + $(MAKE) -C ../../libpayload install DESTDIR=installed + export VERSION=$$(cd depthcharge && \ + git describe --tags --long --dirty 2>/dev/null || \ + echo "unknown") ; \ + cd depthcharge && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(abspath ../../libpayload/installed/libpayload) \ + VB_SOURCE=3rdparty/vboot defconfig + cd depthcharge && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(abspath ../../libpayload/installed/libpayload) \ + VB_SOURCE=../../../../3rdparty/vboot build/depthcharge.elf + +clean: + test -d depthcharge/out && rm -rf depthcharge/out || exit 0 + +distclean: + rm -rf depthcharge + +.PHONY: checkout config build clean distclean clone fetch

1 0

New patch to review for coreboot: intel/fsp1.1: Mark graphics init done after SiliconInit phase
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13986 -gerrit commit 7eed854b0a561b545296e2991c59150503b21b35 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 7 13:21:56 2016 -0800 intel/fsp1.1: Mark graphics init done after SiliconInit phase If the VBT was provided to the FSP GOP driver then graphics init will be done as part of SiliconInit step and we can mark that when it is completed. This will result in the "oprom" flag being set properly in the coreboot gpio table and the netboot firmware will have video. BUG=chrome-os-partner:50864 BRANCH=glados TEST=boot image.net.bin on chell and get working graphics without being setuck in a reboot loop thinking graphics needs to be started when it already has been. Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331301 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240) Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5 Original-Reviewed-on: https://chromium-review.googlesource.com/331355 --- src/drivers/intel/fsp1_1/ramstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 277b609..1e4873e 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootmode.h> #include <arch/acpi.h> #include <cbmem.h> #include <cbfs.h> @@ -140,6 +141,11 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) timestamp_add_now(TS_FSP_SILICON_INIT_END); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + /* Mark graphics init done after SiliconInit if VBT was provided */ + if (IS_ENABLED(CONFIG_GOP_SUPPORT) && + silicon_init_params.GraphicsConfigPtr) + gfx_set_init_done(1); + display_hob_info(fsp_info_header); soc_after_silicon_init(); }

1 0

New patch to review for coreboot: soc/intel/skylake: add option to statically clock gate 8254 timer
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13985 -gerrit commit 2b4e1928e2f9076f4a10e38e7b8765805b82a92e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 25 17:17:35 2016 -0600 soc/intel/skylake: add option to statically clock gate 8254 timer In order to save more power by shutting down clocks add the ability to optionally clock gate the 8254 programmable interrupt timer. When doing this the platforms lose their "PC"-ness which certain payloads and OSes rely on such as SeaBIOS. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Enabled option on chell. Noted the bit is set upon booting. Change-Id: I01f9d177bbde417d1efec2e16656a07dcebccbde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 662575aa6a63656dedfa0ce1f202f5fac0205477 Original-Change-Id: Ib4a613cf1c28fc96c36fa2987c4b58a05beab178 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329411 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331171 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/skylake/chip.h | 2 ++ src/soc/intel/skylake/include/soc/pcr.h | 3 +++ src/soc/intel/skylake/lpc.c | 13 +++++++++++++ 3 files changed, 18 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e18b45a..ca902ae 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -335,6 +335,8 @@ struct soc_intel_skylake_config { * 0 - Don't Send, 1 - Send */ u8 SendVrMbxCmd; + /* Statically clock gate 8254 PIT. */ + u8 clock_gate_8254; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index 8a46cd1..c3e8d83 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -60,6 +60,9 @@ #define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 /* PIRQH Routing Control Register*/ #define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 +/* ITSS Power reduction control */ +#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 +# define CGE8254 (1 << 2) /* IO Trap PCRs */ /* Trap status Register */ diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index e47026c..cebd836 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -154,6 +154,18 @@ static const struct reg_script pch_misc_init_script[] = { REG_SCRIPT_END }; +static void clock_gate_8254(struct device *dev) +{ + config_t *config = dev->chip_info; + const uint32_t cge8254_mask = CGE8254; + + if (!config->clock_gate_8254) + return; + + pcr_andthenor32(PID_ITSS, R_PCH_PCR_ITSS_ITSSPRC, + ~cge8254_mask, cge8254_mask); +} + static void lpc_init(struct device *dev) { /* Legacy initialization */ @@ -165,6 +177,7 @@ static void lpc_init(struct device *dev) pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); + clock_gate_8254(dev); } static void pch_lpc_add_mmio_resources(device_t dev)

1 0

New patch to review for coreboot: vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13984 -gerrit commit 7a60f8c91e1cfa0ee1945966a1e08d3db5901f5d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 14:44:01 2016 -0600 vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0 The previous copy of FspUpdVpd.h was not up to date w.r.t. the FSP release being used for skylake boards. Fix that. BUG=chrome-os-partner:50863 BRANCH=None TEST=Built and booted on chell. Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7 Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331290 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- .../intel/fsp/fsp1_1/skylake/FspUpdVpd.h | 155 +++++++++++---------- 1 file changed, 80 insertions(+), 75 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h index b03214c..45f2099 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -370,9 +370,15 @@ typedef struct { **/ UINT32 FspCarSize; -/** Offset 0x015C +/** Offset 0x015C - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x015D **/ - UINT8 ReservedMemoryInitUpd[164]; + UINT8 ReservedMemoryInitUpd[163]; } MEMORY_INIT_UPD; /** UPD data structure for FspSiliconInitApi @@ -477,7 +483,7 @@ typedef struct { UINT8 HsioMessaging; /** Offset 0x0227 - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. This must be enabled if Integrated Touch (iTouch) is supported. 0: disable, 1: enable $EN_DIS **/ UINT8 Heci3Enabled; @@ -654,304 +660,304 @@ typedef struct { **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x02EB -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x02EC - Enable PCIE RP +/** Offset 0x02EB - Enable PCIE RP Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpEnable[20]; -/** Offset 0x0300 - Enable PCIE RP PMSCI +/** Offset 0x02FF - Enable PCIE RP PMSCI Indicate whether the root port power manager SCI is enabled - 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpPmSci[20]; -/** Offset 0x0314 - Enable PCIE RP CLKREQ Support +/** Offset 0x0313 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpClkReqSupport[20]; -/** Offset 0x0328 - Configure CLKREQ Number +/** Offset 0x0327 - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpClkReqNumber[20]; -/** Offset 0x033C - Enable LAN +/** Offset 0x033B - Enable LAN Enable/Disable LAN controller. $EN_DIS **/ UINT8 EnableLan; -/** Offset 0x033D - LAN LTR Programming +/** Offset 0x033C - LAN LTR Programming Enable/Disable LTR capabilty of PCH internal LAN. $EN_DIS **/ UINT8 LanLtrEnable; -/** Offset 0x033E - SATA eSATASpeedLimit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable. +/** Offset 0x033D - SATA eSATASpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable. $EN_DIS **/ UINT8 eSATASpeedLimit; -/** Offset 0x033F - SATA RST RAID0 +/** Offset 0x033E - SATA RST RAID0 Enable/Disable RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x0340 - SATA RST RAID1 +/** Offset 0x033F - SATA RST RAID1 Enable/Disable RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x0341 - SATA RST RAID10 +/** Offset 0x0340 - SATA RST RAID10 Enable/Disable RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x0342 - SATA RST RAID5 +/** Offset 0x0341 - SATA RST RAID5 Enable/Disable RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x0343 - Skip Multi-Processor Initialization +/** Offset 0x0342 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize, 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0344 - Enable PCIE RP HotPlug +/** Offset 0x0343 - Enable PCIE RP HotPlug Enable/disable PCIE Root Ports HogPlug. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpHotPlug[20]; -/** Offset 0x0358 - Enable PCIE RP Function Swap +/** Offset 0x0357 - Enable PCIE RP Function Swap Enable/disable PCIE RP function swap. 0: disable, 1: enable. It allows BIOS to use root port function number swapping when root port of function 0 is disabled. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage. Disabling function swap may have adverse impact on power management. $EN_DIS **/ UINT8 RpFunctionSwap; -/** Offset 0x0359 - USB2 Port Over Current Configuration +/** Offset 0x0358 - USB2 Port Over Current Configuration Configure over current pin assignment per USB2 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0369 - USB3 Port Over Current Configuration +/** Offset 0x0368 - USB3 Port Over Current Configuration Configure over current pin assignment per USB3 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0373 -**/ - UINT8 UnusedUpdSpace7[1]; - -/** Offset 0x0374 - Psi1Threshold +/** Offset 0x0372 - Psi1Threshold Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 Psi1Threshold[5]; -/** Offset 0x037E - Psi2Threshold +/** Offset 0x037C - Psi2Threshold Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 Psi2Threshold[5]; -/** Offset 0x0388 - Psi3Threshold +/** Offset 0x0386 - Psi3Threshold State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 Psi3Threshold[5]; -/** Offset 0x0392 - Psi3Enable +/** Offset 0x0390 - Psi3Enable Power State 3 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 Psi3Enable[5]; -/** Offset 0x0397 - Psi4Enable +/** Offset 0x0395 - Psi4Enable Power State 4 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 Psi4Enable[5]; -/** Offset 0x039C - ImonSlope +/** Offset 0x039A - ImonSlope Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 ImonSlope[5]; -/** Offset 0x03A1 - ImonOffset +/** Offset 0x039F - ImonOffset Imon offset correction. Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 ImonOffset[5]; -/** Offset 0x03A6 - IccMax +/** Offset 0x03A4 - IccMax VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 IccMax[5]; -/** Offset 0x03B0 - VrVoltageLimit +/** Offset 0x03AE - VrVoltageLimit VR Voltage Limit. Range is 0-7999mV. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 VrVoltageLimit[5]; -/** Offset 0x03BA - VrConfigEnable +/** Offset 0x03B8 - VrConfigEnable BIOS configuration of VR 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 VrConfigEnable[5]; -/** Offset 0x03BF -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x03C0 - CPU S3 Resume Hob Data - CPU S3 Resume Hob Data +/** Offset 0x03BD - CPU S3 Resume Data + CPU S3 Resume Data passed from the FSP CPU S3 Resume HOB during normal boot. **/ UINT32 CpuS3ResumeHobData; -/** Offset 0x03C4 - CpuS3ResumeMtrrData +/** Offset 0x03C1 - CpuS3ResumeMtrrData Pointer CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData; -/** Offset 0x03C8 - CpuS3ResumeMtrrDataSize +/** Offset 0x03C5 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data. **/ UINT16 CpuS3ResumeMtrrDataSize; -/** Offset 0x03CA - Lock Down Config Global Smi +/** Offset 0x03C7 - Lock Down Config Global Smi Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 LockDownConfigGlobalSmi; -/** Offset 0x03CB - Lock Down Config Bios Interface +/** Offset 0x03C8 - Lock Down Config Bios Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. Top Swap bit and the General Control and Status Registers Boot BIOS Straps. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 LockDownConfigBiosInterface; -/** Offset 0x03CC - Lock Down Config Bios Lock +/** Offset 0x03C9 - Lock Down Config Bios Lock When enabled, the BIOS Region can only be modified from SMM after EndOfDxe protocol is installed. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 LockDownConfigBiosLock; -/** Offset 0x03CD - Lock Down Config Spi Eiss +/** Offset 0x03CA - Lock Down Config Spi Eiss Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also in order to write to BIOS regions of SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The BIOS must set the EISS bit while BIOS Guard support is enabled. Value 0: Clear EISS bit, 1: Set EISS bit. $EN_DIS **/ UINT8 LockDownConfigSpiEiss; -/** Offset 0x03CE - Subsystem Vendor ID +/** Offset 0x03CB - Subsystem Vendor ID Subsystem Vendor ID of the PCH devices. **/ UINT16 PchConfigSubSystemVendorId; -/** Offset 0x03D0 - Subsystem ID +/** Offset 0x03CD - Subsystem ID Subsystem ID of the PCH devices. **/ UINT16 PchConfigSubSystemId; -/** Offset 0x03D2 - Wol Enable Override +/** Offset 0x03CF - Wol Enable Override Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 WakeConfigWolEnableOverride; -/** Offset 0x03D3 - Pcie Wake From DeepSx +/** Offset 0x03D0 - Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 WakeConfigPcieWakeFromDeepSx; -/** Offset 0x03D4 - Power Management DeepSxPolicy +/** Offset 0x03D1 - Power Management DeepSxPolicy Deep Sx Policy. Values 0: PchDeepSxPolDisable, 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn. 0 : 0x06 **/ UINT8 PmConfigDeepSxPol; -/** Offset 0x03D5 - Power Management SlpS3MinAssert +/** Offset 0x03D2 - Power Management SlpS3MinAssert SLP_S3 Minimum Assertion Width Policy. Values 0: PchSlpS360us, 1: PchSlpS31ms, 2: PchSlpS350ms, 3: PchSlpS32s. 0 : 0x03 **/ UINT8 PmConfigSlpS3MinAssert; -/** Offset 0x03D6 - Power Management SlpS4MinAssert +/** Offset 0x03D3 - Power Management SlpS4MinAssert SLP_S4 Minimum Assertion Width Policy. Values 0: PchSlpS4PchTime, 1: PchSlpS41s, 2: PchSlpS42s, 3: PchSlpS43s, 4: PchSlpS44s. 0 : 0x04 **/ UINT8 PmConfigSlpS4MinAssert; -/** Offset 0x03D7 - Power Management SlpSusMinAssert +/** Offset 0x03D4 - Power Management SlpSusMinAssert SLP_SUS Minimum Assertion Width Policy. Values 0: PchSlpSus0ms, 1: PchSlpSus500ms, 2: PchSlpSus1s, 3: PchSlpSus4s. 0 : 0x03 **/ UINT8 PmConfigSlpSusMinAssert; -/** Offset 0x03D8 - Power Management SlpAMinAssert +/** Offset 0x03D5 - Power Management SlpAMinAssert SLP_A Minimum Assertion Width Policy. Values 0: PchSlpA0ms, 1: PchSlpA4s, 2: PchSlpA98ms, 3: PchSlpA2s. 0 : 0x03 **/ UINT8 PmConfigSlpAMinAssert; -/** Offset 0x03D9 - Power Management Pci Clock Run +/** Offset 0x03D6 - Power Management Pci Clock Run This member describes whether or not the PCI ClockRun feature of PCH should be enabled. Values 0: Disabled, 1: Enabled $EN_DIS **/ UINT8 PmConfigPciClockRun; -/** Offset 0x03DA - Power Management SLP_X Stretching After SUS Well +/** Offset 0x03D7 - Power Management SLP_X Stretching After SUS Well SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled $EN_DIS **/ UINT8 PmConfigSlpStrchSusUp; -/** Offset 0x03DB - Power Management Power Button Override Period +/** Offset 0x03D8 - Power Management Power Button Override Period PCH power button override period. Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s. 0 : 0x05 **/ UINT8 PmConfigPwrBtnOverridePeriod; -/** Offset 0x03DC - Power Management Power Reset Power Cycle Duration +/** Offset 0x03D9 - Power Management Power Reset Power Cycle Duration Reset Power Cycle Duration could be customized in the unit of second. PCH HW default is 4 seconds, and range is 1~4 seconds. Values: 0x0 - 0s, 0x1 - 1s, 0x2 - 2s, 0x3 - 3s, 0x4 - 4s. 0 : 0x04 **/ UINT8 PmConfigPwrCycDur; -/** Offset 0x03DD - PCH Serial IRQ Configuration +/** Offset 0x03DA - PCH Serial IRQ Configuration Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled $EN_DIS **/ UINT8 SerialIrqConfigSirqEnable; -/** Offset 0x03DE - PCH Serial IRQ Mode Select +/** Offset 0x03DB - PCH Serial IRQ Mode Select Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode. 0 : 0x01 **/ UINT8 SerialIrqConfigSirqMode; -/** Offset 0x03DF - PCH Serial IRQ Start Frame Pulse Width +/** Offset 0x03DC - PCH Serial IRQ Start Frame Pulse Width Start Frame Pulse Width. Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. 0 : 0x02 **/ UINT8 SerialIrqConfigStartFramePulse; -/** Offset 0x03E0 - PSF Unlock +/** Offset 0x03DD - PSF Unlock The PSF registers will be locked before 3rd party code execution. This policy unlock the PSF space. NOTE: Do not set this policy "PsfUnlock" unless necessary. $EN_DIS **/ UINT8 PsfUnlock; -/** Offset 0x03E1 - IO voltage for I2C controllers +/** Offset 0x03DE - IO voltage for I2C controllers Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. **/ UINT8 SerialIoI2cVoltage[6]; -/** Offset 0x03E7 +/** Offset 0x03E4 - Enable 8254 Static Clock Gating in early POST time + Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this. + $EN_DIS +**/ + UINT8 Early8254ClockGatingEnable; + +/** Offset 0x03E5 - Enable VR specific mailbox command + When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. This for FSP only. 0 - Don't Send, 1 - Send + $EN_DIS +**/ + UINT8 SendVrMbxCmd; + +/** Offset 0x03E6 **/ - UINT8 ReservedSiliconInitUpd[19]; + UINT8 ReservedSiliconInitUpd[20]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ @@ -1004,7 +1010,7 @@ typedef struct { } UPD_DATA_REGION; #define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */ -#define FSP_IMAGE_REV 0x01080100 +#define FSP_IMAGE_REV 0x01090000 /** VPD data structure **/ @@ -1019,8 +1025,7 @@ typedef struct { **/ UINT32 PcdImageRevision; -/** Offset 0x000C - PcdUpdRegionOffset - This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +/** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; @@ -1029,7 +1034,7 @@ typedef struct { UINT8 UnusedVpdSpace0[32]; /** Offset 0x0030 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing **/ UINT8 PcdSerialIoUartDebugEnable;

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New patch to review for coreboot: glados/chell: send an extra VR mailbox command
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13983 -gerrit commit 87aba39817fe1022751f06ec62f4acd5ead0bd1c Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Feb 24 14:56:32 2016 +0530 glados/chell: send an extra VR mailbox command MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 15 +++++++++------ src/mainboard/google/glados/devicetree.cb | 15 +++++++++------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index bb925ce..428779a 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -63,7 +63,7 @@ chip soc/intel/skylake #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 0 | 0 | 0 | 0 | 0 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 34A | 35A | 35A | @@ -75,7 +75,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), @@ -88,7 +88,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -101,7 +101,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -114,7 +114,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -127,7 +127,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -174,6 +174,9 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 89fcff8..c4b89af 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -63,7 +63,7 @@ chip soc/intel/skylake #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 0 | 0 | 0 | 0 | 0 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 34A | 35A | 35A | @@ -75,7 +75,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), @@ -88,7 +88,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -101,7 +101,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -114,7 +114,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -127,7 +127,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -174,6 +174,9 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + device cpu_cluster 0 on device lapic 0 on end end

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New patch to review for coreboot: soc/intel/skylake: add option to enable VR specific mailbox cmd
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13982 -gerrit commit e7061011fb9024acfef300f9bef7a3e6c103cbf2 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Feb 24 14:31:40 2016 +0530 soc/intel/skylake: add option to enable VR specific mailbox cmd Adding an option to enable VR specific mailbox command. When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917 Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329393 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.c | 4 ++++ src/soc/intel/skylake/chip.h | 11 +++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b5bcc65..dbf7785 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -410,6 +410,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->TcoIrqSelect = config->TcoIrqSelect; /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; + params->SendVrMbxCmd = config->SendVrMbxCmd; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, @@ -1011,6 +1012,9 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, original->SerialIoI2cVoltage[5], params->SerialIoI2cVoltage[5]); + fsp_display_upd_value("SendVrMbxCmd", 1, + original->SendVrMbxCmd, + params->SendVrMbxCmd); } static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 6203916..e18b45a 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -312,8 +312,8 @@ struct soc_intel_skylake_config { */ u8 SerialIrqConfigStartFramePulse; u8 FspSkipMpInit; - - /* VrConfig Settings for 5 domains + /* + * VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ @@ -328,6 +328,13 @@ struct soc_intel_skylake_config { u8 PmTimerDisabled; /* Intel Speed Shift Technology */ u8 speed_shift_enable; + /* + * Enable VR specific mailbox command + * When set, an extra VR mailbox command specifically + * for the MPS IMPV8 VR will be sent. + * 0 - Don't Send, 1 - Send + */ + u8 SendVrMbxCmd; }; typedef struct soc_intel_skylake_config config_t;

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coreboot-gerrit March 2016