coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13984 -gerrit commit 825c530dceb6658299fdf7fc39e8002a589756c7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 14:44:01 2016 -0600 vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0 The previous copy of FspUpdVpd.h was not up to date w.r.t. the FSP release being used for skylake boards. Fix that. BUG=chrome-os-partner:50863 BRANCH=None TEST=Built and booted on chell. Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7 Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331290 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- .../intel/fsp/fsp1_1/skylake/FspUpdVpd.h | 155 +++++++++++---------- 1 file changed, 80 insertions(+), 75 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h index b03214c..45f2099 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -370,9 +370,15 @@ typedef struct { **/ UINT32 FspCarSize; -/** Offset 0x015C +/** Offset 0x015C - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x015D **/ - UINT8 ReservedMemoryInitUpd[164]; + UINT8 ReservedMemoryInitUpd[163]; } MEMORY_INIT_UPD; /** UPD data structure for FspSiliconInitApi @@ -477,7 +483,7 @@ typedef struct { UINT8 HsioMessaging; /** Offset 0x0227 - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. This must be enabled if Integrated Touch (iTouch) is supported. 0: disable, 1: enable $EN_DIS **/ UINT8 Heci3Enabled; @@ -654,304 +660,304 @@ typedef struct { **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x02EB -**/ - UINT8 UnusedUpdSpace6[1]; - -/** Offset 0x02EC - Enable PCIE RP +/** Offset 0x02EB - Enable PCIE RP Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpEnable[20]; -/** Offset 0x0300 - Enable PCIE RP PMSCI +/** Offset 0x02FF - Enable PCIE RP PMSCI Indicate whether the root port power manager SCI is enabled - 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpPmSci[20]; -/** Offset 0x0314 - Enable PCIE RP CLKREQ Support +/** Offset 0x0313 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpClkReqSupport[20]; -/** Offset 0x0328 - Configure CLKREQ Number +/** Offset 0x0327 - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpClkReqNumber[20]; -/** Offset 0x033C - Enable LAN +/** Offset 0x033B - Enable LAN Enable/Disable LAN controller. $EN_DIS **/ UINT8 EnableLan; -/** Offset 0x033D - LAN LTR Programming +/** Offset 0x033C - LAN LTR Programming Enable/Disable LTR capabilty of PCH internal LAN. $EN_DIS **/ UINT8 LanLtrEnable; -/** Offset 0x033E - SATA eSATASpeedLimit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable. +/** Offset 0x033D - SATA eSATASpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable. $EN_DIS **/ UINT8 eSATASpeedLimit; -/** Offset 0x033F - SATA RST RAID0 +/** Offset 0x033E - SATA RST RAID0 Enable/Disable RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x0340 - SATA RST RAID1 +/** Offset 0x033F - SATA RST RAID1 Enable/Disable RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x0341 - SATA RST RAID10 +/** Offset 0x0340 - SATA RST RAID10 Enable/Disable RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x0342 - SATA RST RAID5 +/** Offset 0x0341 - SATA RST RAID5 Enable/Disable RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x0343 - Skip Multi-Processor Initialization +/** Offset 0x0342 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize, 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0344 - Enable PCIE RP HotPlug +/** Offset 0x0343 - Enable PCIE RP HotPlug Enable/disable PCIE Root Ports HogPlug. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ UINT8 PcieRpHotPlug[20]; -/** Offset 0x0358 - Enable PCIE RP Function Swap +/** Offset 0x0357 - Enable PCIE RP Function Swap Enable/disable PCIE RP function swap. 0: disable, 1: enable. It allows BIOS to use root port function number swapping when root port of function 0 is disabled. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage. Disabling function swap may have adverse impact on power management. $EN_DIS **/ UINT8 RpFunctionSwap; -/** Offset 0x0359 - USB2 Port Over Current Configuration +/** Offset 0x0358 - USB2 Port Over Current Configuration Configure over current pin assignment per USB2 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0369 - USB3 Port Over Current Configuration +/** Offset 0x0368 - USB3 Port Over Current Configuration Configure over current pin assignment per USB3 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0373 -**/ - UINT8 UnusedUpdSpace7[1]; - -/** Offset 0x0374 - Psi1Threshold +/** Offset 0x0372 - Psi1Threshold Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 Psi1Threshold[5]; -/** Offset 0x037E - Psi2Threshold +/** Offset 0x037C - Psi2Threshold Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 Psi2Threshold[5]; -/** Offset 0x0388 - Psi3Threshold +/** Offset 0x0386 - Psi3Threshold State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 Psi3Threshold[5]; -/** Offset 0x0392 - Psi3Enable +/** Offset 0x0390 - Psi3Enable Power State 3 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 Psi3Enable[5]; -/** Offset 0x0397 - Psi4Enable +/** Offset 0x0395 - Psi4Enable Power State 4 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 Psi4Enable[5]; -/** Offset 0x039C - ImonSlope +/** Offset 0x039A - ImonSlope Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 ImonSlope[5]; -/** Offset 0x03A1 - ImonOffset +/** Offset 0x039F - ImonOffset Imon offset correction. Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 ImonOffset[5]; -/** Offset 0x03A6 - IccMax +/** Offset 0x03A4 - IccMax VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 IccMax[5]; -/** Offset 0x03B0 - VrVoltageLimit +/** Offset 0x03AE - VrVoltageLimit VR Voltage Limit. Range is 0-7999mV. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT16 VrVoltageLimit[5]; -/** Offset 0x03BA - VrConfigEnable +/** Offset 0x03B8 - VrConfigEnable BIOS configuration of VR 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced **/ UINT8 VrConfigEnable[5]; -/** Offset 0x03BF -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x03C0 - CPU S3 Resume Hob Data - CPU S3 Resume Hob Data +/** Offset 0x03BD - CPU S3 Resume Data + CPU S3 Resume Data passed from the FSP CPU S3 Resume HOB during normal boot. **/ UINT32 CpuS3ResumeHobData; -/** Offset 0x03C4 - CpuS3ResumeMtrrData +/** Offset 0x03C1 - CpuS3ResumeMtrrData Pointer CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData; -/** Offset 0x03C8 - CpuS3ResumeMtrrDataSize +/** Offset 0x03C5 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data. **/ UINT16 CpuS3ResumeMtrrDataSize; -/** Offset 0x03CA - Lock Down Config Global Smi +/** Offset 0x03C7 - Lock Down Config Global Smi Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 LockDownConfigGlobalSmi; -/** Offset 0x03CB - Lock Down Config Bios Interface +/** Offset 0x03C8 - Lock Down Config Bios Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. Top Swap bit and the General Control and Status Registers Boot BIOS Straps. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 LockDownConfigBiosInterface; -/** Offset 0x03CC - Lock Down Config Bios Lock +/** Offset 0x03C9 - Lock Down Config Bios Lock When enabled, the BIOS Region can only be modified from SMM after EndOfDxe protocol is installed. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 LockDownConfigBiosLock; -/** Offset 0x03CD - Lock Down Config Spi Eiss +/** Offset 0x03CA - Lock Down Config Spi Eiss Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also in order to write to BIOS regions of SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The BIOS must set the EISS bit while BIOS Guard support is enabled. Value 0: Clear EISS bit, 1: Set EISS bit. $EN_DIS **/ UINT8 LockDownConfigSpiEiss; -/** Offset 0x03CE - Subsystem Vendor ID +/** Offset 0x03CB - Subsystem Vendor ID Subsystem Vendor ID of the PCH devices. **/ UINT16 PchConfigSubSystemVendorId; -/** Offset 0x03D0 - Subsystem ID +/** Offset 0x03CD - Subsystem ID Subsystem ID of the PCH devices. **/ UINT16 PchConfigSubSystemId; -/** Offset 0x03D2 - Wol Enable Override +/** Offset 0x03CF - Wol Enable Override Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 WakeConfigWolEnableOverride; -/** Offset 0x03D3 - Pcie Wake From DeepSx +/** Offset 0x03D0 - Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. Value 0: Disable, 1: Enable. $EN_DIS **/ UINT8 WakeConfigPcieWakeFromDeepSx; -/** Offset 0x03D4 - Power Management DeepSxPolicy +/** Offset 0x03D1 - Power Management DeepSxPolicy Deep Sx Policy. Values 0: PchDeepSxPolDisable, 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn. 0 : 0x06 **/ UINT8 PmConfigDeepSxPol; -/** Offset 0x03D5 - Power Management SlpS3MinAssert +/** Offset 0x03D2 - Power Management SlpS3MinAssert SLP_S3 Minimum Assertion Width Policy. Values 0: PchSlpS360us, 1: PchSlpS31ms, 2: PchSlpS350ms, 3: PchSlpS32s. 0 : 0x03 **/ UINT8 PmConfigSlpS3MinAssert; -/** Offset 0x03D6 - Power Management SlpS4MinAssert +/** Offset 0x03D3 - Power Management SlpS4MinAssert SLP_S4 Minimum Assertion Width Policy. Values 0: PchSlpS4PchTime, 1: PchSlpS41s, 2: PchSlpS42s, 3: PchSlpS43s, 4: PchSlpS44s. 0 : 0x04 **/ UINT8 PmConfigSlpS4MinAssert; -/** Offset 0x03D7 - Power Management SlpSusMinAssert +/** Offset 0x03D4 - Power Management SlpSusMinAssert SLP_SUS Minimum Assertion Width Policy. Values 0: PchSlpSus0ms, 1: PchSlpSus500ms, 2: PchSlpSus1s, 3: PchSlpSus4s. 0 : 0x03 **/ UINT8 PmConfigSlpSusMinAssert; -/** Offset 0x03D8 - Power Management SlpAMinAssert +/** Offset 0x03D5 - Power Management SlpAMinAssert SLP_A Minimum Assertion Width Policy. Values 0: PchSlpA0ms, 1: PchSlpA4s, 2: PchSlpA98ms, 3: PchSlpA2s. 0 : 0x03 **/ UINT8 PmConfigSlpAMinAssert; -/** Offset 0x03D9 - Power Management Pci Clock Run +/** Offset 0x03D6 - Power Management Pci Clock Run This member describes whether or not the PCI ClockRun feature of PCH should be enabled. Values 0: Disabled, 1: Enabled $EN_DIS **/ UINT8 PmConfigPciClockRun; -/** Offset 0x03DA - Power Management SLP_X Stretching After SUS Well +/** Offset 0x03D7 - Power Management SLP_X Stretching After SUS Well SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled $EN_DIS **/ UINT8 PmConfigSlpStrchSusUp; -/** Offset 0x03DB - Power Management Power Button Override Period +/** Offset 0x03D8 - Power Management Power Button Override Period PCH power button override period. Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s. 0 : 0x05 **/ UINT8 PmConfigPwrBtnOverridePeriod; -/** Offset 0x03DC - Power Management Power Reset Power Cycle Duration +/** Offset 0x03D9 - Power Management Power Reset Power Cycle Duration Reset Power Cycle Duration could be customized in the unit of second. PCH HW default is 4 seconds, and range is 1~4 seconds. Values: 0x0 - 0s, 0x1 - 1s, 0x2 - 2s, 0x3 - 3s, 0x4 - 4s. 0 : 0x04 **/ UINT8 PmConfigPwrCycDur; -/** Offset 0x03DD - PCH Serial IRQ Configuration +/** Offset 0x03DA - PCH Serial IRQ Configuration Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled $EN_DIS **/ UINT8 SerialIrqConfigSirqEnable; -/** Offset 0x03DE - PCH Serial IRQ Mode Select +/** Offset 0x03DB - PCH Serial IRQ Mode Select Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode. 0 : 0x01 **/ UINT8 SerialIrqConfigSirqMode; -/** Offset 0x03DF - PCH Serial IRQ Start Frame Pulse Width +/** Offset 0x03DC - PCH Serial IRQ Start Frame Pulse Width Start Frame Pulse Width. Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. 0 : 0x02 **/ UINT8 SerialIrqConfigStartFramePulse; -/** Offset 0x03E0 - PSF Unlock +/** Offset 0x03DD - PSF Unlock The PSF registers will be locked before 3rd party code execution. This policy unlock the PSF space. NOTE: Do not set this policy "PsfUnlock" unless necessary. $EN_DIS **/ UINT8 PsfUnlock; -/** Offset 0x03E1 - IO voltage for I2C controllers +/** Offset 0x03DE - IO voltage for I2C controllers Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. **/ UINT8 SerialIoI2cVoltage[6]; -/** Offset 0x03E7 +/** Offset 0x03E4 - Enable 8254 Static Clock Gating in early POST time + Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this. + $EN_DIS +**/ + UINT8 Early8254ClockGatingEnable; + +/** Offset 0x03E5 - Enable VR specific mailbox command + When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. This for FSP only. 0 - Don't Send, 1 - Send + $EN_DIS +**/ + UINT8 SendVrMbxCmd; + +/** Offset 0x03E6 **/ - UINT8 ReservedSiliconInitUpd[19]; + UINT8 ReservedSiliconInitUpd[20]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ @@ -1004,7 +1010,7 @@ typedef struct { } UPD_DATA_REGION; #define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */ -#define FSP_IMAGE_REV 0x01080100 +#define FSP_IMAGE_REV 0x01090000 /** VPD data structure **/ @@ -1019,8 +1025,7 @@ typedef struct { **/ UINT32 PcdImageRevision; -/** Offset 0x000C - PcdUpdRegionOffset - This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +/** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; @@ -1029,7 +1034,7 @@ typedef struct { UINT8 UnusedVpdSpace0[32]; /** Offset 0x0030 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing **/ UINT8 PcdSerialIoUartDebugEnable;

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Patch set updated for coreboot: intel/skylake: Do not log wake source on reset
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13991 -gerrit commit 5e99ceb6051316eacd8f0e4e9bf508a60753fd3e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Mar 1 17:01:35 2016 -0800 intel/skylake: Do not log wake source on reset Skip logging a wake source when just resetting without coming from S3 or S5 state. This will prevent the occasional spurious event like PCI PME from showing up in the event log. BUG=chrome-os-partner:40635 BRANCH=glados TEST=run warm reboot teset on chell and ensure no wake source is logged Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890 Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329846 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331173 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/skylake/elog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index bbc4147..fc3e29a 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -118,7 +118,8 @@ static void pch_log_state(void *unused) pch_log_power_and_resets(ps); /* Wake Sources */ - pch_log_wake_source(ps); + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL);

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Patch set updated for coreboot: intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13990 -gerrit commit 07927b0de2917ccb48505c4237e56861473a453c Author: mgarima <medha.garima(a)intel.com> Date: Mon Feb 29 15:11:18 2016 +0530 intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM Enable SDHCI runtime PM since the display flicker due to SCC Power Gatingis addressed by 0x82 microcode BRANCH=glados BUG=chrome-os-partner:44663 TEST=Check if display flicker is gone when SCC is power-gated Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3 Original-Signed-off-by: Medha Garima <medha.garima(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329651 Original-Commit-Ready: Jenny Tc <jenny.tc(a)intel.com> Original-Tested-by: Jenny Tc <jenny.tc(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331172 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/intel/kunimitsu/gpio.h | 3 +++ 2 files changed, 22 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index f44e362..4a85e35 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -308,3 +308,22 @@ Scope (\_SB.PCI0.I2C4) } } } + +Scope (\_SB.PCI0.SDXC) +{ + Name (_CRS, ResourceTemplate () { + GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000, + "\\_SB.PCI0.GPIO", 0, ResourceConsumer) + { + GPIO_SD_CARD_DETECT + } + }) + + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "cd-gpio", Package () { ^SDXC, 0, 0, 1 } }, + } + }) +} diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 2dc8cfc..de51fb5 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -58,6 +58,9 @@ */ #define AUDIO_DB_ID GPP_E3 +/* SD controller needs additional card detect GPIO to support RTD3 */ +#define GPIO_SD_CARD_DETECT GPP_A7 + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = {

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New patch to review for coreboot: skylake mainboards: Configure gpio PADRSTCFG to PLTRST
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13992 -gerrit commit 064caa68fbba77813604793e4efa27c06a05258c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Feb 29 13:20:44 2016 +0530 skylake mainboards: Configure gpio PADRSTCFG to PLTRST With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki(a)intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 8 +++--- src/mainboard/google/lars/gpio.h | 48 ++++++++++++++++++------------------ src/mainboard/intel/kunimitsu/gpio.h | 10 ++++---- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 0503e3e..05897eb 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ @@ -155,14 +155,14 @@ static const struct pad_config gpio_table[] = { /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index 5aee237..e187795 100644 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -72,19 +72,19 @@ static const struct pad_config gpio_table[] = { /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ /* GPP_A16 */ -/* SD_PWR_EN */ /* GPP_A17 */ -/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ /* GPP_A19 */ -/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), -/* ISH_GP5 */ /* GPP_A23 */ -/* CORE_VID0 */ /* GPP_B0 */ -/* CORE_VID1 */ /* GPP_B1 */ -/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), -/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), +/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), +/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), +/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), @@ -152,15 +152,15 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ /* GPP_D21 */ /* ITCH_SPI_D3 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), -/* SATAXPCIE1 */ /* GPP_E1 */ -/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* CPU_GP0 */ /* GPP_E3 */ -/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), -/* SATA_DEVSLP1 */ /* GPP_E5 */ -/* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), -/* SATALED# */ /* GPP_E8 */ +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* TCH_PNL_INTR* */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), @@ -186,8 +186,8 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), -/* I2C5_SCL */ /* GPP_F11 */ +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index de51fb5..d310396 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), @@ -160,14 +160,14 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), /* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SSD_PEDET */ PAD_CFG_NC(GPP_E2), /* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -181,7 +181,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),

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New patch to review for coreboot: intel/skylake: Do not log wake source on reset
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13991 -gerrit commit 337e1c35c5f22e3b7a85aad3a83dc27584195199 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Mar 1 17:01:35 2016 -0800 intel/skylake: Do not log wake source on reset Skip logging a wake source when just resetting without coming from S3 or S5 state. This will prevent the occasional spurious event like PCI PME from showing up in the event log. BUG=chrome-os-partner:40635 BRANCH=glados TEST=run warm reboot teset on chell and ensure no wake source is logged Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890 Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329846 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331173 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/skylake/elog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index bbc4147..fc3e29a 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -118,7 +118,8 @@ static void pch_log_state(void *unused) pch_log_power_and_resets(ps); /* Wake Sources */ - pch_log_wake_source(ps); + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL);

1 0

New patch to review for coreboot: intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13990 -gerrit commit bfa5d4279cd4dc29f569bee9973b3e0237bd9ce2 Author: mgarima <medha.garima(a)intel.com> Date: Mon Feb 29 15:11:18 2016 +0530 intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM Enable SDHCI runtime PM since the display flicker due to SCC Power Gatingis addressed by 0x82 microcode BRANCH=glados BUG=chrome-os-partner:44663 TEST=Check if display flicker is gone when SCC is power-gated Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3 Original-Signed-off-by: Medha Garima <medha.garima(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329651 Original-Commit-Ready: Jenny Tc <jenny.tc(a)intel.com> Original-Tested-by: Jenny Tc <jenny.tc(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331172 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 19 +++++++++++++++++++ src/mainboard/intel/kunimitsu/gpio.h | 3 +++ 2 files changed, 22 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index f44e362..4a85e35 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -308,3 +308,22 @@ Scope (\_SB.PCI0.I2C4) } } } + +Scope (\_SB.PCI0.SDXC) +{ + Name (_CRS, ResourceTemplate () { + GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000, + "\\_SB.PCI0.GPIO", 0, ResourceConsumer) + { + GPIO_SD_CARD_DETECT + } + }) + + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "cd-gpio", Package () { ^SDXC, 0, 0, 1 } }, + } + }) +} diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 2dc8cfc..de51fb5 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -58,6 +58,9 @@ */ #define AUDIO_DB_ID GPP_E3 +/* SD controller needs additional card detect GPIO to support RTD3 */ +#define GPIO_SD_CARD_DETECT GPP_A7 + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = {

1 0

New patch to review for coreboot: mediatek/mt8173: memlayout: Create DRAM DMA region for NOR flash DMA read.
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13989 -gerrit commit f36c9cbf427f82b30ae50ac3b73489519f493177 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Tue Feb 16 20:42:10 2016 +0800 mediatek/mt8173: memlayout: Create DRAM DMA region for NOR flash DMA read. NOR flash has a hardware limitation that it can't access SRAM region after 4GB mode is enabled. We add a DRAM DMA region after 0x40000000 for NOR flash driver. So that the NOR flash driver can use this region after 4GB mode is enabled. BRANCH=none BUG=chormoe-os-partner:49229 TEST=Boot to kernel on rev4 w/ 2GB ram and rev3 w/ 4GB ram. And check /proc/meminfo. Change-Id: I4a86f0028b26509589ec8d09e2d077920446ece1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: dc61ec55187959101a9e891fe5e93928e9b8176e Original-Change-Id: Ifedc9e2dfba5d294297b3a28134997ac1dd38f94 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327962 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331177 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/flash_controller.c | 29 ++++++++++++++++------ src/soc/mediatek/mt8173/include/soc/memlayout.ld | 6 +++++ .../mediatek/mt8173/include/soc/mmu_operations.h | 4 +++ src/soc/mediatek/mt8173/mmu_operations.c | 2 ++ 4 files changed, 34 insertions(+), 7 deletions(-) diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index f662916..5d73f3a 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -26,6 +26,7 @@ #include <symbols.h> #include <timer.h> #include <soc/flash_controller.h> +#include <soc/mmu_operations.h> #define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff) @@ -112,21 +113,22 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(65535, buf_len); } -static int dma_read(u32 addr, u8 *buf, u32 len) +static int dma_read(u32 addr, u8 *buf, u32 len, uintptr_t dma_buf, + size_t dma_buf_len) { struct stopwatch sw; assert(IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN) && IS_ALIGNED(len, SFLASH_DMA_ALIGN) && - len <= _dma_coherent_size); + len <= dma_buf_len); /* do dma reset */ write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_SW_RESET); write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); /* flash source address and dram dest address */ write32(&mt8173_nor->fdma_fadr, addr); - write32(&mt8173_nor->fdma_dadr, ((uintptr_t)_dma_coherent )); - write32(&mt8173_nor->fdma_end_dadr, ((uintptr_t)_dma_coherent + len)); + write32(&mt8173_nor->fdma_dadr, dma_buf); + write32(&mt8173_nor->fdma_end_dadr, (dma_buf + len)); /* start dma */ write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); @@ -138,7 +140,7 @@ static int dma_read(u32 addr, u8 *buf, u32 len) } } - memcpy(buf, _dma_coherent, len); + memcpy(buf, (const void *)dma_buf, len); return 0; } @@ -160,6 +162,9 @@ static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) u32 next; size_t done = 0; + uintptr_t dma_buf; + size_t dma_buf_len; + if (!IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN)) { next = MIN(ALIGN_UP((uintptr_t)buf, SFLASH_DMA_ALIGN) - (uintptr_t)buf, len); @@ -167,10 +172,20 @@ static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) return -1; done += next; } + + if (ENV_BOOTBLOCK || ENV_VERSTAGE) { + dma_buf = (uintptr_t)_dma_coherent; + dma_buf_len = _dma_coherent_size; + } else { + dma_buf = (uintptr_t)_dram_dma; + dma_buf_len = _dram_dma_size; + } + while (len - done >= SFLASH_DMA_ALIGN) { - next = MIN(_dma_coherent_size, ALIGN_DOWN(len - done, + next = MIN(dma_buf_len, ALIGN_DOWN(len - done, SFLASH_DMA_ALIGN)); - if (dma_read(addr + done, buf + done, next)) + if (dma_read(addr + done, buf + done, next, dma_buf, + dma_buf_len)) return -1; done += next; } diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 7d0c766..771f326 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -25,6 +25,11 @@ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_L2C_START(0x000C0000) @@ -44,6 +49,7 @@ SECTIONS SRAM_END(0x00130000) DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) RAMSTAGE(0x40200000, 256K) } diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h index 98fffa2..2428c42 100644 --- a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h +++ b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h @@ -29,6 +29,10 @@ extern unsigned char _sram_l2c[]; extern unsigned char _esram_l2c[]; #define _sram_l2c_size (_esram_l2c - _sram_l2c) +extern unsigned char _dram_dma[]; +extern unsigned char _edram_dma[]; +#define _dram_dma_size (_edram_dma - _dram_dma) + void mt8173_mmu_init(void); void mt8173_mmu_after_dram(void); diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index 53152dd..c744d65 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -53,6 +53,8 @@ void mt8173_mmu_after_dram(void) /* TODO: Implement true unmapping, and also use it for the zero-page! */ mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM); + /* Careful: changing cache geometry while it's active is a bad idea! */ mmu_disable();

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New patch to review for coreboot: mediatek/mt8173: detect sdram size at runtime
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13988 -gerrit commit c2af299189938ad3e3ea53211b1c81b6505a5792 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Thu Feb 4 17:26:48 2016 +0800 mediatek/mt8173: detect sdram size at runtime Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect the DRAM size at runtime. BUG=chrome-os-partner:49427 BRANCH=none TEST=Boot to kernel Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223 Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed Original-Signed-off-by: PH Hsu <ph.hsu(a)mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327961 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331176 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 4 ---- src/soc/mediatek/mt8173/Makefile.inc | 2 +- src/soc/mediatek/mt8173/cbmem.c | 4 ++-- src/soc/mediatek/mt8173/emi.c | 36 +++++++++++++++++++++++++++++++ src/soc/mediatek/mt8173/include/soc/emi.h | 14 +++++++++++- src/soc/mediatek/mt8173/mmu_operations.c | 5 ++--- src/soc/mediatek/mt8173/soc.c | 4 ++-- 7 files changed, 56 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index ce783f3..cca9054 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER string default "oak" -config DRAM_SIZE_MB - int - default 2048 - config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0 diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b35e1f6..e18e6fe 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -59,7 +59,7 @@ romstage-y += rtc.c ################################################################################ -ramstage-y += cbmem.c +ramstage-y += cbmem.c emi.c ramstage-y += spi.c ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c mtcmos.c diff --git a/src/soc/mediatek/mt8173/cbmem.c b/src/soc/mediatek/mt8173/cbmem.c index c7afd6c..1967a2c 100644 --- a/src/soc/mediatek/mt8173/cbmem.c +++ b/src/soc/mediatek/mt8173/cbmem.c @@ -17,9 +17,9 @@ #include <stddef.h> #include <stdlib.h> #include <symbols.h> +#include <soc/emi.h> void *cbmem_top(void) { - return (void *)min((uintptr_t)_dram + ((size_t)CONFIG_DRAM_SIZE_MB * MiB), - (uintptr_t)4 * GiB); + return (void *)min((uintptr_t)_dram + sdram_size(), (uintptr_t)4 * GiB); } diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f6ef40f..1ff4f23 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -127,6 +127,42 @@ static void init_dram(const struct mt8173_sdram_params *sdram_params) dramc_init(CHANNEL_B, sdram_params); } +size_t sdram_size(void) +{ + u32 value = read32(&emi_regs->emi_cona); + u32 bit_counter = 0; + + /* check if dual channel */ + if (value & CONA_DUAL_CH_EN) + bit_counter++; + + /* check if 32bit , 32 = 2^5*/ + if (value & CONA_32BIT_EN) + bit_counter += 5; + else + bit_counter += 4; + + /* check column address */ + /* 00 is 9 bits, 01 is 10 bits , 10 is 11 bits */ + bit_counter += ((value & COL_ADDR_BITS_MASK) >> COL_ADDR_BITS_SHIFT) + + 9; + + /* check if row address */ + /*00 is 13 bits , 01 is 14 bits , 10 is 15bits , 11 is 16 bits */ + bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + + 13; + + /* check if dual rank */ + if (value & CONA_DUAL_RANK_EN) + bit_counter++; + + /* add bank address bit, LPDDR3 is 8 banks =2^3 */ + bit_counter += 3; + + /*transfor bits to bytes */ + return ((size_t)1 << (bit_counter - 3)); +} + void mt_set_emi(const struct mt8173_sdram_params *sdram_params) { /* voltage info */ diff --git a/src/soc/mediatek/mt8173/include/soc/emi.h b/src/soc/mediatek/mt8173/include/soc/emi.h index d3a2aee..959e1c9 100644 --- a/src/soc/mediatek/mt8173/include/soc/emi.h +++ b/src/soc/mediatek/mt8173/include/soc/emi.h @@ -18,6 +18,7 @@ #include <soc/dramc_common.h> #include <stdint.h> +#include <types.h> /* DDR type */ enum ram_type { @@ -124,6 +125,17 @@ struct mt8173_mrs_params { u32 mrs_63; }; +enum { + /* CONA = 0x000 */ + CONA_DUAL_CH_EN = BIT(0), + CONA_32BIT_EN = BIT(1), + CONA_DUAL_RANK_EN = BIT(17), + COL_ADDR_BITS_SHIFT = 4, + COL_ADDR_BITS_MASK = 3 << COL_ADDR_BITS_SHIFT, + ROW_ADDR_BITS_SHIFT = 12, + ROW_ADDR_BITS_MASK = 3 << ROW_ADDR_BITS_SHIFT +}; + struct mt8173_sdram_params { struct mt8173_calib_params calib_params; struct mt8173_timing_params ac_timing; @@ -136,5 +148,5 @@ struct mt8173_sdram_params { void mt_set_emi(const struct mt8173_sdram_params *sdram_params); void mt_mem_init(const struct mt8173_sdram_params *sdram_params); const struct mt8173_sdram_params *get_sdram_config(void); - +size_t sdram_size(void); #endif diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index 744248a..53152dd 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -20,12 +20,11 @@ #include <stdlib.h> #include <stdint.h> #include <soc/addressmap.h> +#include <soc/emi.h> #include <soc/infracfg.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> -static const uint64_t dram_size = (uint64_t)CONFIG_DRAM_SIZE_MB * MiB; - void mt8173_mmu_init(void) { mmu_init(); @@ -48,7 +47,7 @@ void mt8173_mmu_init(void) void mt8173_mmu_after_dram(void) { /* Map DRAM as cached now that it's up and running */ - mmu_config_range(_dram, dram_size, CACHED_MEM); + mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ /* TODO: Implement true unmapping, and also use it for the zero-page! */ diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c index 7f0b1b7..7507ae4 100644 --- a/src/soc/mediatek/mt8173/soc.c +++ b/src/soc/mediatek/mt8173/soc.c @@ -17,11 +17,11 @@ #include <console/console.h> #include <device/device.h> #include <symbols.h> +#include <soc/emi.h> static void soc_read_resources(device_t dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, - CONFIG_DRAM_SIZE_MB * (MiB / KiB)); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); } static void soc_init(device_t dev)

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New patch to review for coreboot: mediatek/mt8173: mmu: update mmu range before DRAM is initialized.
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13987 -gerrit commit b5415626f0b1bec632a3988a59bf52f539349a6e Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Jan 18 11:06:19 2016 +0800 mediatek/mt8173: mmu: update mmu range before DRAM is initialized. The DRAM size can not be determined before DRAM is initialized. Since mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of 2GB DRAM address before DRAM is initialized. BRANCH=none BUG=none TEST=boot to kernel Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327960 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331175 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/mmu_operations.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index a70fe2c..744248a 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -30,8 +30,8 @@ void mt8173_mmu_init(void) { mmu_init(); - /* Set 0x0 to end of dram as device memory */ - mmu_config_range((void *)0, (uintptr_t)_dram + dram_size, DEV_MEM); + /* Set 0x0 to the end of 2GB dram address as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); @@ -47,7 +47,7 @@ void mt8173_mmu_init(void) void mt8173_mmu_after_dram(void) { - /* Remap DRAM as cached now that it's up and running */ + /* Map DRAM as cached now that it's up and running */ mmu_config_range(_dram, dram_size, CACHED_MEM); /* Unmap L2C SRAM so it can be reclaimed by L2 cache */

1 0

Patch set updated for coreboot: mediatek/mt8173: Enable ARM trusted firmware integration
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13968 -gerrit commit f8189208ad208625925acf3912a0ef7bea74dd4e Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 8 21:42:00 2016 +0100 mediatek/mt8173: Enable ARM trusted firmware integration In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 91a8d4f..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8173 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING if SPI_FLASH

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coreboot-gerrit March 2016