coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

New patch to review for coreboot: soc/intel/apollolake: Avoid hardcoding CAR region size for FSPM
by Andrey Petrov 09 Mar '16

09 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14001 -gerrit commit 6fad2891a89eab329a6043be294e42d962068f2c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Mar 8 21:59:01 2016 -0800 soc/intel/apollolake: Avoid hardcoding CAR region size for FSPM Instead of having to supply CAR memory region during compilation time it is possible to determine it in runtime. FSP2.0 blobs carry a copy of UPD structure pre-populated with 'default' values. The default value for StackSize is actually the real value blob needs. Change-Id: I298e07bb12470ce659f63846ab096189138e594f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 6 ------ src/soc/intel/apollolake/romstage.c | 12 ++++++++---- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 022c2e4..a11c5a2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -98,10 +98,4 @@ config ROMSTAGE_ADDR help The base address (in CAR) where romstage should be linked -config FSPM_STACK_SIZE - hex - default 0x40000 - help - The amount of CAR memory FSPM needs. Recommended at least 256KiB - endif diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2c8bbe8..7c8924d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -141,10 +141,14 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) mupd->FspmConfig.FitTablePtr = read32((void*) FIT_POINTER); /* Reserve enough memory under TOLUD to save CBMEM header */ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); - /* Let FSPM use memory right at the top of CAR */ - /* TODO: Add checks to see if we collide with other areas */ - mupd->FspmArchUpd.StackBase = _car_region_end - CONFIG_FSPM_STACK_SIZE; - mupd->FspmArchUpd.StackSize = CONFIG_FSPM_STACK_SIZE; + /* + * FSPM_UPD passed here is populated with default values provided by + * the blob itself. We let FSPM use top of CAR region of the size it + * requests. + * TODO: add checks to avoid overlap/conflict of CAR usage. + */ + mupd->FspmArchUpd.StackBase = _car_region_end - + mupd->FspmArchUpd.StackSize; } __attribute__ ((weak))

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Patch set updated for coreboot: north/sandybridge/mrccache: parse the return code of flash->write
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13999 -gerrit commit fcce220a2f3c1ba9f1ecc479488a26d029af45bc Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 04:02:42 2016 +0100 north/sandybridge/mrccache: parse the return code of flash->write Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/sandybridge/mrccache.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a5dd456..b5b87ab 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -160,6 +160,7 @@ static void update_mrc_cache(void *unused) struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); struct mrc_data_container *cache, *cache_base; u32 cache_size; + int ret; if (!current) { printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); @@ -220,8 +221,13 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(flash, cache), + ret = flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); + if (ret) + printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", + ret); + else + printk(BIOS_DEBUG, "Successful written MRC cache\n"); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);

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New patch to review for coreboot: spi/SST: fix write support for SST25VF064C
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14000 -gerrit commit 3bf7af4afb6423e933e8a8366d4566ceea40b372 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 05:11:44 2016 +0100 spi/SST: fix write support for SST25VF064C The SST25VF064C doesn't support the auto incrementing write which all other supported SST chips support. Allow the chips to select their write method. Change-Id: Ic088d35461a625469ee6973d1267d7dd11963496 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/drivers/spi/sst.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index aab654c..87c1c5b 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -40,6 +40,8 @@ struct sst_spi_flash_params { u8 idcode1; u16 nr_sectors; const char *name; + int (*write)(struct spi_flash *flash, u32 offset, + size_t len, const void *buf); }; struct sst_spi_flash { @@ -47,44 +49,58 @@ struct sst_spi_flash { const struct sst_spi_flash_params *params; }; +static int +sst_write_ai(struct spi_flash *flash, u32 offset, size_t len, const void *buf); +static int +sst_write_256(struct spi_flash *flash, u32 offset, size_t len, const void *buf); + #define SST_SECTOR_SIZE (4 * 1024) static const struct sst_spi_flash_params sst_spi_flash_table[] = { { .idcode1 = 0x8d, .nr_sectors = 128, .name = "SST25VF040B", + .write = sst_write_ai, },{ .idcode1 = 0x8e, .nr_sectors = 256, .name = "SST25VF080B", + .write = sst_write_ai, },{ .idcode1 = 0x41, .nr_sectors = 512, .name = "SST25VF016B", + .write = sst_write_ai, },{ .idcode1 = 0x4a, .nr_sectors = 1024, .name = "SST25VF032B", + .write = sst_write_ai, },{ .idcode1 = 0x4b, .nr_sectors = 2048, .name = "SST25VF064C", + .write = sst_write_256, },{ .idcode1 = 0x01, .nr_sectors = 16, .name = "SST25WF512", + .write = sst_write_ai, },{ .idcode1 = 0x02, .nr_sectors = 32, .name = "SST25WF010", + .write = sst_write_ai, },{ .idcode1 = 0x03, .nr_sectors = 64, .name = "SST25WF020", + .write = sst_write_ai, },{ .idcode1 = 0x04, .nr_sectors = 128, .name = "SST25WF040", + .write = sst_write_ai, }, }; @@ -143,7 +159,83 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) } static int -sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) +sst_write_256(struct spi_flash *flash, u32 offset, size_t len, const void *buf) +{ + size_t actual, chunk_len, cmd_len; + unsigned long byte_addr; + unsigned long page_size; + int ret = 0; + u8 cmd[4]; + + page_size = 256; + byte_addr = offset % page_size; + + flash->spi->rw = SPI_WRITE_FLAG; + + /* If the data is not word aligned, write out leading single byte */ + actual = offset % 2; + if (actual) { + ret = sst_byte_write(flash, offset, buf); + if (ret) + goto done; + } + offset += actual; + + ret = sst_enable_writing(flash); + if (ret) + goto done; + + cmd_len = 4; + cmd[0] = CMD_SST_AAI_WP; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); + + cmd[0] = CMD_SST_BP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: SST Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + offset += chunk_len; + byte_addr = 0; + } + +done: +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "SF: SST: program %s %zu bytes @ 0x%lx\n", + ret ? "failure" : "success", len, (unsigned long)offset - actual); +#endif + return ret; +} + +static int +sst_write_ai(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { size_t actual, cmd_len; int ret = 0; @@ -257,7 +349,7 @@ spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) stm->flash.spi = spi; stm->flash.name = params->name; - stm->flash.write = sst_write; + stm->flash.write = params->write; stm->flash.erase = spi_flash_cmd_erase; stm->flash.status = spi_flash_cmd_status; stm->flash.read = spi_flash_cmd_read_fast;

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New patch to review for coreboot: north/sandybridge: parse rc of flash->write and log the result
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13999 -gerrit commit 189cc70c23f212ca945b5b6bfc4928c29fe79e38 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 04:02:42 2016 +0100 north/sandybridge: parse rc of flash->write and log the result Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/sandybridge/mrccache.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a5dd456..b5b87ab 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -160,6 +160,7 @@ static void update_mrc_cache(void *unused) struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); struct mrc_data_container *cache, *cache_base; u32 cache_size; + int ret; if (!current) { printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); @@ -220,8 +221,13 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(flash, cache), + ret = flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); + if (ret) + printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", + ret); + else + printk(BIOS_DEBUG, "Successful written MRC cache\n"); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);

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Patch set updated for coreboot: north/intel: move mrc_data definition into common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13998 -gerrit commit 1cdae8d083e24d43f8befe80c5c397caec2d535f Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 north/intel: move mrc_data definition into common The mrc_data definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/common/mrc_data.h | 15 +++++++++++++++ src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ---- src/northbridge/intel/haswell/haswell.h | 13 +------------ src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/haswell/raminit.c | 1 + src/northbridge/intel/nehalem/nehalem.h | 13 +------------ src/northbridge/intel/nehalem/raminit.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/sandybridge.h | 13 +------------ 11 files changed, 24 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/common/mrc_data.h b/src/northbridge/intel/common/mrc_data.h new file mode 100644 index 0000000..b6ccdb9 --- /dev/null +++ b/src/northbridge/intel/common/mrc_data.h @@ -0,0 +1,15 @@ +#ifndef MRCDATA_H +#define MRCDATA_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +#endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index ab428c3..a41b2ca 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 8a01edc..c560428 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 7139930..848ee6c 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -20,6 +20,7 @@ #include <cbfs.h> #include <fmap.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/device.h> #include <cbmem.h> #include "pei_data.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 92a4532..73c3354 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,6 +22,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index d15c7ef..a2536cc 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4bc95ba..5e5db50 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,6 +40,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <northbridge/intel/common/mrc_data.h> #endif #if !REAL diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a5dd456..bb411e5 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" +#include <northbridge/intel/common/mrc_data.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1527ec3..7f83b33 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -26,6 +26,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/pci_def.h> #include <memory_info.h> #include <smbios.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 162caf6..8c05347 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -24,6 +24,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mrc_data.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ba8f8d9..116e0a8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,18 +235,7 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h"

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Patch set updated for coreboot: north/intel: move mrc_data definition into common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13998 -gerrit commit 87012d7306421de884bab14dc5a66fc788861054 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 north/intel: move mrc_data definition into common The mrc_data definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab --- src/northbridge/intel/common/mrc_data.h | 15 +++++++++++++++ src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ---- src/northbridge/intel/haswell/haswell.h | 13 +------------ src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/haswell/raminit.c | 1 + src/northbridge/intel/nehalem/nehalem.h | 13 +------------ src/northbridge/intel/nehalem/raminit.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/sandybridge.h | 13 +------------ 11 files changed, 24 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/common/mrc_data.h b/src/northbridge/intel/common/mrc_data.h new file mode 100644 index 0000000..b6ccdb9 --- /dev/null +++ b/src/northbridge/intel/common/mrc_data.h @@ -0,0 +1,15 @@ +#ifndef MRCDATA_H +#define MRCDATA_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +#endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index ab428c3..a41b2ca 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 8a01edc..c560428 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 7139930..848ee6c 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -20,6 +20,7 @@ #include <cbfs.h> #include <fmap.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/device.h> #include <cbmem.h> #include "pei_data.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 92a4532..73c3354 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,6 +22,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index d15c7ef..a2536cc 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4bc95ba..5e5db50 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,6 +40,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <northbridge/intel/common/mrc_data.h> #endif #if !REAL diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a5dd456..bb411e5 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" +#include <northbridge/intel/common/mrc_data.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1527ec3..7f83b33 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -26,6 +26,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/pci_def.h> #include <memory_info.h> #include <smbios.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 162caf6..8c05347 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -24,6 +24,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mrc_data.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ba8f8d9..116e0a8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,18 +235,7 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h"

1 0

Patch set updated for coreboot: north/intel: move mrc_data definition into common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13998 -gerrit commit b719f27921de48035f02602f05deb6a9f4f4f76d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 north/intel: move mrc_data definition into common The mrc_data definition and the struct mrc_container are the same over all intel platforms Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab --- src/northbridge/intel/common/mrc_data.h | 15 +++++++++++++++ src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ---- src/northbridge/intel/haswell/haswell.h | 13 +------------ src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/haswell/raminit.c | 1 + src/northbridge/intel/nehalem/nehalem.h | 13 +------------ src/northbridge/intel/nehalem/raminit.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/sandybridge.h | 13 +------------ 11 files changed, 24 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/common/mrc_data.h b/src/northbridge/intel/common/mrc_data.h new file mode 100644 index 0000000..b6ccdb9 --- /dev/null +++ b/src/northbridge/intel/common/mrc_data.h @@ -0,0 +1,15 @@ +#ifndef MRCDATA_H +#define MRCDATA_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +#endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index ab428c3..a41b2ca 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 8a01edc..c560428 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 7139930..848ee6c 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -20,6 +20,7 @@ #include <cbfs.h> #include <fmap.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/device.h> #include <cbmem.h> #include "pei_data.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 92a4532..73c3354 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,6 +22,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index d15c7ef..a2536cc 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4bc95ba..5e5db50 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,6 +40,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <northbridge/intel/common/mrc_data.h> #endif #if !REAL diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a5dd456..bb411e5 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" +#include <northbridge/intel/common/mrc_data.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1527ec3..7f83b33 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -26,6 +26,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/pci_def.h> #include <memory_info.h> #include <smbios.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 162caf6..8c05347 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -24,6 +24,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mrc_data.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ba8f8d9..116e0a8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,18 +235,7 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h"

1 0

New patch to review for coreboot: north/intel: move mrc_data definition into common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13998 -gerrit commit 99985211dec6453a69bd70a70bdc4c6ac5c06537 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 north/intel: move mrc_data definition into common The mrc_data definition and the struct mrc_container are the same over all intel platforms Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab --- src/northbridge/intel/common/mrc_data.h | 15 +++++++++++++++ src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ---- src/northbridge/intel/haswell/haswell.h | 13 +------------ src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/haswell/raminit.c | 1 + src/northbridge/intel/nehalem/nehalem.h | 13 +------------ src/northbridge/intel/nehalem/raminit.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/sandybridge.h | 13 +------------ 11 files changed, 24 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/common/mrc_data.h b/src/northbridge/intel/common/mrc_data.h new file mode 100644 index 0000000..b6ccdb9 --- /dev/null +++ b/src/northbridge/intel/common/mrc_data.h @@ -0,0 +1,15 @@ +#ifndef MRCDATA_H +#define MRCDATA_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +#endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index ab428c3..a41b2ca 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 8a01edc..f2e5d78 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container *; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 7139930..848ee6c 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -20,6 +20,7 @@ #include <cbfs.h> #include <fmap.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/device.h> #include <cbmem.h> #include "pei_data.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 92a4532..73c3354 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,6 +22,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_data.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index d15c7ef..a2536cc 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4bc95ba..5e5db50 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,6 +40,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <northbridge/intel/common/mrc_data.h> #endif #if !REAL diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a5dd456..bb411e5 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" +#include <northbridge/intel/common/mrc_data.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1527ec3..7f83b33 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -26,6 +26,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/common/mrc_data.h> #include <device/pci_def.h> #include <memory_info.h> #include <smbios.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 162caf6..8c05347 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -24,6 +24,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mrc_data.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ba8f8d9..eee3650 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,18 +235,7 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container *; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h"

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Populate static devicetree
by Andrey Petrov 09 Mar '16

09 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13926 -gerrit commit be100fd65ef22cfdee3e75950f02a70e67fd8805 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Sun Mar 6 22:19:31 2016 -0800 mainboard/intel/apollolake_rvp: Populate static devicetree Add configuration in accordance to "PCI Configuration Matrix". Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/devicetree.cb | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index d624bc0..746aaf3 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -1,9 +1,56 @@ chip soc/intel/apollolake + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + device cpu_cluster 0 on device lapic 0 on end end device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS end end

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Patch set updated for coreboot: soc/intel/apollolake: Add chip initialization
by Andrey Petrov 09 Mar '16

09 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13911 -gerrit commit 8de9655c5746b54a52d1d2a10839d585a08e4583 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 4 21:41:13 2016 -0800 soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 109 ++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 32 ++++++++++ 3 files changed, 142 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b31f12..1b2efdf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += cpu.c +ramstage-y += chip.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c new file mode 100644 index 0000000..f801eec --- /dev/null +++ b/src/soc/intel/apollolake/chip.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <soc/cpu.h> + +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = apollolake_init_cpus, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + /* pretty liberal allowed range for now */ + struct range_entry range = {.begin=0x200000, .end=0xffffffff}; + fsp_silicon_init(&range); +} + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ + struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; + static struct soc_intel_apollolake_config *cfg; + + /* Load VBT before devicetree-specific config. */ + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + + struct device *dev = dev_find_slot(0, 0); + if (!dev && !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; + silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; + silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; + silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; + silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; + silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; +} + +struct chip_operations soc_intel_apollolake_ops = { + CHIP_NAME("Intel Apollolake SOC") + .enable_dev = &enable_dev, + .init = &soc_init +}; + +static void fsp_notify_dummy(void *arg) +{ + + enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; + + if (fsp_notify(ph) != FSP_SUCCESS) + printk(BIOS_CRIT, "FspNotify failed!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h new file mode 100644 index 0000000..026fdda --- /dev/null +++ b/src/soc/intel/apollolake/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CHIP_H_ +#define _SOC_APOLLOLAKE_CHIP_H_ + +#define CLKREQ_DISABLED 0xf + +struct soc_intel_apollolake_config { + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + uint8_t pcie_rp0_clkreq_pin; + uint8_t pcie_rp1_clkreq_pin; + uint8_t pcie_rp2_clkreq_pin; + uint8_t pcie_rp3_clkreq_pin; + uint8_t pcie_rp4_clkreq_pin; + uint8_t pcie_rp5_clkreq_pin; +}; + +#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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coreboot-gerrit March 2016