Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13910
-gerrit
commit 15fb1008e834709524600ff7b27c8904eecc1b19
Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Date: Fri Mar 4 21:33:04 2016 -0800
soc/apollolake: Enable all CPU cores using the parallel MP lib
This is the minimal setup needed to get all CPU cores enabled. That
includes sending an IPI to APs and setting up MTRRs. Microcode updates
are not performed for two reasons:
* CSE (Converged Security Engine) upgrades the microcode before
releasing reset
* Microcode update files are not available at this point in time
Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 2 +
src/soc/intel/apollolake/cpu.c | 105 +++++++++++++++++++++++++++++
src/soc/intel/apollolake/include/soc/cpu.h | 6 ++
3 files changed, 113 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index dd2213e..3b31f12 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
+subdirs-y += ../../../cpu/x86/cache
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
@@ -24,6 +25,7 @@ romstage-y += memmap.c
romstage-y += mmap_boot.c
smm-y += placeholders.c
+ramstage-y += cpu.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
new file mode 100644
index 0000000..2af6e83
--- /dev/null
+++ b/src/soc/intel/apollolake/cpu.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/cpu.h>
+
+static void cpu_core_init(device_t cpu)
+{
+ /* Turn on cache */
+ x86_enable_cache();
+ /* Set up Memory Type Range Registers */
+ x86_setup_mtrrs();
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = cpu_core_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
+ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
+static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
+{
+ msr_t msr;
+ msr = rdmsr(MSR_CORE_THREAD_COUNT);
+ *num_virt = (msr.lo >> 0) & 0xffff;
+ *num_phys = (msr.lo >> 16) & 0xffff;
+}
+
+/*
+ * Do essential initialization tasks before APs can be fired up
+ *
+ * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
+ * creates the MTRR solution that the APs will use. Otherwise APs will try to
+ * apply the incomplete solution as the BSP is calculating it.
+ */
+static void bsp_pre_mp_setup(void)
+{
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+}
+
+/*
+ * CPU initialization recipe
+ *
+ * Note that no microcode update is passed to the init function. CSE updates
+ * the microcode on all cores before releasing them from reset. That means that
+ * the BSP and all APs will come up with the same microcode revision.
+ */
+static struct mp_flight_record flight_plan[] = {
+ /* NOTE: MTRR solution must be calculated before firing up the APs */
+ MP_FR_NOBLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
+};
+
+void apollolake_init_cpus(device_t dev)
+{
+ unsigned int num_virt_cores, num_phys_cores;
+
+ /* Pre-flight check */
+ bsp_pre_mp_setup();
+
+ /* Find CPU topology */
+ read_cpu_topology(&num_phys_cores, &num_virt_cores);
+ printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
+ num_phys_cores, num_virt_cores);
+
+ /* Systems check */
+ struct mp_params flight_data_recorder = {
+ .num_cpus = num_virt_cores,
+ .parallel_microcode_load = 0,
+ .microcode_pointer = NULL,
+ .adjust_apic_id = NULL,
+ .flight_plan = flight_plan,
+ .num_records = ARRAY_SIZE(flight_plan),
+ };
+
+ /* Clear for take-off */
+ if (mp_init(dev->link_list, &flight_data_recorder) < 0)
+ printk(BIOS_ERR, "MP initialization failure.\n");
+}
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 870f474..765be70 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -14,12 +14,18 @@
#define _SOC_APOLLOLAKE_CPU_H_
#include <cpu/x86/msr.h>
+#include <device/device.h>
#define CPUID_APOLLOLAKE_A0 0x506c8
+#define CPUID_APOLLOLAKE_B0 0x506c9
#define MSR_PLATFORM_INFO 0xce
#define MSR_POWER_MISC 0x120
+#define MSR_CORE_THREAD_COUNT 0x35
#define BASE_CLOCK_MHZ 100
+void apollolake_init_cpus(struct device *dev);
+
+
#endif /* _SOC_APOLLOLAKE_CPU_H_ */
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13997
-gerrit
commit 2dbead3fd746040661deea1f7b85c7b8789aac97
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Tue Mar 8 16:12:06 2016 -0800
soc/intel/apollolake: Avoid UART BAR relocation at ramstage
UART bar gets overwritten during resource allocation stage. As result
the serial driver ends up using stale BAR so serial output does not
work. This driver simply tells resource allocator not to change BAR
of UART device.
Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/uart.c | 55 +++++++++++++++++++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 1b2efdf..8581607 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -32,6 +32,7 @@ ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
+ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
new file mode 100644
index 0000000..2040cb0
--- /dev/null
+++ b/src/soc/intel/apollolake/uart.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/*
+ * The sole purpose of this driver is to avoid BAR to be changed during
+ * resource allocation. Since configuration space is just 32 bytes it
+ * shouldn't cause any fragmentation.
+ */
+
+#include <console/uart.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+
+static void uart_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ res = new_resource(dev, PCI_BASE_ADDRESS_0);
+ res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+ res->size = 32;
+ res->align = 5;
+ res->gran = 5;
+ res->limit = res->base + res->size - 1;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_ASSIGNED;
+}
+
+static struct device_operations uart_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = uart_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = pci_dev_init,
+ .enable = DEVICE_NOOP
+};
+
+static const unsigned short uart_ids[] = {
+ PCI_DEV_ID_APOLLOLAKE_UART2,
+ 0
+};
+
+static const struct pci_driver uart_driver __pci_driver = {
+ .ops = &uart_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = uart_ids
+};
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13997
-gerrit
commit 0ddd944b173cc787e7814d6f5de2cee7722e0d20
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Tue Mar 8 16:12:06 2016 -0800
soc/intel/apollolake: Avoid UART BAR relocation at ramstage
UART bar gets overwritten during resource allocation stage. As result
the serial driver ends up using stale BAR so serial output does not
work. This driver simply tells resource allocator not to change BAR
of UART device.
Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/uart.c | 55 +++++++++++++++++++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 1b2efdf..8581607 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -32,6 +32,7 @@ ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
+ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
new file mode 100644
index 0000000..2040cb0
--- /dev/null
+++ b/src/soc/intel/apollolake/uart.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/*
+ * The sole purpose of this driver is to avoid BAR to be changed during
+ * resource allocation. Since configuration space is just 32 bytes it
+ * shouldn't cause any fragmentation.
+ */
+
+#include <console/uart.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+
+static void uart_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ res = new_resource(dev, PCI_BASE_ADDRESS_0);
+ res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+ res->size = 32;
+ res->align = 5;
+ res->gran = 5;
+ res->limit = res->base + res->size - 1;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_ASSIGNED;
+}
+
+static struct device_operations uart_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = uart_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = pci_dev_init,
+ .enable = DEVICE_NOOP
+};
+
+static const unsigned short uart_ids[] = {
+ PCI_DEV_ID_APOLLOLAKE_UART2,
+ 0
+};
+
+static const struct pci_driver uart_driver __pci_driver = {
+ .ops = &uart_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = uart_ids
+};
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13926
-gerrit
commit f556f444dc7e460c4a99959cdfe2561065e6c8c8
Author: Lance Zhao <lijian.zhao(a)intel.com>
Date: Sun Mar 6 22:19:31 2016 -0800
mainboard/intel/apollolake_rvp: Populate static devicetree
Add configuration in accordance to "PCI Configuration Matrix".
Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/devicetree.cb | 47 ++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index d624bc0..746aaf3 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -1,9 +1,56 @@
chip soc/intel/apollolake
+ register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2
+ register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot
+ register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1
+ register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 11.0 on end # - ISH
+ device pci 12.0 on end # - SATA
+ device pci 13.0 on end # - PCIe-A 0
+ device pci 13.2 on end # - Onboard Lan
+ device pci 13.3 on end # - PCIe-A 3
+ device pci 14.0 on end # - PCIe-B 0
+ device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT)
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 on end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 on end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 on end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1b.0 on end # - SDCARD
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 on end # - SDIO
+ device pci 1f.0 on end # - LPC
+ device pci 1f.1 on end # - SMBUS
end
end
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13910
-gerrit
commit 094bf1f2ad130dbe5bd37e43fa5da16e72f11488
Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Date: Fri Mar 4 21:33:04 2016 -0800
soc/apollolake: Enable all CPU cores using the parallel MP lib
This is the minimal setup needed to get all CPU cores enabled. That
includes sending an IPI to APs and setting up MTRRs. Microcode updates
are not performed for two reasons:
* CSE (Converged Security Engine) upgrades the microcode before
releasing reset
* Microcode update files are not available at this point in time
Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 2 +
src/soc/intel/apollolake/cpu.c | 105 +++++++++++++++++++++++++++++
src/soc/intel/apollolake/include/soc/cpu.h | 6 ++
3 files changed, 113 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index dd2213e..3b31f12 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
+subdirs-y += ../../../cpu/x86/cache
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
@@ -24,6 +25,7 @@ romstage-y += memmap.c
romstage-y += mmap_boot.c
smm-y += placeholders.c
+ramstage-y += cpu.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
new file mode 100644
index 0000000..2af6e83
--- /dev/null
+++ b/src/soc/intel/apollolake/cpu.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/cpu.h>
+
+static void cpu_core_init(device_t cpu)
+{
+ /* Turn on cache */
+ x86_enable_cache();
+ /* Set up Memory Type Range Registers */
+ x86_setup_mtrrs();
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = cpu_core_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
+ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
+static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
+{
+ msr_t msr;
+ msr = rdmsr(MSR_CORE_THREAD_COUNT);
+ *num_virt = (msr.lo >> 0) & 0xffff;
+ *num_phys = (msr.lo >> 16) & 0xffff;
+}
+
+/*
+ * Do essential initialization tasks before APs can be fired up
+ *
+ * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
+ * creates the MTRR solution that the APs will use. Otherwise APs will try to
+ * apply the incomplete solution as the BSP is calculating it.
+ */
+static void bsp_pre_mp_setup(void)
+{
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+}
+
+/*
+ * CPU initialization recipe
+ *
+ * Note that no microcode update is passed to the init function. CSE updates
+ * the microcode on all cores before releasing them from reset. That means that
+ * the BSP and all APs will come up with the same microcode revision.
+ */
+static struct mp_flight_record flight_plan[] = {
+ /* NOTE: MTRR solution must be calculated before firing up the APs */
+ MP_FR_NOBLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
+};
+
+void apollolake_init_cpus(device_t dev)
+{
+ unsigned int num_virt_cores, num_phys_cores;
+
+ /* Pre-flight check */
+ bsp_pre_mp_setup();
+
+ /* Find CPU topology */
+ read_cpu_topology(&num_phys_cores, &num_virt_cores);
+ printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
+ num_phys_cores, num_virt_cores);
+
+ /* Systems check */
+ struct mp_params flight_data_recorder = {
+ .num_cpus = num_virt_cores,
+ .parallel_microcode_load = 0,
+ .microcode_pointer = NULL,
+ .adjust_apic_id = NULL,
+ .flight_plan = flight_plan,
+ .num_records = ARRAY_SIZE(flight_plan),
+ };
+
+ /* Clear for take-off */
+ if (mp_init(dev->link_list, &flight_data_recorder) < 0)
+ printk(BIOS_ERR, "MP initialization failure.\n");
+}
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 870f474..765be70 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -14,12 +14,18 @@
#define _SOC_APOLLOLAKE_CPU_H_
#include <cpu/x86/msr.h>
+#include <device/device.h>
#define CPUID_APOLLOLAKE_A0 0x506c8
+#define CPUID_APOLLOLAKE_B0 0x506c9
#define MSR_PLATFORM_INFO 0xce
#define MSR_POWER_MISC 0x120
+#define MSR_CORE_THREAD_COUNT 0x35
#define BASE_CLOCK_MHZ 100
+void apollolake_init_cpus(struct device *dev);
+
+
#endif /* _SOC_APOLLOLAKE_CPU_H_ */