coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cbmem: Add utility to get memory region occupied by cbmem
by Andrey Petrov 09 Mar '16

09 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13363 -gerrit commit 08db53ac5d0b11efcd9824ae4056c099b069a110 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Nov 16 13:26:33 2015 -0800 cbmem: Add utility to get memory region occupied by cbmem Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/include/cbmem.h | 2 ++ src/lib/imd_cbmem.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efaa44f..2e947a1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -109,6 +109,8 @@ int cbmem_recovery(int s3resume); void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +/* Get location and size of CBMEM region in memory */ +void cbmem_region_used(uintptr_t *base, size_t *size); /* Indicate to each hook if cbmem is being recovered or not. */ typedef void (* const cbmem_init_hook_t)(int is_recovery); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 49faad9..4b07959 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -263,6 +263,13 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } +void cbmem_region_used(uintptr_t *base, size_t *size) +{ + void *baseptr; + imd_region_used(cbmem_get_imd(), &baseptr, size); + *base = (uintptr_t)baseptr; +} + void cbmem_add_bootmem(void) { void *base = NULL;

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Patch set updated for coreboot: soc/apollolake: Add memory and reserve MMIO resources
by Andrey Petrov 09 Mar '16

09 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13360 -gerrit commit 835e44b38aacde8b7dc7f26e30f94aa8ef3c4151 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jan 15 18:05:12 2016 -0800 soc/apollolake: Add memory and reserve MMIO resources This adds most important MMIO reserved memory resources, real DRAM memory resources, and some DRAM resources that can not be used as RAM for whatever reason. Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/northbridge.c | 143 +++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 8581607..4e05726 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -33,6 +33,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c +ramstage-y += northbridge.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c new file mode 100644 index 0000000..efea23b --- /dev/null +++ b/src/soc/intel/apollolake/northbridge.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <soc/iomap.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/northbridge.h> +#include <soc/pci_ids.h> + +static uint32_t get_bar(device_t dev, unsigned int index) +{ + uint32_t bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled return 0 else strip enabled bit */ + return (bar & 1) ? (bar & ~1) : 0; +} + +static int mc_add_fixed_mmio_resources(device_t dev, int index) +{ + struct resource *res; + + /* PCI extended config region */ + res = new_resource(dev, index++); + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + /* only last 4 bits encode BAR */ + res->base = get_bar(dev, PCIEXBAR) & 0xf0000000; + res->size = PCIEX_SIZE; + + /* Memory Controller HUB */ + res = new_resource(dev, index++); + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + /* BITS 31:15 encode BAR */ + res->base = get_bar(dev, MCHBAR) & 0xffff8000; + res->size = MCH_BASE_SIZE; + return index; +} + + +static int mc_add_dram_resources(device_t dev, int index) +{ + unsigned long base_k, size_k; + uint32_t bgsm, bdsm, tolud, tseg; + uint64_t touud; + struct resource *resource; + + bgsm = ALIGN_DOWN(pci_read_config32(dev, BGSM), MiB); + bdsm = ALIGN_DOWN(pci_read_config32(dev, BDSM), MiB); + tolud = ALIGN_DOWN(pci_read_config32(dev, TOLUD), MiB); + tseg = ALIGN_DOWN(pci_read_config32(dev, TSEG), MiB); + + /* TOUUD is naturally a 64 bit integer */ + touud = ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB); + touud |= (uint64_t)pci_read_config32(dev, TOUUD + + sizeof(uint32_t)) << 32; + + /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ + ram_resource(dev, index++, 0, 640); + + /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */ + base_k = 768; + size_k = (tseg >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG -> BGSM */ + resource = new_resource(dev, index++); + resource->base = tseg; + resource->size = bgsm - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + + /* BGSM -> BDSM */ + resource = new_resource(dev, index++); + resource->base = bgsm; + resource->size = bdsm - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* BDSM -> TOLUD */ + resource = new_resource(dev, index++); + resource->base = bdsm; + resource->size = tolud - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* 4G -> TOUUD */ + base_k = 4ULL*GiB >> 10; + size_k = (touud >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, index++, 640, 128); + + /* 0xe0000 - 0xfffff: PAM area */ + reserved_ram_resource(dev, index++, 768, 256); + + return index; +} + +static void northbridge_read_resources(device_t dev) +{ + + int index = 0; + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources. */ + index = mc_add_fixed_mmio_resources(dev, index); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, index); +} + +static struct device_operations northbridge_ops = { + .read_resources = northbridge_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = DEVICE_NOOP, + .enable = DEVICE_NOOP +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEV_ID_APOLLOLAKE_NB +};

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Add configuration for memory training
by Andrey Petrov 09 Mar '16

09 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13870 -gerrit commit 5fcbad0b0c270d7ae975736d88e80e03255b6746 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Mar 1 17:03:23 2016 -0800 mainboard/intel/apollolake_rvp: Add configuration for memory training Pass memory training information to MemoryInit, so memory training can be completed. Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/romstage.c | 125 +++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 7cfef9f..99fa5a9 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1 +1,124 @@ -/* Nothing here yet, but this file is needed by the build system */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <fsp/api.h> +#include <soc/fsp/FspmUpd.h> + +static const uint8_t swizzling_rvp1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static const uint8_t swizzling0_rvp2[] = { + 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1, + 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9, +}; + +static const uint8_t swizzling1_rvp2[] = { + 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4, + 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25, +}; + +static const uint8_t swizzling2_rvp2[] = { + 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18, + 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2, +}; + +static const uint8_t swizzling3_rvp2[] = { + 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19, + 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, +}; + +static void rvp1_fill_memory_params(struct FSPM_UPD *mupd) +{ + mupd->FspmConfig.Profile = 33; + mupd->FspmConfig.DIMM0SPDAddress = 0xa0; + mupd->FspmConfig.DIMM1SPDAddress = 0xa4; + mupd->FspmConfig.Ch0_RankEnable = 0; + mupd->FspmConfig.Ch0_DeviceWidth = 0; + mupd->FspmConfig.Ch0_DramDensity = 0; + mupd->FspmConfig.Ch0_Option = 3; + mupd->FspmConfig.Ch1_RankEnable = 0; + mupd->FspmConfig.Ch1_DeviceWidth = 0; + mupd->FspmConfig.Ch1_DramDensity = 0; + mupd->FspmConfig.Ch1_Option = 3; + mupd->FspmConfig.Ch2_RankEnable = 0; + mupd->FspmConfig.Ch2_DeviceWidth = 0; + mupd->FspmConfig.Ch2_DramDensity = 0; + mupd->FspmConfig.Ch2_Option = 3; + mupd->FspmConfig.Ch3_RankEnable = 0; + mupd->FspmConfig.Ch3_DeviceWidth = 0; + mupd->FspmConfig.Ch3_DramDensity = 0; + mupd->FspmConfig.Ch3_Option = 3; + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); +} + +static void rvp2_fill_memory_params(struct FSPM_UPD *mupd) +{ + mupd->FspmConfig.Profile = 5; + mupd->FspmConfig.DIMM0SPDAddress = 0; + mupd->FspmConfig.DIMM1SPDAddress = 0; + mupd->FspmConfig.Ch0_RankEnable = 3; + mupd->FspmConfig.Ch0_DeviceWidth = 2; + mupd->FspmConfig.Ch0_DramDensity = 0; + mupd->FspmConfig.Ch0_Option = 3; + mupd->FspmConfig.Ch1_RankEnable = 3; + mupd->FspmConfig.Ch1_DeviceWidth = 2; + mupd->FspmConfig.Ch1_DramDensity = 0; + mupd->FspmConfig.Ch1_Option = 3; + mupd->FspmConfig.Ch2_RankEnable = 3; + mupd->FspmConfig.Ch2_DeviceWidth = 2; + mupd->FspmConfig.Ch2_DramDensity = 0; + mupd->FspmConfig.Ch2_Option = 3; + mupd->FspmConfig.Ch3_RankEnable = 3; + mupd->FspmConfig.Ch3_DeviceWidth = 2; + mupd->FspmConfig.Ch3_DramDensity = 0; + mupd->FspmConfig.Ch3_Option = 3; + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, swizzling0_rvp2, + sizeof(swizzling0_rvp2)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, swizzling1_rvp2, + sizeof(swizzling1_rvp2)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, swizzling2_rvp2, + sizeof(swizzling2_rvp2)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling3_rvp2, + sizeof(swizzling3_rvp2)); +} + +void mainboard_memory_init_params(struct FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.MemoryDown = 1; + mupd->FspmConfig.DDR3LPageSize = 0; + mupd->FspmConfig.DDR3LASR = 0; + mupd->FspmConfig.ScramblerSupport = 1; + mupd->FspmConfig.ChannelHashMask = 0; + mupd->FspmConfig.SliceHashMask = 0; + mupd->FspmConfig.InterleavedMode = 0; + mupd->FspmConfig.ChannelsSlicesEnable = 0; + mupd->FspmConfig.MinRefRate2xEnable = 0; + mupd->FspmConfig.DualRankSupportEnable = 1; + mupd->FspmConfig.DisableFastBoot = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.LowMemoryMaxValue = 0; + mupd->FspmConfig.HighMemoryMaxValue = 0; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) + rvp1_fill_memory_params(mupd); + else + rvp2_fill_memory_params(mupd); +}

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New patch to review for coreboot: nb/amd/mct_ddr3: Require minumum training quality for both read and write
by Timothy Pearson 09 Mar '16

09 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13993 -gerrit commit 422e64eec6d7d18bb5b5f773514c0b6d0ff25ad3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 16:44:39 2016 -0600 nb/amd/mct_ddr3: Require minumum training quality for both read and write The existing MCT code proceeded to the next DRAM training phase if the minimum lane quality standard passed for either the read or write direction. Ensure that both pass for a given set of delay values before proceeding to the next training phase. Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 19a7acb..d2ecefa 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1318,6 +1318,8 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t write_iter; uint8_t read_iter; uint8_t check_antiphase; + uint8_t passing_read_dqs_delay_found; + uint8_t passing_write_dqs_delay_found; uint16_t initial_write_dqs_delay[MAX_BYTE_LANES]; uint16_t initial_read_dqs_delay[MAX_BYTE_LANES]; uint16_t initial_write_data_timing[MAX_BYTE_LANES]; @@ -1385,6 +1387,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, memcpy(current_write_data_delay, initial_write_data_timing, sizeof(current_write_data_delay)); for (lane = lane_start; lane < lane_end; lane++) { + passing_read_dqs_delay_found = 0; + passing_write_dqs_delay_found = 0; + /* 2.10.5.8.4 (2) * For each Write Data Delay value from Write DQS Delay to Write DQS Delay + 1 UI */ @@ -1510,7 +1515,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* Program the Read DQS Timing Control register with the center of the passing window */ current_read_dqs_delay[lane] = region_center << 1; - passing_dqs_delay_found[lane] = 1; + passing_read_dqs_delay_found = 1; /* Commit the current Read DQS Timing Control settings to the hardware registers */ write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); @@ -1560,7 +1565,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, current_write_dqs_delay[lane] = ((best_pos + initial_write_dqs_delay[lane]) + (best_count / 3)); else current_write_dqs_delay[lane] = ((best_pos + initial_write_dqs_delay[lane]) + (best_count / 2)); - passing_dqs_delay_found[lane] = 1; + passing_write_dqs_delay_found = 1; /* Commit the current Write DQS Timing Control settings to the hardware registers */ write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); @@ -1574,6 +1579,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* Reprogram the Write DQS Timing Control register with the original settings */ write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); } + + if (passing_read_dqs_delay_found && passing_write_dqs_delay_found) + passing_dqs_delay_found[lane] = 1; } #ifdef PRINT_PASS_FAIL_BITMAPS

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Patch merged into coreboot/master: x86 chipsets: utilize x86_setup_mtrrs_with_detect()
by gerrit＠coreboot.org 08 Mar '16

08 Mar '16

the following patch was just integrated into master: commit 2a08137feebaf0f8f55feeff00096f5a9d03f44c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:23:47 2016 -0600 x86 chipsets: utilize x86_setup_mtrrs_with_detect() For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13936 for details. -gerrit

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Patch set updated for coreboot: skylake mainboards: Configure gpio PADRSTCFG to PLTRST
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13992 -gerrit commit b51e39a0abd9701e63c01c7935964be7494240a8 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Feb 29 13:20:44 2016 +0530 skylake mainboards: Configure gpio PADRSTCFG to PLTRST With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki(a)intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 8 +++--- src/mainboard/google/lars/gpio.h | 48 ++++++++++++++++++------------------ src/mainboard/intel/kunimitsu/gpio.h | 10 ++++---- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 0503e3e..05897eb 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ @@ -155,14 +155,14 @@ static const struct pad_config gpio_table[] = { /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index 5aee237..e187795 100644 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -72,19 +72,19 @@ static const struct pad_config gpio_table[] = { /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ /* GPP_A16 */ -/* SD_PWR_EN */ /* GPP_A17 */ -/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ /* GPP_A19 */ -/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), -/* ISH_GP5 */ /* GPP_A23 */ -/* CORE_VID0 */ /* GPP_B0 */ -/* CORE_VID1 */ /* GPP_B1 */ -/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), -/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), +/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), +/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), +/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), @@ -152,15 +152,15 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ /* GPP_D21 */ /* ITCH_SPI_D3 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), -/* SATAXPCIE1 */ /* GPP_E1 */ -/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* CPU_GP0 */ /* GPP_E3 */ -/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), -/* SATA_DEVSLP1 */ /* GPP_E5 */ -/* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), -/* SATALED# */ /* GPP_E8 */ +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* TCH_PNL_INTR* */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), @@ -186,8 +186,8 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), -/* I2C5_SCL */ /* GPP_F11 */ +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index de51fb5..d310396 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), @@ -160,14 +160,14 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), /* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SSD_PEDET */ PAD_CFG_NC(GPP_E2), /* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -181,7 +181,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),

1 0

Patch set updated for coreboot: soc/intel/skylake: add option to enable VR specific mailbox cmd
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13982 -gerrit commit 82af47f386bc6453016dd3696ad42ff5e2e10911 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Feb 24 14:31:40 2016 +0530 soc/intel/skylake: add option to enable VR specific mailbox cmd Adding an option to enable VR specific mailbox command. When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917 Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329393 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.c | 4 ++++ src/soc/intel/skylake/chip.h | 11 +++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b5bcc65..dbf7785 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -410,6 +410,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->TcoIrqSelect = config->TcoIrqSelect; /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; + params->SendVrMbxCmd = config->SendVrMbxCmd; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, @@ -1011,6 +1012,9 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, original->SerialIoI2cVoltage[5], params->SerialIoI2cVoltage[5]); + fsp_display_upd_value("SendVrMbxCmd", 1, + original->SendVrMbxCmd, + params->SendVrMbxCmd); } static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 6203916..e18b45a 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -312,8 +312,8 @@ struct soc_intel_skylake_config { */ u8 SerialIrqConfigStartFramePulse; u8 FspSkipMpInit; - - /* VrConfig Settings for 5 domains + /* + * VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ @@ -328,6 +328,13 @@ struct soc_intel_skylake_config { u8 PmTimerDisabled; /* Intel Speed Shift Technology */ u8 speed_shift_enable; + /* + * Enable VR specific mailbox command + * When set, an extra VR mailbox command specifically + * for the MPS IMPV8 VR will be sent. + * 0 - Don't Send, 1 - Send + */ + u8 SendVrMbxCmd; }; typedef struct soc_intel_skylake_config config_t;

1 0

Patch set updated for coreboot: glados/chell: send an extra VR mailbox command
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13983 -gerrit commit 409068a91cc1d58f28a03b49b29669ba09266748 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Feb 24 14:56:32 2016 +0530 glados/chell: send an extra VR mailbox command MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 15 +++++++++------ src/mainboard/google/glados/devicetree.cb | 15 +++++++++------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index bb925ce..428779a 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -63,7 +63,7 @@ chip soc/intel/skylake #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 0 | 0 | 0 | 0 | 0 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 34A | 35A | 35A | @@ -75,7 +75,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), @@ -88,7 +88,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -101,7 +101,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -114,7 +114,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -127,7 +127,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -174,6 +174,9 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 89fcff8..c4b89af 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -63,7 +63,7 @@ chip soc/intel/skylake #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 0 | 0 | 0 | 0 | 0 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| IccMax | 7A | 34A | 34A | 35A | 35A | @@ -75,7 +75,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), @@ -88,7 +88,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -101,7 +101,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), @@ -114,7 +114,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -127,7 +127,7 @@ chip soc/intel/skylake .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, - .psi4enable = 0, + .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), @@ -174,6 +174,9 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + device cpu_cluster 0 on device lapic 0 on end end

1 0

Patch set updated for coreboot: intel/fsp1.1: Mark graphics init done after SiliconInit phase
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13986 -gerrit commit 427343f6cc84b81b1b84e54bb74d935e0e99017f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 7 13:21:56 2016 -0800 intel/fsp1.1: Mark graphics init done after SiliconInit phase If the VBT was provided to the FSP GOP driver then graphics init will be done as part of SiliconInit step and we can mark that when it is completed. This will result in the "oprom" flag being set properly in the coreboot gpio table and the netboot firmware will have video. BUG=chrome-os-partner:50864 BRANCH=glados TEST=boot image.net.bin on chell and get working graphics without being setuck in a reboot loop thinking graphics needs to be started when it already has been. Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331301 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240) Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5 Original-Reviewed-on: https://chromium-review.googlesource.com/331355 --- src/drivers/intel/fsp1_1/ramstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 277b609..1e4873e 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootmode.h> #include <arch/acpi.h> #include <cbmem.h> #include <cbfs.h> @@ -140,6 +141,11 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) timestamp_add_now(TS_FSP_SILICON_INIT_END); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + /* Mark graphics init done after SiliconInit if VBT was provided */ + if (IS_ENABLED(CONFIG_GOP_SUPPORT) && + silicon_init_params.GraphicsConfigPtr) + gfx_set_init_done(1); + display_hob_info(fsp_info_header); soc_after_silicon_init(); }

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Patch set updated for coreboot: soc/intel/skylake: add option to statically clock gate 8254 timer
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13985 -gerrit commit d037cb198412ce5194d22be9ce1da71bd2c5dfef Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 25 17:17:35 2016 -0600 soc/intel/skylake: add option to statically clock gate 8254 timer In order to save more power by shutting down clocks add the ability to optionally clock gate the 8254 programmable interrupt timer. When doing this the platforms lose their "PC"-ness which certain payloads and OSes rely on such as SeaBIOS. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Enabled option on chell. Noted the bit is set upon booting. Change-Id: I01f9d177bbde417d1efec2e16656a07dcebccbde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 662575aa6a63656dedfa0ce1f202f5fac0205477 Original-Change-Id: Ib4a613cf1c28fc96c36fa2987c4b58a05beab178 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329411 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331171 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/skylake/chip.h | 2 ++ src/soc/intel/skylake/include/soc/pcr.h | 3 +++ src/soc/intel/skylake/lpc.c | 13 +++++++++++++ 3 files changed, 18 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e18b45a..ca902ae 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -335,6 +335,8 @@ struct soc_intel_skylake_config { * 0 - Don't Send, 1 - Send */ u8 SendVrMbxCmd; + /* Statically clock gate 8254 PIT. */ + u8 clock_gate_8254; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index 8a46cd1..c3e8d83 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -60,6 +60,9 @@ #define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 /* PIRQH Routing Control Register*/ #define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 +/* ITSS Power reduction control */ +#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 +# define CGE8254 (1 << 2) /* IO Trap PCRs */ /* Trap status Register */ diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index e47026c..cebd836 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -154,6 +154,18 @@ static const struct reg_script pch_misc_init_script[] = { REG_SCRIPT_END }; +static void clock_gate_8254(struct device *dev) +{ + config_t *config = dev->chip_info; + const uint32_t cge8254_mask = CGE8254; + + if (!config->clock_gate_8254) + return; + + pcr_andthenor32(PID_ITSS, R_PCH_PCR_ITSS_ITSSPRC, + ~cge8254_mask, cge8254_mask); +} + static void lpc_init(struct device *dev) { /* Legacy initialization */ @@ -165,6 +177,7 @@ static void lpc_init(struct device *dev) pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); + clock_gate_8254(dev); } static void pch_lpc_add_mmio_resources(device_t dev)

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coreboot-gerrit March 2016