coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Add a driver for the parade ps8640
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13981 -gerrit commit d86cbde8db6750a557c9eb9cb7f244954d83befa Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Fri Jan 8 15:59:46 2016 +0800 Add a driver for the parade ps8640 BRANCH=none BUG=none TEST=none Change-Id: Icf397ce2ffdaed5048367daf2086c067984fea0a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b5a88793ccfc46af196300791a300be67b70f5b1 Original-Change-Id: I75adf2688c9c8b9a2338f7dee5d0ac10e7181529 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321056 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/parade/Kconfig | 1 + src/drivers/parade/Makefile.inc | 1 + src/drivers/parade/ps8640/Kconfig | 24 ++++++++++ src/drivers/parade/ps8640/Makefile.inc | 20 ++++++++ src/drivers/parade/ps8640/ps8640.c | 83 ++++++++++++++++++++++++++++++++++ src/drivers/parade/ps8640/ps8640.h | 49 ++++++++++++++++++++ 6 files changed, 178 insertions(+) diff --git a/src/drivers/parade/Kconfig b/src/drivers/parade/Kconfig index be80bb8..7fe74df 100644 --- a/src/drivers/parade/Kconfig +++ b/src/drivers/parade/Kconfig @@ -14,3 +14,4 @@ ## source src/drivers/parade/ps8625/Kconfig +source src/drivers/parade/ps8640/Kconfig diff --git a/src/drivers/parade/Makefile.inc b/src/drivers/parade/Makefile.inc index 0470763..06367c1 100644 --- a/src/drivers/parade/Makefile.inc +++ b/src/drivers/parade/Makefile.inc @@ -14,3 +14,4 @@ ## subdirs-$(CONFIG_DRIVER_PARADE_PS8625) += ps8625/ +subdirs-$(CONFIG_DRIVER_PARADE_PS8640) += ps8640/ diff --git a/src/drivers/parade/ps8640/Kconfig b/src/drivers/parade/ps8640/Kconfig new file mode 100644 index 0000000..0a6e931 --- /dev/null +++ b/src/drivers/parade/ps8640/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config DRIVER_PARADE_PS8640 + bool + default n + help + Parade PS8640 MIPI DSI to eDP Converter diff --git a/src/drivers/parade/ps8640/Makefile.inc b/src/drivers/parade/ps8640/Makefile.inc new file mode 100644 index 0000000..27d491f --- /dev/null +++ b/src/drivers/parade/ps8640/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += ps8640.c diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c new file mode 100644 index 0000000..5737923 --- /dev/null +++ b/src/drivers/parade/ps8640/ps8640.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <device/i2c.h> +#include <edid.h> +#include <console/console.h> +#include <timer.h> + +#include "ps8640.h" + +int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + int ret; + u8 edid[EDID_LENGTH * 2]; + u32 edid_size; + + i2c_writeb(bus, chip + 2, PAGE2_I2C_BYPASS, + EDID_I2C_ADDR | I2C_BYPASS_EN); + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0, edid, EDID_LENGTH); + + if (ret != 0) { + printk(BIOS_INFO, "Failed to read EDID.\n"); + return -1; + } + + /* check if edid have extension flag, and read additional EDID data */ + if (edid[EDID_EXTENSION_FLAG]) { + edid_size += EDID_LENGTH; + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, + &edid[EDID_LENGTH], EDID_LENGTH); + if (ret != 0) { + printk(BIOS_INFO, "Failed to read EDID ext block.\n"); + return -1; + } + } + + if (decode_edid(edid, edid_size, out)) { + printk(BIOS_INFO, "Failed to decode EDID.\n"); + return -1; + } + + return 0; +} + +int ps8640_init(uint8_t bus, uint8_t chip) +{ + u8 set_vdo_done; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, 350); + + do { + i2c_readb(bus, chip + 2, PAGE2_GPIO_H, &set_vdo_done); + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Failed to init ps8640.\n"); + return -1; + } + } while ((set_vdo_done & PS_GPIO9) != PS_GPIO9); + + i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); + i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_DIS); + i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); + i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_EN); + + return 0; +} diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h new file mode 100644 index 0000000..ab617a7 --- /dev/null +++ b/src/drivers/parade/ps8640/ps8640.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <edid.h> +#include <types.h> + +#ifndef _PS8640_H_ +#define _PS8640_H_ + +enum { + PAGE2_GPIO_L = 0xa6, + PAGE2_GPIO_H = 0xa7, + PAGE2_I2C_BYPASS = 0xea, + PS_GPIO9 = BIT(1), + I2C_BYPASS_EN = BIT(7), + + PAGE3_SET_ADD = 0xfe, + PAGE3_SET_VAL = 0xff, + VDO_CTL_ADD = 0x13, + VDO_DIS = 0x18, + VDO_EN = 0x1c, +}; + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +int ps8640_init(uint8_t bus, uint8_t chip); +int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out); +#endif +

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New patch to review for coreboot: mediatek/mt8173: pll: raising the CPU core frequency
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13980 -gerrit commit 4aa91182c489a41c33da593f60c7e0b6dab12fe2 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Jan 29 17:25:03 2016 +0800 mediatek/mt8173: pll: raising the CPU core frequency Runs the LITTLE core at highest freqency to speed up the boot time. Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.) BRANCH=none BUG=chrome-os-partner:47422 TEST=flash the bootloader and measure the boottime by cbmem result Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161 Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/324685 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/romstage.c | 22 +++++++++++++++++++++- src/soc/mediatek/mt8173/include/soc/mt6391.h | 2 ++ src/soc/mediatek/mt8173/include/soc/pll.h | 1 + src/soc/mediatek/mt8173/mt6391.c | 17 +++++++++++++++++ src/soc/mediatek/mt8173/pll.c | 6 ++++-- 5 files changed, 45 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index d72693f..3d018a0 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -17,7 +17,7 @@ #include <arch/exception.h> #include <arch/io.h> #include <arch/mmu.h> - +#include <boardid.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -25,14 +25,20 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <symbols.h> +#include <timer.h> #include <timestamp.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/mt6391.h> +#include <soc/pll.h> #include <soc/rtc.h> void main(void) { + int stabilize_usec; + struct stopwatch sw; + timestamp_add_now(TS_START_ROMSTAGE); /* init uart baudrate when pll on */ @@ -41,9 +47,23 @@ void main(void) rtc_boot(); + /* Raise CPU voltage to allow higher frequency */ + stabilize_usec = mt6391_configure_ca53_voltage(1125000); + + stopwatch_init_usecs_expire(&sw, stabilize_usec); + /* init memory */ mt_mem_init(get_sdram_config()); + while (!stopwatch_expired(&sw)) + ; + + /* Set to maximum frequency */ + if (board_id() < 5) + mt_pll_raise_ca53_freq(1600 * MHz); + else + mt_pll_raise_ca53_freq(1700 * MHz); + mt8173_mmu_after_dram(); /* should be called after memory init */ diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h index 392ad63..c2a2ef3 100644 --- a/src/soc/mediatek/mt8173/include/soc/mt6391.h +++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h @@ -98,6 +98,7 @@ enum{ PMIC_RG_VCA15_CON9 = 0x0226, PMIC_RG_VCA15_CON10 = 0x0228, PMIC_RG_VCA15_CON11 = 0x022A, + PMIC_RG_VCA15_CON12 = 0x022C, PMIC_RG_VCA15_CON18 = 0x0238, PMIC_RG_VSRMCA15_CON5 = 0x0244, PMIC_RG_VSRMCA15_CON6 = 0x0246, @@ -291,6 +292,7 @@ enum ldo_voltage { /* * PMIC Exported Function */ +int mt6391_configure_ca53_voltage(int uv); void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel); u32 mt6391_read(u16 reg, u32 mask, u32 shift); void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift); diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index 6d38bb3..9b3cca3 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -286,6 +286,7 @@ void mt_pll_post_init(void); void mt_pll_init(void); void mt_pll_set_aud_div(u32 rate); void mt_pll_enable_ssusb_clk(void); +void mt_pll_raise_ca53_freq(u32 freq); void mt_mem_pll_set_clk_cfg(void); void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params); void mt_mem_pll_config_post(void); diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 21ce7ea..9f5ed0a 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -59,6 +59,23 @@ void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift) return; } +int mt6391_configure_ca53_voltage(int uv) +{ + /* target voltage = 700mv + 6.25mv * buck_val */ + u16 buck_val = (uv - 700000) / 6250; + u16 current_val = mt6391_read(PMIC_RG_VCA15_CON12, 0x7f, 0x0); + + assert(buck_val < (1 << 8)); + mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0); + + /* For buck delay, default slew rate is 6.25mv/0.5us */ + if (buck_val > current_val) + return ((buck_val - current_val) / 2) ; + else + return 0; +} + static void mt6391_configure_vcama(enum ldo_voltage vsel) { /* 2'b00: 1.5V diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index d54538d..1366bb5 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -467,8 +467,6 @@ void mt_pll_post_init(void) clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff); /* select ARMPLL */ - /* TODO: possibly raise ARMPLL frequency here */ - /* NOTICE: raise Vproc voltage before raise ARMPLL frequency */ write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); } @@ -506,6 +504,10 @@ void mt_pll_set_aud_div(u32 rate) } } +void mt_pll_raise_ca53_freq(u32 freq) { + pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ +} + void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params) { u32 mpll_sdm_pcw_20_0 = 0xF13B1;

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New patch to review for coreboot: mediatek/mt8173: add NOR DMA read
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13979 -gerrit commit 606e596968e28d6f236cf6df6dee91c67cd54048 Author: Bayi Cheng <bayi.cheng(a)mediatek.com> Date: Thu Jan 21 21:48:37 2016 +0800 mediatek/mt8173: add NOR DMA read BRANCH=none BUG=none TEST=boot oak to kernel on rev2 Change-Id: I368fcac1cf5e2261d00a34882a7341733ebd0732 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6ea0407f7273bc88613bc23a6fc4c41f9cca1adb Original-Change-Id: Ic422e7265fdd35c573d8cd44280a1f7dc163a6db Original-Signed-off-by: Bayi Cheng <bayi.cheng(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/323932 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/flash_controller.c | 60 ++++++++++++++++++++-- .../mediatek/mt8173/include/soc/flash_controller.h | 15 +++++- 2 files changed, 70 insertions(+), 5 deletions(-) diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 3cd81a2..f662916 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -23,6 +23,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <symbols.h> #include <timer.h> #include <soc/flash_controller.h> @@ -111,21 +112,74 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(65535, buf_len); } -static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) +static int dma_read(u32 addr, u8 *buf, u32 len) { - u8 *buffer = (u8 *)buf; + struct stopwatch sw; + + assert(IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN) && + IS_ALIGNED(len, SFLASH_DMA_ALIGN) && + len <= _dma_coherent_size); + + /* do dma reset */ + write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_SW_RESET); + write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); + /* flash source address and dram dest address */ + write32(&mt8173_nor->fdma_fadr, addr); + write32(&mt8173_nor->fdma_dadr, ((uintptr_t)_dma_coherent )); + write32(&mt8173_nor->fdma_end_dadr, ((uintptr_t)_dma_coherent + len)); + /* start dma */ + write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + while ((read32(&mt8173_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, "dma read timeout!\n"); + return -1; + } + } + + memcpy(buf, _dma_coherent, len); + return 0; +} +static int pio_read(u32 addr, u8 *buf, u32 len) +{ set_sfpaddr(addr); while (len) { if (mt8173_nor_execute_cmd(SFLASH_RD_TRIGGER | SFLASH_AUTOINC)) return -1; - *buffer++ = read8(&mt8173_nor->rdata); + *buf++ = read8(&mt8173_nor->rdata); len--; } return 0; } +static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) +{ + u32 next; + + size_t done = 0; + if (!IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN)) { + next = MIN(ALIGN_UP((uintptr_t)buf, SFLASH_DMA_ALIGN) - + (uintptr_t)buf, len); + if (pio_read(addr, buf, next)) + return -1; + done += next; + } + while (len - done >= SFLASH_DMA_ALIGN) { + next = MIN(_dma_coherent_size, ALIGN_DOWN(len - done, + SFLASH_DMA_ALIGN)); + if (dma_read(addr + done, buf + done, next)) + return -1; + done += next; + } + next = len - done; + if (next > 0 && pio_read(addr + done, buf + done, next)) + return -1; + return 0; +} + static int nor_write(struct spi_flash *flash, u32 addr, size_t len, const void *buf) { diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h index 2527d6b..1d2ac32 100644 --- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h @@ -27,6 +27,7 @@ enum { SFLASHNAME_LENGTH = 16, SFLASH_WRITE_IN_PROGRESS = 1, SFLASH_COMMAND_ENABLE = 0x30, + SFLASH_DMA_ALIGN = 0x10, /* NOR flash controller commands */ SFLASH_RD_TRIGGER = 1 << 0, @@ -38,7 +39,11 @@ enum { /* NOR flash commands */ SFLASH_OP_WREN = 0x6, SECTOR_ERASE_CMD = 0x20, - SFLASH_UNPROTECTED = 0x0 + SFLASH_UNPROTECTED = 0x0, + /* DMA commands */ + SFLASH_DMA_TRIGGER = 1 << 0, + SFLASH_DMA_SW_RESET = 1 << 1, + SFLASH_DMA_WDLE_EN = 1 << 2 }; /* register Offset */ @@ -72,8 +77,14 @@ struct mt8173_nor_regs { u32 radr3; u32 read_dual; u32 delsel[3]; + u32 reserved[397]; + u32 cfg1_bri[2]; + u32 fdma_ctl; + u32 fdma_fadr; + u32 fdma_dadr; + u32 fdma_end_dadr; }; -check_member(mt8173_nor_regs, delsel[2], 0xD8); +check_member(mt8173_nor_regs, fdma_end_dadr, 0x724); static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE; struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi);

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New patch to review for coreboot: device/i2c: Add i2c_read_bytes() API
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13978 -gerrit commit f434ce5218fb46b402fe4fdc92b7610884fa069d Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Mon Feb 1 17:33:49 2016 +0800 device/i2c: Add i2c_read_bytes() API Add multi-bytes read support. BRANCH=none BUG=none TEST=saw edid log and dev screen Change-Id: I106be98e751e2a3b998ccaedb28f71f3c6e18994 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 94ee0b834947e8d971943aa24e61a9353c7b7306 Original-Change-Id: Iac5fe497da92b7d09383e0d6a04d98709aea5b20 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/325211 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/include/device/i2c.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index 78817bb..8e59ba7 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -88,6 +88,28 @@ static inline int i2c_write_raw(unsigned bus, uint8_t chip, uint8_t *data, } /** + * Read multi-bytes with two segments in one frame + * + * [start][slave addr][w][register addr][start][slave addr][r][data...][stop] + */ +static inline int i2c_read_bytes(unsigned bus, uint8_t chip, uint8_t reg, + uint8_t *data, int len) +{ + struct i2c_seg seg[2]; + + seg[0].read = 0; + seg[0].chip = chip; + seg[0].buf = ® + seg[0].len = 1; + seg[1].read = 1; + seg[1].chip = chip; + seg[1].buf = data; + seg[1].len = len; + + return i2c_transfer(bus, seg, ARRAY_SIZE(seg)); +} + +/** * Read a byte with two segments in one frame * * [start][slave addr][w][register addr][start][slave addr][r][data][stop]

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New patch to review for coreboot: google/oak: Configure USB OC pins
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13977 -gerrit commit 599d2cc0fca42cdac2f1949568d61bdd404375de Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Jan 11 10:05:46 2016 +0800 google/oak: Configure USB OC pins BRANCH=none BUG=none TEST=none Change-Id: If7244d0050833c676de72106d1c8473dd8f290a8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 89356785e66eb6d5b52fdf09933d2d28d9f67a90 Original-Change-Id: I94dda9834da6553795e7f3f65ff267fdcb6b7d47 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321055 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index df0945b..192f4b3 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -135,8 +135,21 @@ static void configure_usb(void) { setup_usb_host(); - if (board_id() > 3) + if (board_id() > 3) { + /* Enable current limit */ gpio_output(PAD_CM2MCLK, 1); + /* Configure USB OC pins*/ + gpio_input_pullup(PAD_MSDC3_DSL); + gpio_input_pullup(PAD_CMPCLK); + gpio_input_pullup(PAD_PCM_SYNC); + } + + if (board_id() > 4) { + /* USB 2.0 type A port over current interrupt pin(low active) */ + gpio_input_pullup(PAD_UCTS2); + /* USB 2.0 type A port BC1.2 STATUS(low active) */ + gpio_input_pullup(PAD_AUD_DAT_MISO); + } } static void configure_usb_hub(void)

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New patch to review for coreboot: google/oak: Config USB Hub for rev5
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13976 -gerrit commit 29d8f29591da2cf4ba3e944a75134dbbe745a25d Author: Ben Lok <ben.lok(a)mediatek.com> Date: Fri Jan 8 13:10:34 2016 +0800 google/oak: Config USB Hub for rev5 Reset pin of USB Hub is connected to GPIO118, it is low active. Config GPIO118 as GPO and output high. BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I630cfd1c1019447736e7e5b286790fead4bdcfb6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b4b5cd98d0b3c5d2bab408ecebebc924d1f2b7df Original-Change-Id: I1ea0e1baac3da4d13301307f01bbe51e108298dd Original-Signed-off-by: Ben Lok <ben.lok(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321054 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 289aa32..df0945b 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -139,6 +139,13 @@ static void configure_usb(void) gpio_output(PAD_CM2MCLK, 1); } +static void configure_usb_hub(void) +{ + /* set usb hub reset pin (low active) to high */ + if (board_id() > 4) + gpio_output(PAD_UTXD3, 1); +} + /* Setup backlight control pins as output pin and power-off by default */ static void configure_backlight(void) { @@ -176,6 +183,7 @@ static void mainboard_init(device_t dev) configure_audio(); configure_backlight(); configure_usb(); + configure_usb_hub(); configure_bl31(); elog_init();

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New patch to review for coreboot: google/oak: Config audio for rev5
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13975 -gerrit commit 8e4ee4378157c428667d1e32505614882dd3cdf7 Author: Koro Chen <koro.chen(a)mediatek.com> Date: Wed Dec 30 17:31:44 2015 +0800 google/oak: Config audio for rev5 BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: Ibdafa4ffe0baf5231654e67612b7ca59d835b602 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 63fedfec26ba1444934e348ce59609fa88e12de5 Original-Change-Id: Ifbbf8d2b3b6e163481843308c2e3edc4a55f90c6 Original-Signed-off-by: Koro Chen <koro.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319988 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index fe6bbcc..289aa32 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -108,7 +108,8 @@ static void configure_audio(void) mt6391_configure_ldo(LDO_VCAMA, LDO_1P8); /* reset ALC5676 */ - gpio_output(PAD_LCM_RST, 1); + if (board_id() < 5) + gpio_output(PAD_LCM_RST, 1); /* SoC I2S */ gpio_set_mode(PAD_I2S0_LRCK, PAD_I2S0_LRCK_FUNC_I2S1_WS); @@ -116,6 +117,8 @@ static void configure_audio(void) gpio_set_mode(PAD_I2S0_MCK, PAD_I2S0_MCK_FUNC_I2S1_MCK); gpio_set_mode(PAD_I2S0_DATA0, PAD_I2S0_DATA0_FUNC_I2S1_DO_1); gpio_set_mode(PAD_I2S0_DATA1, PAD_I2S0_DATA1_FUNC_I2S2_DI_2); + if (board_id() >= 5) + gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1); /* codec ext MCLK ON */ mt6391_gpio_output(MT6391_KP_COL4, 1);

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New patch to review for coreboot: google/oak: Remove obsolete Rev0 setting
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13974 -gerrit commit 64a7f4e6467b875207915603b3d24298c827c0a1 Author: Koro Chen <koro.chen(a)mediatek.com> Date: Wed Dec 30 17:50:56 2015 +0800 google/oak: Remove obsolete Rev0 setting BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I65aa87e88cf812fdb490933de1a3b121866a2694 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f703f7e71ae6ffc0f1ac0e70486d087a28da5ba Original-Change-Id: I8d794464d45ea69f9a46f7ebc505f6ec2127f204 Original-Signed-off-by: Koro Chen <koro.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319987 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index e58d168..fe6bbcc 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -100,24 +100,12 @@ static void configure_audio(void) { mtcmos_audio_power_on(); - /* regulator for codecs */ - switch (board_id()) { - case 0: - /* vgp1 set to 1.22V */ - mt6391_configure_ldo(LDO_VCAMD, LDO_1P22); - /* vgp4 set to 1.8V */ - mt6391_configure_ldo(LDO_VGP4, LDO_1P8); - break; - default: - /* board from Rev1 */ - /* vgp1 set to 1.8V */ - mt6391_configure_ldo(LDO_VCAMD, LDO_1P8); - /* delay 1ms for realtek's power sequence request */ - mdelay(1); - /* vcama set to 1.8V */ - mt6391_configure_ldo(LDO_VCAMA, LDO_1P8); - break; - } + /* vgp1 set to 1.8V */ + mt6391_configure_ldo(LDO_VCAMD, LDO_1P8); + /* delay 1ms for realtek's power sequence request */ + mdelay(1); + /* vcama set to 1.8V */ + mt6391_configure_ldo(LDO_VCAMA, LDO_1P8); /* reset ALC5676 */ gpio_output(PAD_LCM_RST, 1);

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New patch to review for coreboot: google/oak: Enable TP_SHIFT_EN for the revisons before 5 only
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13973 -gerrit commit 8ee164ee5145feb581b725b91ebf619a0647777a Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Dec 28 17:22:33 2015 +0800 google/oak: Enable TP_SHIFT_EN for the revisons before 5 only BRANCH=none BUG=none TEST=emerge coreboot Change-Id: Ic46490a56a6a8146b91a055b9ce5d5bb23bc7a49 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 082ce1848bf37bba369fd0dccc4cf3fc83a8a018 Original-Change-Id: I58f009d2fc03cf5a52b4dbd042a92973cde4d035 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320029 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index b09703e..e58d168 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -176,7 +176,8 @@ static void mainboard_init(device_t dev) /* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which * also contains the PS8640 eDP brige and the USB hub. */ - mt6391_gpio_output(MT6391_KP_ROW2, 1); + if (board_id() < 5) + mt6391_gpio_output(MT6391_KP_ROW2, 1); /* Config SD card detection pin */ gpio_input(PAD_EINT1); /* SD_DET */

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New patch to review for coreboot: google/oak: da9212 gpio configuration for rev5
by Patrick Georgi 08 Mar '16

08 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13972 -gerrit commit f805baf6403fea561658c21690bbbaeb8f1d65be Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Wed Dec 23 11:45:29 2015 +0800 google/oak: da9212 gpio configuration for rev5 BRANCH=none BUG=none TEST=none Change-Id: Ib44a9e8ca94727809e47831228f4742c25a53977 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: da9185c22264440da822aa252c0c5d2aef78b455 Original-Change-Id: I98c2ad757d0cd0e3234e49392091784b43a106e7 Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320028 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/mainboard.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index c330fac..b09703e 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -40,9 +40,9 @@ static void register_da9212_to_bl31(void) }, .i2c_bus = 1, .ic_en = { - .type = PARAM_GPIO_SOC, + .type = PARAM_GPIO_MT6391, .polarity = PARAM_GPIO_ACTIVE_HIGH, - .index = PAD_UCTS2, + .index = MT6391_KP_ROW3, }, .en_a = { .type = PARAM_GPIO_MT6391, @@ -53,6 +53,10 @@ static void register_da9212_to_bl31(void) .type = PARAM_GPIO_NONE, }, }; + if (board_id() == 2) { + param_da9212.ic_en.type = PARAM_GPIO_SOC; + param_da9212.ic_en.index = PAD_UCTS2; + } register_bl31_param(&param_da9212.h); /* Init i2c bus Timing register for da9212 */ @@ -79,13 +83,16 @@ static void register_mt6311_to_bl31(void) static void configure_bl31(void) { switch (board_id()) { - case 2: - register_da9212_to_bl31(); - break; - default: + case 3: + case 4: /* rev-3 and rev-4 use mt6311 as external buck */ register_mt6311_to_bl31(); break; + case 2: + default: + /* rev-2 and rev-5 use da9212 as external buck */ + register_da9212_to_bl31(); + break; } }

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coreboot-gerrit March 2016