coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Add configuration for memory training
by Andrey Petrov 07 Mar '16

07 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13870 -gerrit commit 3bacbd9a6d345d8de794d60f97c1b524b9f53898 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Mar 1 17:03:23 2016 -0800 mainboard/intel/apollolake_rvp: Add configuration for memory training Pass memory training information to MemoryInit, so memory training can be completed. Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/romstage.c | 125 +++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 7cfef9f..99fa5a9 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1 +1,124 @@ -/* Nothing here yet, but this file is needed by the build system */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <fsp/api.h> +#include <soc/fsp/FspmUpd.h> + +static const uint8_t swizzling_rvp1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static const uint8_t swizzling0_rvp2[] = { + 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1, + 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9, +}; + +static const uint8_t swizzling1_rvp2[] = { + 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4, + 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25, +}; + +static const uint8_t swizzling2_rvp2[] = { + 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18, + 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2, +}; + +static const uint8_t swizzling3_rvp2[] = { + 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19, + 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, +}; + +static void rvp1_fill_memory_params(struct FSPM_UPD *mupd) +{ + mupd->FspmConfig.Profile = 33; + mupd->FspmConfig.DIMM0SPDAddress = 0xa0; + mupd->FspmConfig.DIMM1SPDAddress = 0xa4; + mupd->FspmConfig.Ch0_RankEnable = 0; + mupd->FspmConfig.Ch0_DeviceWidth = 0; + mupd->FspmConfig.Ch0_DramDensity = 0; + mupd->FspmConfig.Ch0_Option = 3; + mupd->FspmConfig.Ch1_RankEnable = 0; + mupd->FspmConfig.Ch1_DeviceWidth = 0; + mupd->FspmConfig.Ch1_DramDensity = 0; + mupd->FspmConfig.Ch1_Option = 3; + mupd->FspmConfig.Ch2_RankEnable = 0; + mupd->FspmConfig.Ch2_DeviceWidth = 0; + mupd->FspmConfig.Ch2_DramDensity = 0; + mupd->FspmConfig.Ch2_Option = 3; + mupd->FspmConfig.Ch3_RankEnable = 0; + mupd->FspmConfig.Ch3_DeviceWidth = 0; + mupd->FspmConfig.Ch3_DramDensity = 0; + mupd->FspmConfig.Ch3_Option = 3; + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); +} + +static void rvp2_fill_memory_params(struct FSPM_UPD *mupd) +{ + mupd->FspmConfig.Profile = 5; + mupd->FspmConfig.DIMM0SPDAddress = 0; + mupd->FspmConfig.DIMM1SPDAddress = 0; + mupd->FspmConfig.Ch0_RankEnable = 3; + mupd->FspmConfig.Ch0_DeviceWidth = 2; + mupd->FspmConfig.Ch0_DramDensity = 0; + mupd->FspmConfig.Ch0_Option = 3; + mupd->FspmConfig.Ch1_RankEnable = 3; + mupd->FspmConfig.Ch1_DeviceWidth = 2; + mupd->FspmConfig.Ch1_DramDensity = 0; + mupd->FspmConfig.Ch1_Option = 3; + mupd->FspmConfig.Ch2_RankEnable = 3; + mupd->FspmConfig.Ch2_DeviceWidth = 2; + mupd->FspmConfig.Ch2_DramDensity = 0; + mupd->FspmConfig.Ch2_Option = 3; + mupd->FspmConfig.Ch3_RankEnable = 3; + mupd->FspmConfig.Ch3_DeviceWidth = 2; + mupd->FspmConfig.Ch3_DramDensity = 0; + mupd->FspmConfig.Ch3_Option = 3; + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, swizzling0_rvp2, + sizeof(swizzling0_rvp2)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, swizzling1_rvp2, + sizeof(swizzling1_rvp2)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, swizzling2_rvp2, + sizeof(swizzling2_rvp2)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling3_rvp2, + sizeof(swizzling3_rvp2)); +} + +void mainboard_memory_init_params(struct FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.MemoryDown = 1; + mupd->FspmConfig.DDR3LPageSize = 0; + mupd->FspmConfig.DDR3LASR = 0; + mupd->FspmConfig.ScramblerSupport = 1; + mupd->FspmConfig.ChannelHashMask = 0; + mupd->FspmConfig.SliceHashMask = 0; + mupd->FspmConfig.InterleavedMode = 0; + mupd->FspmConfig.ChannelsSlicesEnable = 0; + mupd->FspmConfig.MinRefRate2xEnable = 0; + mupd->FspmConfig.DualRankSupportEnable = 1; + mupd->FspmConfig.DisableFastBoot = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.LowMemoryMaxValue = 0; + mupd->FspmConfig.HighMemoryMaxValue = 0; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) + rvp1_fill_memory_params(mupd); + else + rvp2_fill_memory_params(mupd); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add SiliconInit API
by Andrey Petrov 07 Mar '16

07 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13799 -gerrit commit 751d4ab19b62bb4c0aa06fa816b1e8f6f4f9c96b Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:17:45 2016 -0800 drivers/intel/fsp2_0: Add SiliconInit API This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/silicon_init.c | 59 +++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c new file mode 100644 index 0000000..66043c8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +struct fsp_header fsps_hdr; + +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); + +static enum fsp_status do_silicon_init(struct fsp_header *hdr) +{ + struct FSPS_UPD upd, *supd; + fsp_silicon_init_fn silicon_init; + enum fsp_status status; + + supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); + + if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) { + printk(BIOS_ERR, "Invalid FSPS signature\n"); + return FSP_INCOMPATIBLE_VERSION; + } + + memcpy(&upd, supd, sizeof(upd)); + + /* Give SoC/mainboard a chance to populate entries */ + platform_fsp_silicon_init_params_cb(&upd); + + silicon_init = (void *) (hdr->image_base + + hdr->silicon_init_entry_offset); + + status = silicon_init(&upd); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + return status; +} + +enum fsp_status fsp_silicon_init(struct range_entry *range) +{ + /* Load FSP-S and save FSP header. We will need it for Notify */ + /* TODO: do not hardcode CBFS file names */ + if (fsp_load_binary(&fsps_hdr, "blobs/fsps.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_silicon_init(&fsps_hdr); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add MemoryInit API
by Andrey Petrov 07 Mar '16

07 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798 -gerrit commit 0568233ec6c9fc274312882a675e0383514a43e7 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:16:33 2016 -0800 drivers/intel/fsp2_0: Add MemoryInit API This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 11 ++-- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 14 ----- src/drivers/intel/fsp2_0/memory_init.c | 73 ++++++++++++++++++++++ 3 files changed, 77 insertions(+), 21 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 0d45df3..c098a5b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -16,6 +16,8 @@ #include <stddef.h> #include <memrange.h> #include <fsp/info_header.h> +#include <soc/fsp/FspmUpd.h> +#include <soc/fsp/FspsUpd.h> enum fsp_status { FSP_SUCCESS = 0x00000000, @@ -39,19 +41,14 @@ enum fsp_notify_phase { }; -/* Opaque structures. These are platform-specific. */ -struct FSP_M_CONFIG; -struct FSP_S_CONFIG; - /* Main FSP stages */ enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r); enum fsp_status fsp_silicon_init(struct range_entry *r); enum fsp_status fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd, - struct FSP_M_CONFIG *mcfg); -void platform_fsp_silicon_init_params_cb(struct FSP_S_CONFIG *silupd); +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); /* * # DOCUMENTATION: diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 0f25496..468101e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -39,20 +39,6 @@ struct fsp_header { uint8_t revision; }; -struct fsp_upd_header { - uint64_t signature; - uint8_t revision; -}; - -struct fsp_m_arch_upd { - uint8_t revision; - uintptr_t nvs_buffer; - uintptr_t stack_base; - uint32_t stack_size; - uint32_t bootloader_tolumsz; - uint32_t boot_mode; -}; - enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); void fsp_print_header_info(const struct fsp_header *hdr); void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c new file mode 100644 index 0000000..8033937 --- /dev/null +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (void *raminit_upd, void **hob_list); + +static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, + struct fsp_header *hdr) +{ + enum fsp_status status; + fsp_memory_init_fn fsp_raminit; + struct FSPM_UPD fspm_upd, *upd; + + post_code(0x34); + + upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + + if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { + printk(BIOS_ERR, "Invalid FSPM signature\n"); + return FSP_INCOMPATIBLE_VERSION; + } + + /* Copy the default values from the UPD area */ + memcpy(&fspm_upd, upd, sizeof(fspm_upd)); + + /* Give SoC and mainboard a chance to update the UPD */ + platform_fsp_memory_init_params_cb(&fspm_upd); + + /* Call FspMemoryInit */ + fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd); + printk(BIOS_SPEW, "\t%p: hob_list ptr\n", hob_list_ptr); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_raminit(&fspm_upd, hob_list_ptr); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + return status; +} + +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range) +{ + struct fsp_header hdr; + + /* TODO: do not hardcode CBFS file names */ + if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_fsp_memory_init(hob_list, &hdr); +}

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Patch set updated for coreboot: x86 chipsets: utilize x86_setup_mtrrs_with_detect()
by Aaron Durbin 07 Mar '16

07 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13936 -gerrit commit 978f8cb20de2b8d276d026a5e615e7b84a23d5e3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:23:47 2016 -0600 x86 chipsets: utilize x86_setup_mtrrs_with_detect() For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 5 +---- src/cpu/intel/haswell/haswell_init.c | 3 +-- src/cpu/intel/model_2065x/model_2065x_init.c | 5 +---- src/cpu/intel/model_206ax/model_206ax_init.c | 5 +---- src/soc/intel/baytrail/cpu.c | 3 +-- src/soc/intel/braswell/cpu.c | 3 +-- src/soc/intel/broadwell/cpu.c | 3 +-- src/soc/intel/skylake/cpu.c | 3 +-- 8 files changed, 8 insertions(+), 22 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index f6e352e..da1ea2b 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -366,7 +366,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -381,9 +380,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5c34a30..b4bff83 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -717,8 +717,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d724842..4005b3d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -358,7 +358,6 @@ static void intel_cores_init(struct device *cpu) static void model_2065x_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -374,9 +373,7 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ()); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index ae2332e4..7575603 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -552,7 +552,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -567,9 +566,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9c69d16..6188689 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,8 +83,7 @@ void baytrail_init_cpus(device_t dev) void *default_smm_area; /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index feb9d9b..71af487 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -89,8 +89,7 @@ void soc_init_cpus(device_t dev) __FILE__, __func__, dev_name(dev)); /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 4a94c1d..5f3fb15 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -573,8 +573,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 327bee9..d154f0e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -343,8 +343,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }

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Patch set updated for coreboot: cpu/x86/mtrr: add helper function to detect variable MTRRs
by Aaron Durbin 07 Mar '16

07 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13935 -gerrit commit b7ad987356a66a27d7c29d1af3de74fdff74f41c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:05:36 2016 -0600 cpu/x86/mtrr: add helper function to detect variable MTRRs The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 13 ++++++++++--- src/include/cpu/x86/mtrr.h | 12 +++++++++--- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index efd0b68..794df99 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -789,8 +789,6 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) addr_space = get_physical_address_space(); if (sol == NULL) { - if (above4gb == 2) - detect_var_mtrrs(); sol = &mtrr_global_solution; sol->mtrr_default_type = calc_var_mtrrs(addr_space, !!above4gb, address_bits); @@ -804,12 +802,21 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) void x86_setup_mtrrs(void) { int address_size; + x86_setup_fixed_mtrrs(); address_size = cpu_phys_address_size(); - printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); + printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", + address_size); + /* Always handle addresses above 4GiB. */ x86_setup_var_mtrrs(address_size, 1); } +void x86_setup_mtrrs_with_detect(void) +{ + detect_var_mtrrs(); + x86_setup_mtrrs(); +} + void x86_mtrr_check(void) { /* Only Pentium Pro and later have MTRR */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..d158735 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,14 +56,20 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. + * + * Note that this function sets up MTRRs for addresses above 4GiB. */ void x86_setup_mtrrs(void); /* + * x86_setup_mtrrs_with_detect() does the same thing as x86_setup_mtrrs(), but + * it always dynamically detects the number of variable MTRRs available. + */ +void x86_setup_mtrrs_with_detect(void); +/* * x86_setup_var_mtrrs() parameters: * address_bits - number of physical address bits supported by cpu - * above4gb - 2 means dynamically detect number of variable MTRRs available. - * non-zero means handle memory ranges above 4GiB. - * 0 means ignore memory ranges above 4GiB + * above4gb - if set setup MTRRs for addresses above 4GiB else ignore + * memory ranges above 4GiB */ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void enable_fixed_mtrr(void);

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Patch set updated for coreboot: x86 chipsets: utilize x86_setup_mtrrs_with_detect()
by Aaron Durbin 07 Mar '16

07 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13936 -gerrit commit c36eb0a13923c9c97cf460faf5189ba7cac39d72 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:23:47 2016 -0600 x86 chipsets: utilize x86_setup_mtrrs_with_detect() For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 5 +---- src/cpu/intel/haswell/haswell_init.c | 3 +-- src/cpu/intel/model_2065x/model_2065x_init.c | 5 +---- src/cpu/intel/model_206ax/model_206ax_init.c | 5 +---- src/soc/intel/baytrail/cpu.c | 3 +-- src/soc/intel/braswell/cpu.c | 3 +-- src/soc/intel/broadwell/cpu.c | 3 +-- src/soc/intel/skylake/cpu.c | 3 +-- 8 files changed, 8 insertions(+), 22 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index f6e352e..da1ea2b 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -366,7 +366,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -381,9 +380,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5c34a30..b4bff83 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -717,8 +717,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d724842..4005b3d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -358,7 +358,6 @@ static void intel_cores_init(struct device *cpu) static void model_2065x_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -374,9 +373,7 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ()); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index ae2332e4..7575603 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -552,7 +552,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -567,9 +566,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9c69d16..6188689 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,8 +83,7 @@ void baytrail_init_cpus(device_t dev) void *default_smm_area; /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index feb9d9b..71af487 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -89,8 +89,7 @@ void soc_init_cpus(device_t dev) __FILE__, __func__, dev_name(dev)); /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 4a94c1d..5f3fb15 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -573,8 +573,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 327bee9..d154f0e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -343,8 +343,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }

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Patch set updated for coreboot: cpu/x86/mtrr: add helper function to detect variable MTRRs
by Aaron Durbin 07 Mar '16

07 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13935 -gerrit commit 0aea9ee1b83aeebad51b7bab68ddd00aa31ca5c1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:05:36 2016 -0600 cpu/x86/mtrr: add helper function to detect variable MTRRs The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 13 ++++++++++--- src/include/cpu/x86/mtrr.h | 14 ++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index efd0b68..794df99 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -789,8 +789,6 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) addr_space = get_physical_address_space(); if (sol == NULL) { - if (above4gb == 2) - detect_var_mtrrs(); sol = &mtrr_global_solution; sol->mtrr_default_type = calc_var_mtrrs(addr_space, !!above4gb, address_bits); @@ -804,12 +802,21 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) void x86_setup_mtrrs(void) { int address_size; + x86_setup_fixed_mtrrs(); address_size = cpu_phys_address_size(); - printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); + printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", + address_size); + /* Always handle addresses above 4GiB. */ x86_setup_var_mtrrs(address_size, 1); } +void x86_setup_mtrrs_with_detect(void) +{ + detect_var_mtrrs(); + x86_setup_mtrrs(); +} + void x86_mtrr_check(void) { /* Only Pentium Pro and later have MTRR */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..4df0bfb 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,16 +56,22 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. + * + * Note that this function sets up MTRRs for addresses above 4GiB. */ void x86_setup_mtrrs(void); /* + * x86_setup_mtrrs_with_detect() does the same thing as x86_setup_mtrrs(), but + * it always dynamically detects the number of variable MTRRs available. + */ +void x86_setup_mtrrs_with_detect(void); +/* * x86_setup_var_mtrrs() parameters: * address_bits - number of physical address bits supported by cpu - * above4gb - 2 means dynamically detect number of variable MTRRs available. - * non-zero means handle memory ranges above 4GiB. - * 0 means ignore memory ranges above 4GiB + * above4gb - if set setup MTRRs for addresses above 4GiB else ignore + * memory ranges above 4GiB */ -void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); +void x86_setup_var_mtrrs(unsigned int address_bits, int above4gb); void enable_fixed_mtrr(void); void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */

1 0

New patch to review for coreboot: x86 chipsets: utilize x86_setup_mtrrs_with_detect()
by Aaron Durbin 07 Mar '16

07 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13936 -gerrit commit 3fc63c4033eab725aa68805c7a8e55f5fa20cc6b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:23:47 2016 -0600 x86 chipsets: utilize x86_setup_mtrrs_with_detect() For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 5 +---- src/cpu/intel/haswell/haswell_init.c | 3 +-- src/cpu/intel/model_2065x/model_2065x_init.c | 5 +---- src/cpu/intel/model_206ax/model_206ax_init.c | 5 +---- src/soc/intel/baytrail/cpu.c | 3 +-- src/soc/intel/braswell/cpu.c | 3 +-- src/soc/intel/broadwell/cpu.c | 3 +-- src/soc/intel/skylake/cpu.c | 3 +-- 8 files changed, 8 insertions(+), 22 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index f6e352e..da1ea2b 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -366,7 +366,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -381,9 +380,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5c34a30..b4bff83 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -717,8 +717,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d724842..4005b3d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -358,7 +358,6 @@ static void intel_cores_init(struct device *cpu) static void model_2065x_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -374,9 +373,7 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ()); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index ae2332e4..7575603 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -552,7 +552,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -567,9 +566,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* Setup Page Attribute Tables (PAT) */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9c69d16..6188689 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,8 +83,7 @@ void baytrail_init_cpus(device_t dev) void *default_smm_area; /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index feb9d9b..71af487 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -89,8 +89,7 @@ void soc_init_cpus(device_t dev) __FILE__, __func__, dev_name(dev)); /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 4a94c1d..5f3fb15 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -573,8 +573,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); initialize_vr_config(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 327bee9..d154f0e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -343,8 +343,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }

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New patch to review for coreboot: cpu/x86/mtrr: add helper function to detect variable MTRRs
by Aaron Durbin 07 Mar '16

07 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13935 -gerrit commit f07430055284cd9c3d31163725f70a2edefbb56d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 7 16:05:36 2016 -0600 cpu/x86/mtrr: add helper function to detect variable MTRRs The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 22 +++++++++++++++++++--- src/include/cpu/x86/mtrr.h | 7 +++++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index efd0b68..84e005a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -801,13 +801,29 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) commit_var_mtrrs(sol); } -void x86_setup_mtrrs(void) +static void __x86_setup_mtrrs(int above4gb) { int address_size; + x86_setup_fixed_mtrrs(); address_size = cpu_phys_address_size(); - printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); - x86_setup_var_mtrrs(address_size, 1); + printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", + address_size); + /* Always handle addresses above 4GiB. */ + x86_setup_var_mtrrs(address_size, above4gb); +} + +void x86_setup_mtrrs(void) +{ + /* Handle addresses above 4GiB, but don't detect number of variable + * MTRRs. */ + __x86_setup_mtrrs(1); +} + +void x86_setup_mtrrs_with_detect(void) +{ + /* Handle addresses above 4GiB, but detect number of variable MTRRs. */ + __x86_setup_mtrrs(2); } void x86_mtrr_check(void) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..5a92ea3 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,9 +56,16 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. + * + * Note that this function sets up MTRRs for addresses above 4GiB. */ void x86_setup_mtrrs(void); /* + * x86_setup_mtrrs_with_detect() does the same thing as x86_setup_mtrrs(), but + * it always dynamically detects the number of variable MTRRs available. + */ +void x86_setup_mtrrs_with_detect(void); +/* * x86_setup_var_mtrrs() parameters: * address_bits - number of physical address bits supported by cpu * above4gb - 2 means dynamically detect number of variable MTRRs available.

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New patch to review for coreboot: nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
by Timothy Pearson 07 Mar '16

07 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13932 -gerrit commit 64eb9380874f7b16e7035f34c092e44c834c7c67 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 7 13:29:24 2016 -0600 nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15 Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 19a7acb..40f5ce1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, Errors = 0; dual_rank = 0; - Receiver = mct_InitReceiver_D(pDCTstat, dct); - if (receiver_start > Receiver) - Receiver = receiver_start; /* There are four receiver pairs, loosely associated with chipselects. * This is essentially looping over each rank within each DIMM. */ - for (; Receiver < receiver_end; Receiver++) { + for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) { dimm = (Receiver >> 1); if ((Receiver & 0x1) == 0) { /* Even rank of DIMM */

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coreboot-gerrit March 2016