Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13628
-gerrit
commit da6a69ca48e090c05ab92f55c25679d34da06493
Author: david <david_wu(a)quantatw.com>
Date: Tue Dec 29 15:02:04 2015 +0800
intel/skylake: Add gpio macro for unused GPIO pins
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.
BUG=none
BRANCH=none
TEST=Build and boot lars
Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319964
Original-Commit-Ready: David Wu <david_wu(a)quantatw.com>
Original-Tested-by: David Wu <david_wu(a)quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
src/soc/intel/skylake/include/soc/gpio.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 7dec874..f2246e9 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_PAD_CFG(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO))
+/* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
+ GPIO TX/RX will be disabled. */
+#define PAD_CFG_NC(pad_) \
+ _PAD_CFG(pad_, NONE, \
+ _DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES))
+
/* General purpose output with termination. */
#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
_PAD_CFG(pad_, term_, \
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13627
-gerrit
commit 41e23bd3791845ab4d2ab6551c168cff356773c8
Author: david <david_wu(a)quantatw.com>
Date: Fri Jan 8 20:49:48 2016 +0800
google/lars: Set I2C[4] port voltage to 1.8v
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.
TEST=Built & booted lars board. Verified that I2C
port 4 is operating at 1.8V level
Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321000
Original-Commit-Ready: David Wu <david_wu(a)quantatw.com>
Original-Tested-by: David Wu <david_wu(a)quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/lars/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index bc39f3e..cf3649a 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -146,6 +146,7 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
+ register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13626
-gerrit
commit 205d8159d1606fb0fbb683dc2c49cf1cad743eec
Author: Alexandru M Stan <amstan(a)chromium.org>
Date: Wed Feb 3 17:28:38 2016 -0800
google/veyron_rialto: Remove developer mode switch
The developer mode gpio switch on rialto is always hardcoded (through a
resistor) as developer mode. We need to ignore it to allow transitions to
verified mode with the virtual developer mode stuff.
TEST=We can now exit dev mode on rialto
Change-Id: I94a949f0973132de5fd008224af79cf612151193
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e78bb8f81eaa9c082e47ad818b64843c2565d00b
Original-Change-Id: If11d752d58a5f26fc270ef01b529dad18b4cce46
Original-Signed-off-by: Alexandru M Stan <amstan(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325861
Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org>
Original-Tested-by: Alexandru Stan <amstan(a)chromium.org>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/mainboard/google/veyron_rialto/chromeos.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c
index 3b4dc33..9099584 100644
--- a/src/mainboard/google/veyron_rialto/chromeos.c
+++ b/src/mainboard/google/veyron_rialto/chromeos.c
@@ -25,7 +25,6 @@
#define GPIO_POWER GPIO(0, A, 5)
#define GPIO_RECOVERY_SERVO GPIO(0, B, 1)
#define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1)
-#define GPIO_DEVELOPER_SWITCH GPIO(7, B, 2)
void setup_chromeos_gpios(void)
@@ -34,7 +33,6 @@ void setup_chromeos_gpios(void)
gpio_input(GPIO_POWER);
gpio_input_pullup(GPIO_RECOVERY_SERVO);
gpio_input_pullup(GPIO_RECOVERY_PUSHKEY);
- gpio_input(GPIO_DEVELOPER_SWITCH); // board has pull up/down resistor.
}
void fill_lb_gpios(struct lb_gpios *gpios)
@@ -69,7 +67,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
count++;
/* Developer: GPIO active high */
- gpios->gpios[count].port = GPIO_DEVELOPER_SWITCH.raw;
+ gpios->gpios[count].port = -1;
gpios->gpios[count].polarity = ACTIVE_HIGH;
gpios->gpios[count].value = get_developer_mode_switch();
strncpy((char *)gpios->gpios[count].name, "developer",
@@ -92,8 +90,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void)
{
- // GPIO_DEVELOPER_SWITCH is active high.
- return gpio_get(GPIO_DEVELOPER_SWITCH);
+ return 0;
}
int get_recovery_mode_switch(void)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13604
-gerrit
commit f4be3b5767ff249ca8055616831e8c8d8f8107d9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Feb 1 17:37:16 2016 -0600
google/chromeos/vboot2: defer clearing rec mode switch
Certain platforms query the recovery mode switch more than just within
vboot during the boot flow. Therefore, it's important that the first call to
get_recovery_mode_switch() is consistent through memory training because
certain platforms use the recovery mode switch to take different action
for memory training. Therefore, defer the clearing of the rec mode
switch to a place when it's known that memory is up and online.
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Three finger salute is honored on chell by retraining memory.
Change-Id: I26ea51de7ffa2fe75b9ef1401fe92f9aec2b4567
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6b0de9369242e50c7ff3b164cf1ced0642c7b087
Original-Change-Id: Ia7709c7346d1222e314bf3ac7e4335a63e9a5144
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325120
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 11 +++++++++++
src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 1 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index dbcc4da..c89e9a0 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -152,6 +152,17 @@ void vboot_fill_handoff(void)
/* needed until we finish transtion to vboot2 for kernel verification */
fill_vboot_handoff(vh, sd);
+
+ /*
+ * The recovery mode switch is cleared (typically backed by EC) here
+ * to allow multiple queries to get_recovery_mode_switch() and have
+ * them return consistent results during the verified boot path as well
+ * as dram initialization. x86 systems ignore the saved dram settings
+ * in the recovery path in order to start from a clean slate. Therefore
+ * clear the state here since this function is called when memory
+ * is known to be up.
+ */
+ clear_recovery_mode_switch();
}
/*
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
index fec368c..a4829c0 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c
@@ -316,7 +316,6 @@ void verstage_main(void)
ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
if (get_recovery_mode_switch()) {
- clear_recovery_mode_switch();
ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY))
ctx.flags |= VB2_DISABLE_DEVELOPER_MODE;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13600
-gerrit
commit d4016c202afe759aac9bf377527e1116946ff330
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 26 16:30:36 2016 -0800
chromeos: Add option to backup VBNV CMOS into flash
This adds a new kconfig option that will backup the VBNV data
from CMOS to flash, and restore it if the CMOS data is invalid
during boot.
This allows special flags to not get lost when power is lost,
RTC reset is triggered, or CMOS is corrupted.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell:
1-boot and run "enable_dev_usb_boot"
2-reboot and check that it is enabled with crossystem
3-run "mosys nvram clear"
4-reboot and check that it is still enabled
Change-Id: I38103d100117da34471734a6dd31eb7058735c12
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 8a356e616c6885d5ae3b776691929675d48a28f9
Original-Change-Id: I06e7ddff7b272e579c704914a0cf8cc14d6994e8
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324122
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/Kconfig | 8 ++++++++
src/vendorcode/google/chromeos/Makefile.inc | 5 +++++
src/vendorcode/google/chromeos/vbnv_cmos.c | 31 +++++++++++++++++++++++++++++
3 files changed, 44 insertions(+)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 79d6918..4a889b1 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -50,6 +50,14 @@ config CHROMEOS_VBNV_CMOS
help
VBNV is stored in CMOS
+config CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
+ bool "Backup Vboot non-volatile storage from CMOS to flash."
+ default n
+ depends on CHROMEOS_VBNV_CMOS
+ help
+ Vboot non-volatile storage data will be backed up from CMOS to flash
+ and restored from flash if the CMOS is invalid due to power loss.
+
config CHROMEOS_VBNV_EC
bool "Vboot non-volatile storage in EC."
default n
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index ee8b50d..7d62b5b 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -28,6 +28,11 @@ verstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c
romstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c
ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c
+bootblock-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+verstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+romstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+
bootblock-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c
verstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c
romstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c
diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c
index e0d7ba1..22acefa 100644
--- a/src/vendorcode/google/chromeos/vbnv_cmos.c
+++ b/src/vendorcode/google/chromeos/vbnv_cmos.c
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <bootstate.h>
+#include <console/console.h>
#include <types.h>
#include <pc80/mc146818rtc.h>
#include "vbnv.h"
@@ -24,6 +26,21 @@ void read_vbnv_cmos(uint8_t *vbnv_copy)
for (i = 0; i < VBNV_BLOCK_SIZE; i++)
vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i);
+
+ if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH)) {
+ if (verify_vbnv(vbnv_copy))
+ return;
+
+ printk(BIOS_INFO, "VBNV: CMOS invalid, restoring from flash\n");
+ read_vbnv_flash(vbnv_copy);
+
+ if (verify_vbnv(vbnv_copy)) {
+ save_vbnv_cmos(vbnv_copy);
+ printk(BIOS_INFO, "VBNV: Flash backup restored\n");
+ } else {
+ printk(BIOS_INFO, "VBNV: Restore from flash failed\n");
+ }
+ }
}
void save_vbnv_cmos(const uint8_t *vbnv_copy)
@@ -33,3 +50,17 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy)
for (i = 0; i < VBNV_BLOCK_SIZE; i++)
cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i);
}
+
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH)
+static void backup_vbnv_cmos(void *unused)
+{
+ uint8_t vbnv_cmos[VBNV_BLOCK_SIZE];
+
+ /* Read current VBNV from CMOS. */
+ read_vbnv_cmos(vbnv_cmos);
+
+ /* Save to flash, will only be saved if different. */
+ save_vbnv_flash(vbnv_cmos);
+}
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, backup_vbnv_cmos, NULL);
+#endif
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13602
-gerrit
commit 9e00779908430bd58b7736bcb1cd62b2de06bb59
Author: Fang, Yang A <yang.a.fang(a)intel.com>
Date: Thu Jan 28 16:52:33 2016 -0800
nhlt: add api to override oem_id and oem_table_id of acpi_header_t
This patch added nhlt_soc_serialize_oem_overrides and
nhlt_serilalize_oem_overrides to be able to override oem_id and
oem_table_id.board file can pass specific string by calling
nhlt_soc_serialize_oem_overrides
kernel use these two fields to construct a topology binary name
if the designate file is not found a default dfw_sst.bin will be used
it is optional.
BUG=chrome-os-partner:49570
BRANCH=glados
TEST=Build & Booted kunimitsu board. Verified that kernel
can read new strings.
Change-Id: I00b64fb8bb63de601d3116e0b8941057c1efa230
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 374ce08b2d8a2f4e5dd7f51eacb505dbb77fd171
Original-Change-Id: I03623c8ac81efb5a5ea3ec9c6cd604d2e9294022
Original-Signed-off-by: Fang, Yang A <yang.a.fang(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/322860
Original-Commit-Ready: Yang Fang <yang.a.fang(a)intel.com>
Original-Tested-by: Yang Fang <yang.a.fang(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/nhlt.h | 17 +++++++++++++++++
src/lib/nhlt.c | 22 ++++++++++++++++++++--
src/soc/intel/skylake/nhlt/nhlt.c | 9 ++++++++-
3 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/src/include/nhlt.h b/src/include/nhlt.h
index ca16693..f0b3b6f 100644
--- a/src/include/nhlt.h
+++ b/src/include/nhlt.h
@@ -125,12 +125,29 @@ void nhlt_next_instance(struct nhlt *nhlt, int link_type);
uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr);
/*
+ * Serialize NHLT object to ACPI table. Take in the beginning address of where
+ * the table will reside oem_id and oem_table_id and return the address of the
+ * next ACPI table. On error 0 will be returned. The NHLT object is no longer
+ * valid after thisfunction is called.
+ */
+uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, uintptr_t acpi_addr,
+ const char *oem_id, const char *oem_table_id);
+
+/*
* While very similar to nhlt_serialize() the SoC specific function allows
* the chipset to perform any needed accounting work such as updating ACPI
* field references for the serialized structure.
*/
uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr);
+/*
+ * While very similar to nhlt_serialize_oem_overrides() the SoC specific
+ * function allows the chipset to perform any needed accounting work such
+ * as updating ACPI field references for the serialized structure.
+ */
+uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt,
+ uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id);
+
/* Link and device types. */
enum {
NHLT_LINK_HDA,
diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c
index 4fa4a0c..11a397c 100644
--- a/src/lib/nhlt.c
+++ b/src/lib/nhlt.c
@@ -389,9 +389,17 @@ static void nhlt_serialize_endpoints(struct nhlt *nhlt, struct cursor *cur)
uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
{
+ return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL);
+}
+
+uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt,
+ uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id)
+{
struct cursor cur;
acpi_header_t *header;
size_t sz;
+ size_t oem_id_len;
+ size_t oem_table_id_len;
printk(BIOS_DEBUG, "ACPI: * NHLT\n");
@@ -403,8 +411,18 @@ uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
memcpy(header->signature, "NHLT", 4);
write_le32(&header->length, sz);
write_le8(&header->revision, 5);
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+
+ if (oem_id == NULL)
+ oem_id = OEM_ID;
+
+ if (oem_table_id == NULL)
+ oem_table_id = ACPI_TABLE_CREATOR;
+
+ oem_id_len = MIN(strlen(oem_id), 6);
+ oem_table_id_len = MIN(strlen(oem_table_id), 8);
+
+ memcpy(header->oem_id, oem_id, oem_id_len);
+ memcpy(header->oem_table_id, oem_table_id, oem_table_id_len);
memcpy(header->asl_compiler_id, ASLC, 4);
cur.buf = (void *)(acpi_addr + sizeof(acpi_header_t));
diff --git a/src/soc/intel/skylake/nhlt/nhlt.c b/src/soc/intel/skylake/nhlt/nhlt.c
index 56e7d39..6ef906a 100644
--- a/src/soc/intel/skylake/nhlt/nhlt.c
+++ b/src/soc/intel/skylake/nhlt/nhlt.c
@@ -87,6 +87,12 @@ struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf,
uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
{
+ return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL);
+}
+
+uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt,
+ uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id)
+{
global_nvs_t *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
@@ -98,5 +104,6 @@ uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
gnvs->nhla = (uintptr_t)acpi_addr;
gnvs->nhll = nhlt_current_size(nhlt);
- return nhlt_serialize(nhlt, acpi_addr);
+ return nhlt_serialize_oem_overrides(nhlt, acpi_addr,
+ oem_id, oem_table_id);
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13599
-gerrit
commit 467201b87c26f93334a93e5ff0a2b33e06cb7c75
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 26 16:22:53 2016 -0800
chromeos: Make vbnv_flash driver safe for CAR usage
This modifies the vbnv_flash driver to make it safe for use
in cache-as-ram by handling the global variables safely.
To make this cleaner all of the variables were moved into
one structure and referenced from there.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=build and boot on chell using following patches to
test backup and restore of vbnv_cmos into flash
Change-Id: I3a17fa51cfd754455502ac2e5f181dae35967f2a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 48876561fa4fb61e1ec8f92596c5610d97135201
Original-Change-Id: Id9fda8467edcc55e5ed760ddab197ab97d1f3d25
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324121
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/vbnv_flash.c | 105 ++++++++++++++++------------
1 file changed, 62 insertions(+), 43 deletions(-)
diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c
index ea5d9f3..88f39b0 100644
--- a/src/vendorcode/google/chromeos/vbnv_flash.c
+++ b/src/vendorcode/google/chromeos/vbnv_flash.c
@@ -11,10 +11,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * TODO: Make this CAR-friendly in case we use it on x86 some day.
*/
+#include <arch/early_variables.h>
#include <assert.h>
#include <console/console.h>
#include <spi_flash.h>
@@ -27,20 +26,26 @@
#define BLOB_SIZE VB2_NVDATA_SIZE
-/* FMAP descriptor of the NVRAM area */
-static struct region_device nvram_region;
+struct vbnv_flash_ctx {
+ /* VBNV flash is initialized */
+ int initialized;
+
+ /* Offset of the current nvdata in SPI flash */
+ int blob_offset;
-/* offset of the current nvdata in SPI flash */
-static int blob_offset = -1;
+ /* Offset of the topmost nvdata blob in SPI flash */
+ int top_offset;
-/* Offset of the topmost nvdata blob in SPI flash */
-static int top_offset;
+ /* SPI flash handler used when saving data */
+ struct spi_flash *flash;
-/* cache of the current nvdata */
-static uint8_t cache[BLOB_SIZE];
+ /* FMAP descriptor of the NVRAM area */
+ struct region_device region;
-/* spi_flash struct used when saving data */
-static struct spi_flash *spi_flash = NULL;
+ /* Cache of the current nvdata */
+ uint8_t cache[BLOB_SIZE];
+};
+static struct vbnv_flash_ctx vbnv_flash CAR_GLOBAL;
/*
* This code assumes that flash is erased to 1-bits, and write operations can
@@ -57,20 +62,16 @@ static inline int can_overwrite(uint8_t current, uint8_t new)
return (current & new) == new;
}
-static inline int is_initialized(void)
-{
- return blob_offset >= 0;
-}
-
static int init_vbnv(void)
{
+ struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
uint8_t buf[BLOB_SIZE];
uint8_t empty_blob[BLOB_SIZE];
int offset;
int i;
- if (vboot_named_region_device("RW_NVRAM", &nvram_region) ||
- region_device_sz(&nvram_region) < BLOB_SIZE) {
+ if (vboot_named_region_device("RW_NVRAM", &ctx->region) ||
+ region_device_sz(&ctx->region) < BLOB_SIZE) {
printk(BIOS_ERR, "%s: failed to locate NVRAM\n", __func__);
return 1;
}
@@ -80,7 +81,7 @@ static int init_vbnv(void)
empty_blob[i] = erase_value();
offset = 0;
- top_offset = region_device_sz(&nvram_region) - BLOB_SIZE;
+ ctx->top_offset = region_device_sz(&ctx->region) - BLOB_SIZE;
/*
* after the loop, offset is supposed to point the blob right before
@@ -88,8 +89,8 @@ static int init_vbnv(void)
* empty blob, or the base of the region if the nvram has never been
* used.
*/
- for (i = 0; i <= top_offset; i += BLOB_SIZE) {
- if (rdev_readat(&nvram_region, buf, i, BLOB_SIZE) < 0) {
+ for (i = 0; i <= ctx->top_offset; i += BLOB_SIZE) {
+ if (rdev_readat(&ctx->region, buf, i, BLOB_SIZE) < 0) {
printk(BIOS_ERR, "failed to read nvdata\n");
return 1;
}
@@ -99,12 +100,13 @@ static int init_vbnv(void)
}
/* reread the nvdata and write it to the cache */
- if (rdev_readat(&nvram_region, cache, offset, BLOB_SIZE) < 0) {
+ if (rdev_readat(&ctx->region, ctx->cache, offset, BLOB_SIZE) < 0) {
printk(BIOS_ERR, "failed to read nvdata\n");
return 1;
}
- blob_offset = offset;
+ ctx->blob_offset = offset;
+ ctx->initialized = 1;
return 0;
}
@@ -122,15 +124,19 @@ static void vbnv_is_erasable(void)
*
* TODO: Check by calling can_erase implemented by each spi flash driver
*/
- assert(!(region_device_offset(&nvram_region) % spi_flash->sector_size));
- assert(!(region_device_sz(&nvram_region) % spi_flash->sector_size));
+ struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
+
+ assert(!(region_device_offset(&ctx->region) % ctx->flash->sector_size));
+ assert(!(region_device_sz(&ctx->region) % ctx->flash->sector_size));
}
static int vbnv_flash_probe(void)
{
- if (!spi_flash) {
- spi_flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0);
- if (!spi_flash) {
+ struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
+
+ if (!ctx->flash) {
+ ctx->flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0);
+ if (!ctx->flash) {
printk(BIOS_ERR, "failed to probe spi flash\n");
return 1;
}
@@ -140,16 +146,25 @@ static int vbnv_flash_probe(void)
*/
vbnv_is_erasable();
}
+
+ /*
+ * Handle the case where spi_flash_probe returns a CAR_GLOBAL
+ * in early execution on x86 but then later is moved to RAM.
+ */
+ ctx->flash = car_get_var_ptr(ctx->flash);
+
return 0;
}
static int erase_nvram(void)
{
+ struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
+
if (vbnv_flash_probe())
return 1;
- if (spi_flash->erase(spi_flash, region_device_offset(&nvram_region),
- region_device_sz(&nvram_region))) {
+ if (ctx->flash->erase(ctx->flash, region_device_offset(&ctx->region),
+ region_device_sz(&ctx->region))) {
printk(BIOS_ERR, "failed to erase nvram\n");
return 1;
}
@@ -160,33 +175,37 @@ static int erase_nvram(void)
void read_vbnv_flash(uint8_t *vbnv_copy)
{
- if (!is_initialized())
+ struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
+
+ if (!ctx->initialized)
if (init_vbnv())
return; /* error */
- memcpy(vbnv_copy, cache, BLOB_SIZE);
+
+ memcpy(vbnv_copy, ctx->cache, BLOB_SIZE);
}
void save_vbnv_flash(const uint8_t *vbnv_copy)
{
+ struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
int new_offset;
int i;
- if (!is_initialized())
+ if (!ctx->initialized)
if (init_vbnv())
return; /* error */
/* Bail out if there have been no changes. */
- if (!memcmp(vbnv_copy, cache, BLOB_SIZE))
+ if (!memcmp(vbnv_copy, ctx->cache, BLOB_SIZE))
return;
- new_offset = blob_offset;
+ new_offset = ctx->blob_offset;
/* See if we can overwrite the current blob with the new one */
for (i = 0; i < BLOB_SIZE; i++) {
- if (!can_overwrite(cache[i], vbnv_copy[i])) {
+ if (!can_overwrite(ctx->cache[i], vbnv_copy[i])) {
/* unable to overwrite. need to use the next blob */
new_offset += BLOB_SIZE;
- if (new_offset > top_offset) {
+ if (new_offset > ctx->top_offset) {
if (erase_nvram())
return; /* error */
new_offset = 0;
@@ -196,12 +215,12 @@ void save_vbnv_flash(const uint8_t *vbnv_copy)
}
if (!vbnv_flash_probe() &&
- !spi_flash->write(spi_flash,
- region_device_offset(&nvram_region) + new_offset,
- BLOB_SIZE, vbnv_copy)) {
+ !ctx->flash->write(ctx->flash,
+ region_device_offset(&ctx->region) + new_offset,
+ BLOB_SIZE, vbnv_copy)) {
/* write was successful. safely move pointer forward */
- blob_offset = new_offset;
- memcpy(cache, vbnv_copy, BLOB_SIZE);
+ ctx->blob_offset = new_offset;
+ memcpy(ctx->cache, vbnv_copy, BLOB_SIZE);
} else {
printk(BIOS_ERR, "failed to save nvdata\n");
}