Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445
-gerrit
commit ad26d15857dc91f32377f51e19d0ff9b6ebd6aba
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 14:37:13 2016 -0800
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 42 +++++++++++++++++++++++++++
src/soc/intel/quark/Makefile.inc | 4 +++
src/soc/intel/quark/include/soc/iomap.h | 27 +++++++++++++++++
src/soc/intel/quark/include/soc/pci_devs.h | 26 +++++++++++++++++
src/soc/intel/quark/include/soc/romstage.h | 29 ++++++++++++++++++
src/soc/intel/quark/romstage/Makefile.inc | 3 ++
src/soc/intel/quark/romstage/cache_as_ram.inc | 41 +++++++++++++++++++++++++-
src/soc/intel/quark/romstage/romstage.c | 27 +++++++++++++++++
src/soc/intel/quark/romstage/uart.c | 42 +++++++++++++++++++++++++++
src/soc/intel/quark/tsc_freq.c | 36 +++++++++++++++++++++++
src/soc/intel/quark/uart.c | 40 +++++++++++++++++++++++++
11 files changed, 316 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 802f972..d99cd54 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -26,9 +26,38 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select SOC_INTEL_COMMON
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
select USE_MARCH_586
#####
+# Debug serial output
+# The following options configure the debug serial port
+#####
+
+config ENABLE_BUILTIN_HSUART1
+ bool "Enable built-in HSUART1"
+ default y
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
+ help
+ The Quark SoC has two HSUART. Choose this option to configure the pads
+ and enable HSUART1, which can be used for the debug console.
+
+config TTYS0_BASE
+ hex "HSUART1 Base Address"
+ depends on ENABLE_BUILTIN_HSUART1
+ default 0xA0019000
+ help
+ Memory mapped MMIO of HSUART1.
+
+config TTYS0_LCS
+ int
+ depends on ENABLE_BUILTIN_HSUART1
+ default 3
+
+#####
# Debug support
# The following options provide debug support for the Quark coreboot
# code. The SD LED is used as a binary marker to determine if a
@@ -65,6 +94,19 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT
Indicate that TempRamInit was successful.
#####
+# ESRAM layout
+# Specify the portion of the ESRAM for coreboot to use as its data area.
+#####
+
+config DCACHE_RAM_BASE
+ hex
+ default 0x80070000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x00008000
+
+#####
# Flash layout
# Specify the size of the coreboot file system in the read-only
# (recovery) portion of the flash part.
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 880f1d4..915360a 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -19,8 +19,12 @@ subdirs-y += romstage
subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c
+romstage-y += tsc_freq.c
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += memmap.c
+ramstage-y += tsc_freq.c
+ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
new file mode 100644
index 0000000..f033dcb
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/*
+ * Memory Mapped IO base addresses.
+ */
+
+/* UART MMIO */
+#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
new file mode 100644
index 0000000..0543a05
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_PCI_DEVS_H_
+#define _QUARK_PCI_DEVS_H_
+
+/* IO Fabric 1 */
+#define SIO1_DEV 0x14
+# define HSUART1_DEV SIO1_DEV
+# define HSUART1_FUNC 5
+
+#endif /* _QUARK_PCI_DEVS_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
new file mode 100644
index 0000000..a35f4a6
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_ROMSTAGE_H_
+#define _QUARK_ROMSTAGE_H_
+
+#if !defined(__PRE_RAM__)
+#error "Don't include romstage.h from a ramstage compilation unit!"
+#endif
+
+#include <fsp/util.h>
+
+int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
+
+#endif /* _QUARK_ROMSTAGE_H_ */
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index cb17d3d..6ade32d 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -15,3 +15,6 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+
+romstage-y += romstage.c
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
index d323f03..4fc60e2 100644
--- a/src/soc/intel/quark/romstage/cache_as_ram.inc
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -115,7 +115,46 @@ CAR_init_done:
#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
/* Set up bootloader stack */
- clrl %eax
+ movl %edx, %esp
+
+ /*
+ * eax: 0
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ * esp: Top of stack in temp RAM
+ */
+
+ /* Create cache_as_ram_params on stack */
+ pushl %edx /* bootloader CAR end */
+ pushl %ecx /* bootloader CAR begin */
+ pushl %ebp /* FSP_INFO_HEADER */
+ pushl $0 /* BIST - esram_init.inc catches non-zero BIST values */
+ /* TODO: Locate 64-bits of storage for initial TSC value */
+ pushl $0 /* tsc[63:32] */
+ pushl $0 /* tsc[31:0] */
+ pushl %esp /* pointer to cache_as_ram_params */
+
+ /* Save FSP_INFO_HEADER location in ebx */
+ mov %ebp, %ebx
+
+ /* Coreboot assumes stack/heap region will be zero */
+ cld
+ movl %ecx, %edi
+ neg %ecx
+ /* Only clear up to current stack value. */
+ add %esp, %ecx
+ shrl $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+before_romstage:
+ post_code(0x2A)
+
+ /* Call cache_as_ram_main(struct cache_as_ram_params *) */
+ call cache_as_ram_main
+ movb $0x69, %ah
jmp .Lhlt
halt1:
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
new file mode 100644
index 0000000..0951b81
--- /dev/null
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/car.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+void car_soc_pre_console_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
+ set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
+ UART_BASE_ADDRESS);
+}
diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c
new file mode 100644
index 0000000..2d53a48
--- /dev/null
+++ b/src/soc/intel/quark/romstage/uart.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <rules.h>
+#include <soc/romstage.h>
+
+int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base)
+{
+ uint16_t reg16;
+
+ /* HSUART controller #1 (B0:D20:F5). */
+ device_t uart_dev = PCI_DEV(bus, dev, func);
+
+ /* Decode BAR0(offset 0x10). */
+ pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);
+
+ /* Enable MEMBASE at CMD(offset 0x04). */
+ reg16 = pci_read_config16(uart_dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(uart_dev, PCI_COMMAND, reg16);
+
+ return 0;
+}
diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c
new file mode 100644
index 0000000..a770c81
--- /dev/null
+++ b/src/soc/intel/quark/tsc_freq.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+
+static unsigned long bus_freq_khz(void)
+{
+ /* cpu freq = 400 MHz */
+ return 400 * 1000;
+}
+
+unsigned long tsc_freq_mhz(void)
+{
+ /* assume ratio=1 */
+ unsigned bclk_khz = bus_freq_khz();
+
+ if (!bclk_khz)
+ return 0;
+
+ return (bclk_khz * 1) / 1000;
+}
diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c
new file mode 100644
index 0000000..2b5b398
--- /dev/null
+++ b/src/soc/intel/quark/uart.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <rules.h>
+#include <soc/pci_devs.h>
+
+unsigned int uart_platform_refclk(void)
+{
+ return 44236800;
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ /* HSUART controller #1 (B0:D20:F5). */
+ device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC);
+
+ /* UART base address at BAR0(offset 0x10). */
+ return (unsigned int) (pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0) & ~0xfff);
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447
-gerrit
commit c14cd8140598e7fd9ba85a801b9f3153e5d5fe98
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 14:48:53 2016 -0800
soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_HOBS"
* Add "select DISPLAY_UPD_DATA"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* MemoryInit returns 0 (success) and
* The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/romstage/romstage.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 0951b81..19d0642 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -14,9 +14,12 @@
* GNU General Public License for more details.
*/
+#include <arch/early_variables.h>
+#include <console/console.h>
#include <fsp/car.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
+#include <soc/pm.h>
#include <soc/romstage.h>
void car_soc_pre_console_init(void)
@@ -25,3 +28,14 @@ void car_soc_pre_console_init(void)
set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
UART_BASE_ADDRESS);
}
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+struct chipset_power_state *fill_power_state(void)
+{
+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+ ps->prev_sleep_state = 0;
+ printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
+ return ps;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443
-gerrit
commit b345cc5807ac2634c886e8a4402b234632725ace
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 10:42:14 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Test 1 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Test 2 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Remove "select ENABLE_DEBUG_LED_FINDFSP"
* Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 118 +++++++++++++++
src/soc/intel/quark/Makefile.inc | 12 ++
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/cache_as_ram.inc | 206 ++++++++++++++++++++++++++
src/soc/intel/quark/romstage/esram_init.inc | 21 +++
5 files changed, 358 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 1bfab49..802f972 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -29,6 +29,42 @@ config CPU_SPECIFIC_OPTIONS
select USE_MARCH_586
#####
+# Debug support
+# The following options provide debug support for the Quark coreboot
+# code. The SD LED is used as a binary marker to determine if a
+# specific point in the execution flow has been reached.
+#####
+
+config ENABLE_DEBUG_LED
+ bool
+ default n
+ help
+ Enable the use of the SD LED for early debugging before serial output
+ is available. Setting this LED indicates that control has reached the
+ desired check point.
+
+config ENABLE_DEBUG_LED_ESRAM
+ bool "SD LED indicates ESRAM initialized"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+ bool "SD LED indicates fsp.bin file was found"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+ bool "SD LED indicates TempRamInit was successful"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that TempRamInit was successful.
+
+#####
# Flash layout
# Specify the size of the coreboot file system in the read-only
# (recovery) portion of the flash part.
@@ -45,6 +81,88 @@ config CBFS_SIZE
- Intel Trusted Execution Engine firmware
#####
+# FSP binary
+# The following options control the FSP binary file placement in
+# the flash image and ESRAM. This file is required by the Quark
+# SoC code to boot coreboot and its payload.
+#####
+
+config ADD_FSP_RAW_BIN
+ bool "Add the Intel FSP binary to the flash image without relocation"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ default "3rdparty/blobs/soc/intel/quark/fsp.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_RAW_BIN
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+ string "8 byte platform string identifying the FSP platform"
+ default "QUK-FSP0"
+ depends on PLATFORM_USES_FSP1_1
+ help
+ 8 ASCII character byte signature string that will help match the FSP
+ binary to a supported hardware configuration.
+
+config FSP_LOC
+ hex
+ default 0xfff80000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config FSP_ESRAM_LOC
+ hex
+ default 0x80000000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in ESRAM where a copy of the FSP binary is placed.
+
+#####
+# FSP PDAT binary
+# The following options control the FSP platform data binary
+# file placement in the flash image.
+#####
+
+config ADD_FSP_PDAT_FILE
+ bool "Should the PDAT binary be added to the flash image?"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The PDAT file is required for the FSP 1.1 binary
+
+config FSP_PDAT_FILE
+ string
+ default "3rdparty/blobs/soc/intel/quark/pdat.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The path and filename of the Intel Galileo platform-data-patch (PDAT)
+ binary. This binary file is generated by the platform-data-patch.py
+ script released with the Quark BSP and contains the Ethernet address.
+
+config FSP_PDAT_LOC
+ hex
+ default 0xfff10000
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The location in CBFS that the PDAT is located. It must match the
+ PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
+
+#####
# RMU binary
# The following options control the Quark chipset microcode file
# placement in the flash image. This file is required to bring
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 8e24d9b..880f1d4 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -27,6 +27,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include
# Chipset microcode path
CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
+# Add the FSP binary to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := raw
+
+# Add the platform data file to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin
+pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE))
+pdat.bin-position := $(CONFIG_FSP_PDAT_LOC)
+pdat.bin-type := raw
+
# Add the chipset microcode file to the CBFS image
cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a0be5d5..cb17d3d 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,3 +14,4 @@
#
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
+cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
new file mode 100644
index 0000000..d323f03
--- /dev/null
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary. This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization. Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM. Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+ /*
+ * eax: BIST value
+ */
+
+ movl %eax, %edi
+
+cache_as_ram:
+ post_code(0x20)
+
+ /*
+ * edi: BIST value
+ */
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_ESRAM_LOC, %eax
+ jbe halt1
+
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ */
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
+ movl %edx, %esi
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ movl %esi, %edx
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
+
+ /* Set up bootloader stack */
+ clrl %eax
+ jmp .Lhlt
+
+halt1:
+ /*
+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+ *
+ * Values are:
+ * 0x01 - FV signature, "_FVH" not present
+ * 0x02 - FFS GUID not present
+ * 0x03 - FSP INFO Header not found
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+ * a different location, or does it need to be?
+ * 0x05 - FSP INFO Header signature "FSPH" not found
+ * 0x06 - FSP Image ID is not the expected ID.
+ */
+ movb $0xBA, %ah
+ jmp .Lhlt
+
+halt2:
+ /*
+ * Failures for postcode 0xBB - failed in the FSP:
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+ */
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+#----------------------------------------------------------------------------
+#
+# Procedure: .Lhlt
+#
+# Input: ah - Upper 8-bits of POST code
+# al - Lower 8-bits of POST code
+#
+# Description:
+# Infinite loop displaying alternating POST code values
+#
+#----------------------------------------------------------------------------
+
+#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
+#define POST_DELAY 0x50
+
+.Lhlt:
+ xchg %al, %ah
+ mov $POST_DELAY, %dh
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+.flash_setup:
+ movl $FLASH_DELAY, %ecx
+.flash_delay:
+ outb %al, $0xED
+ loop .flash_delay
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %dl
+ xorb $1, %dl
+ movb %dl, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+ decb %dh
+ jnz .flash_setup
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+ .long CONFIG_FSP_ESRAM_LOC /* FSP base address */
+
+CAR_init_params:
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index 1b83c13..2a8b0df 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -452,6 +452,22 @@ stackless_PCIConfig_Read:
esram_init_done:
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
+ /* Copy FSP image to eSRAM and call it. */
+ /* TODO: FSP location/size could be got in a routine. */
+ cld
+ movl $(0x00040000), %ecx /* 256K DWORDs = 64K */
+ shrl $2, %ecx
+ movl $CONFIG_FSP_LOC, %esi /* The source address. */
+ movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */
+ rep movsl
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+sd_led:
+ movl %eax, %ecx
+
.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */
.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
@@ -488,6 +504,7 @@ L43:
jmp stackless_PCIConfig_Read
L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
/* Turn on SD LED to indicate ESRAM successfully initialized */
movl $SD_HOST_CTRL, %ebx
movb 0(%ebx), %al
@@ -496,3 +513,7 @@ L44:
/* Loop forever */
jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
+
+ movl %ecx, %eax
+#endif /* CONFIG_ENABLE_DEBUG_LED */
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13618
-gerrit
commit d1fdaabadc4484f9f050ca7e2cd2ec5c61135fc9
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sun Feb 7 22:14:29 2016 +0100
superio/nuvoton/nct5572d: Add PS/2 presence detect
On certain Super I/O devices, when a PS/2 mouse is not present on the
auxiliary channel both channels will cease to function if the
auxiliary channel is probed while the primary channel is active.
Therefore, knowledge of mouse presence must be gathered by coreboot
during early boot, and used to enable or disable the auxiliary PS/2
port before control is passed to the operating system.
This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse
presence detect).
Update the Nuvoton NCT5572D driver to flag the auxiliary channel as
disabled if no device was detected. The code is copied from the Winbond
W83667HG-A driver.
TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this
change, a PS/2 keyboard works fine in Debian GNU/Linux Sid/unstable
with Linux 3.19.
```
[ 1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 1.189970] mousedev: PS/2 mouse device common for all mice
```
Change-Id: I7f9be348d295e70437bef089d4c2173169f38459
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/superio/nuvoton/nct5572d/superio.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c
index 6cafb03..8c80a3e 100644
--- a/src/superio/nuvoton/nct5572d/superio.c
+++ b/src/superio/nuvoton/nct5572d/superio.c
@@ -23,6 +23,7 @@
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
#include <stdlib.h>
+#include <arch/acpi.h>
#include <superio/conf_mode.h>
#include "nct5572d.h"
@@ -38,6 +39,7 @@ static void nct5572d_init(struct device *dev)
{
uint8_t byte;
uint8_t power_status;
+ uint8_t mouse_detected;
if (!dev->enabled)
return;
@@ -45,7 +47,23 @@ static void nct5572d_init(struct device *dev)
switch(dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case NCT5572D_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
+ /* Enable mouse controller */
+ pnp_enter_conf_mode_8787(dev);
+ byte = pnp_read_config(dev, 0x2a);
+ byte &= ~(0x1 << 1);
+ pnp_write_config(dev, 0x2a, byte);
+ pnp_exit_conf_mode_aa(dev);
+
+ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE);
+
+ if (!mouse_detected && !acpi_is_wakeup_s3()) {
+ /* Disable mouse controller */
+ pnp_enter_conf_mode_8787(dev);
+ byte = pnp_read_config(dev, 0x2a);
+ byte |= 0x1 << 1;
+ pnp_write_config(dev, 0x2a, byte);
+ pnp_exit_conf_mode_aa(dev);
+ }
break;
case NCT5572D_ACPI:
/* Set power state after power fail */
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13618
-gerrit
commit 4ddaa5ed0965344c49326533e02a28135aa7a03e
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sun Feb 7 22:14:29 2016 +0100
superio/nuvoton/nct5572d: Add PS/2 presence detect
On certain Super I/O devices, when a PS/2 mouse is not present on the
auxiliary channel both channels will cease to function if the
auxiliary channel is probed while the primary channel is active.
Therefore, knowledge of mouse presence must be gathered by coreboot
during early boot, and used to enable or disable the auxiliary PS/2
port before control is passed to the operating system.
This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse
presence detect).
Update the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.
TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this
change, a PS/2 keyboard works fine in Debian GNU/Linux Sid/unstable
with Linux 3.19.
```
[ 1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 1.189970] mousedev: PS/2 mouse device common for all mice
```
Change-Id: I7f9be348d295e70437bef089d4c2173169f38459
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/superio/nuvoton/nct5572d/superio.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c
index 6cafb03..8c80a3e 100644
--- a/src/superio/nuvoton/nct5572d/superio.c
+++ b/src/superio/nuvoton/nct5572d/superio.c
@@ -23,6 +23,7 @@
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
#include <stdlib.h>
+#include <arch/acpi.h>
#include <superio/conf_mode.h>
#include "nct5572d.h"
@@ -38,6 +39,7 @@ static void nct5572d_init(struct device *dev)
{
uint8_t byte;
uint8_t power_status;
+ uint8_t mouse_detected;
if (!dev->enabled)
return;
@@ -45,7 +47,23 @@ static void nct5572d_init(struct device *dev)
switch(dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case NCT5572D_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
+ /* Enable mouse controller */
+ pnp_enter_conf_mode_8787(dev);
+ byte = pnp_read_config(dev, 0x2a);
+ byte &= ~(0x1 << 1);
+ pnp_write_config(dev, 0x2a, byte);
+ pnp_exit_conf_mode_aa(dev);
+
+ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE);
+
+ if (!mouse_detected && !acpi_is_wakeup_s3()) {
+ /* Disable mouse controller */
+ pnp_enter_conf_mode_8787(dev);
+ byte = pnp_read_config(dev, 0x2a);
+ byte |= 0x1 << 1;
+ pnp_write_config(dev, 0x2a, byte);
+ pnp_exit_conf_mode_aa(dev);
+ }
break;
case NCT5572D_ACPI:
/* Set power state after power fail */
Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13607
-gerrit
commit f13b3510a8f30c0750949ba5fbbc02b7208b0b91
Author: Jean Lucas <jean(a)4ray.co>
Date: Thu Feb 4 19:29:10 2016 -0500
Fix GM45 regression from "northbridge/intel/peg: Disable unused ports"
The `d->link_list' condition in the gm45_init function breaks GM45.
Remove it to restore detection and initialization.
Change-Id: Ic7e116c887b854fd1bce1758a718d963ee0ee5a3
Signed-off-by: Jean Lucas <jean(a)4ray.co>
---
src/northbridge/intel/gm45/northbridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 84df62d..dee6602 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -279,7 +279,7 @@ static void gm45_init(void *const chip_info)
for (; fn >= 0; --fn) {
const struct device *const d =
dev_find_slot(0, PCI_DEVFN(dev, fn));
- if (d && d->enabled && d->link_list && !scan_bus_unused(d->link_list))
+ if (d && d->enabled && !scan_bus_unused(d->link_list))
continue;
const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
pci_write_config32(d0f0, D0F0_DEVEN,
Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796
-gerrit
commit d15cd381cbefaec7a3b3e5121f8f216982f2ebb7
Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
Date: Wed Dec 23 23:27:06 2015 +0100
pcengines/apu1: Supply TPM modules on the LPC connector
Since the APU1 has an LPC connector it is possible to
connect a TPM. I'm using mine mostly for the HWRNG which the
APU1 lacks.
This takes care of setting up the TPM interrupt.
Interrupt 5 was chosen since it is not otherwise used on the APU1,
Alternatively 1, 7, 10-11 and 14-15 should be available as well.
It may also be possible to share the ACPI interrupt (9).
Previously I was getting frequent
"genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)"
errors.
With this I also no longer need to use "tpm_tis.force=1" on
the kernel commandline since the TPM is now declared in the
ACPI DSDT.
See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa
and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o
Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd
Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
---
src/mainboard/pcengines/apu1/Kconfig | 13 +++++++++++++
src/mainboard/pcengines/apu1/devicetree.cb | 5 +++++
src/mainboard/pcengines/apu1/dsdt.asl | 10 ++++++++++
3 files changed, 28 insertions(+)
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 2328776..83a40ba 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
select SPD_CACHE
+ select MAINBOARD_HAS_LPC_TPM if ENABLE_LPC_TPM_SUPPORT
+ select LPC_TPM if ENABLE_LPC_TPM_SUPPORT
+
+config ENABLE_LPC_TPM_SUPPORT
+ def_bool n
+ prompt "Support TPM modules on the APU1 LPC connector"
+ help
+ Enable this option to enable LPC TPM support for the APU1.
+
+ To use a TPM module with the APU1 you must make sure that
+ the third-party module matches the connector pinout.
+
+ If unsure, say N.
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 72e89c0..1a263a2 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -43,6 +43,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
+ chip drivers/pc80/tpm # Support TPM on the LPC header.
+ device pnp 0c31.0 on
+ irq 0x70 = 5
+ end
+ end
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl
index bd9dff2..1b0c0f5 100644
--- a/src/mainboard/pcengines/apu1/dsdt.asl
+++ b/src/mainboard/pcengines/apu1/dsdt.asl
@@ -47,6 +47,16 @@ DefinitionBlock (
}
} /* End Scope(_SB) */
+#ifdef CONFIG_ENABLE_LPC_TPM_SUPPORT
+ /*
+ * LPC Trusted Platform Module
+ */
+ Scope (\_SB.PCI0.LIBR)
+ {
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+ }
+#endif
+
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>