Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13633
-gerrit
commit ffec7ca1ca352be75adb1f8acf98b62df1893319
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 5 11:01:24 2016 +0100
vboot2: Store depthcharge graphic assets only in RO
These files aren't updated (or updatable), and as such don't need to be
copied to the RW sections.
Change-Id: Ie78936792ad651fbf8500fc7e34f0899e33a904c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot2/Makefile.inc | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 34f1f74..61cf71d 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -95,4 +95,8 @@ regions-for-file = $(subst $(spc),$(comma),$(sort \
%/romstage) \
mts \
%/verstage \
+ locales \
+ locale_%.bin \
+ font.bin \
+ vbgfx.bin \
,$(1)),COREBOOT,COREBOOT FW_MAIN_A FW_MAIN_B)))
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13547
-gerrit
commit ab5665514632cd220d22935af4932868ca6ae4ea
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 1 15:26:26 2016 +0100
build system: Build Chrome EC firmware on request
With the Chrome EC's "board" name set in Kconfig, the build system will
build and add the EC firmware, too. Available for the EC and the USB
PD controller.
Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 25 +++++++++++++++++++++++++
src/ec/google/chromeec/Makefile.inc | 27 +++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 2600593..59a9781 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -73,3 +73,28 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP
depends on EC_GOOGLE_CHROMEEC_SPI
hex
default 0
+
+config EC_EXTERNAL_FIRMWARE
+ depends on EC_GOOGLE_CHROMEEC
+ def_bool n
+ help
+ Disable building EC firmware if it's already built externally (and
+ added manually.)
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for EC"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the EC firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
+
+config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC_PD && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for PD"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the PD firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index ad9de9e..9fd024e 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -26,4 +26,31 @@ smm-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
verstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
+CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME))
+CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME))
+
+cbfs-files-$(if $(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME),y) += ecrw
+ecrw-file := $(obj)/ecrw
+ecrw-name := ecrw
+ecrw-type := raw
+ecrw-options := -A sha256
+
+$(obj)/ecrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)/RW/ec.RW.flat $@
+
+$(obj)/pdrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)/RW/ec.RW.flat $@
+
endif
the following patch was just integrated into master:
commit a7ba56e3ce56c8569e2ac5ddb2d2b6c71458d9cb
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 10:42:14 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Test 1 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Test 2 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Remove "select ENABLE_DEBUG_LED_FINDFSP"
* Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13443
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13443 for details.
-gerrit
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443
-gerrit
commit 0411fae79319edc782b705dfb21479069c185258
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 10:42:14 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Test 1 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Test 2 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Remove "select ENABLE_DEBUG_LED_FINDFSP"
* Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 118 +++++++++++++++
src/soc/intel/quark/Makefile.inc | 12 ++
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/cache_as_ram.inc | 206 ++++++++++++++++++++++++++
src/soc/intel/quark/romstage/esram_init.inc | 18 +++
5 files changed, 355 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 1bfab49..802f972 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -29,6 +29,42 @@ config CPU_SPECIFIC_OPTIONS
select USE_MARCH_586
#####
+# Debug support
+# The following options provide debug support for the Quark coreboot
+# code. The SD LED is used as a binary marker to determine if a
+# specific point in the execution flow has been reached.
+#####
+
+config ENABLE_DEBUG_LED
+ bool
+ default n
+ help
+ Enable the use of the SD LED for early debugging before serial output
+ is available. Setting this LED indicates that control has reached the
+ desired check point.
+
+config ENABLE_DEBUG_LED_ESRAM
+ bool "SD LED indicates ESRAM initialized"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+ bool "SD LED indicates fsp.bin file was found"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+ bool "SD LED indicates TempRamInit was successful"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that TempRamInit was successful.
+
+#####
# Flash layout
# Specify the size of the coreboot file system in the read-only
# (recovery) portion of the flash part.
@@ -45,6 +81,88 @@ config CBFS_SIZE
- Intel Trusted Execution Engine firmware
#####
+# FSP binary
+# The following options control the FSP binary file placement in
+# the flash image and ESRAM. This file is required by the Quark
+# SoC code to boot coreboot and its payload.
+#####
+
+config ADD_FSP_RAW_BIN
+ bool "Add the Intel FSP binary to the flash image without relocation"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ default "3rdparty/blobs/soc/intel/quark/fsp.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_RAW_BIN
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+ string "8 byte platform string identifying the FSP platform"
+ default "QUK-FSP0"
+ depends on PLATFORM_USES_FSP1_1
+ help
+ 8 ASCII character byte signature string that will help match the FSP
+ binary to a supported hardware configuration.
+
+config FSP_LOC
+ hex
+ default 0xfff80000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config FSP_ESRAM_LOC
+ hex
+ default 0x80000000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in ESRAM where a copy of the FSP binary is placed.
+
+#####
+# FSP PDAT binary
+# The following options control the FSP platform data binary
+# file placement in the flash image.
+#####
+
+config ADD_FSP_PDAT_FILE
+ bool "Should the PDAT binary be added to the flash image?"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The PDAT file is required for the FSP 1.1 binary
+
+config FSP_PDAT_FILE
+ string
+ default "3rdparty/blobs/soc/intel/quark/pdat.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The path and filename of the Intel Galileo platform-data-patch (PDAT)
+ binary. This binary file is generated by the platform-data-patch.py
+ script released with the Quark BSP and contains the Ethernet address.
+
+config FSP_PDAT_LOC
+ hex
+ default 0xfff10000
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The location in CBFS that the PDAT is located. It must match the
+ PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
+
+#####
# RMU binary
# The following options control the Quark chipset microcode file
# placement in the flash image. This file is required to bring
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 8e24d9b..880f1d4 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -27,6 +27,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include
# Chipset microcode path
CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
+# Add the FSP binary to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := raw
+
+# Add the platform data file to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin
+pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE))
+pdat.bin-position := $(CONFIG_FSP_PDAT_LOC)
+pdat.bin-type := raw
+
# Add the chipset microcode file to the CBFS image
cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a0be5d5..cb17d3d 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,3 +14,4 @@
#
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
+cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
new file mode 100644
index 0000000..d323f03
--- /dev/null
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary. This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization. Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM. Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+ /*
+ * eax: BIST value
+ */
+
+ movl %eax, %edi
+
+cache_as_ram:
+ post_code(0x20)
+
+ /*
+ * edi: BIST value
+ */
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_ESRAM_LOC, %eax
+ jbe halt1
+
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ */
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
+ movl %edx, %esi
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ movl %esi, %edx
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
+
+ /* Set up bootloader stack */
+ clrl %eax
+ jmp .Lhlt
+
+halt1:
+ /*
+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+ *
+ * Values are:
+ * 0x01 - FV signature, "_FVH" not present
+ * 0x02 - FFS GUID not present
+ * 0x03 - FSP INFO Header not found
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+ * a different location, or does it need to be?
+ * 0x05 - FSP INFO Header signature "FSPH" not found
+ * 0x06 - FSP Image ID is not the expected ID.
+ */
+ movb $0xBA, %ah
+ jmp .Lhlt
+
+halt2:
+ /*
+ * Failures for postcode 0xBB - failed in the FSP:
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+ */
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+#----------------------------------------------------------------------------
+#
+# Procedure: .Lhlt
+#
+# Input: ah - Upper 8-bits of POST code
+# al - Lower 8-bits of POST code
+#
+# Description:
+# Infinite loop displaying alternating POST code values
+#
+#----------------------------------------------------------------------------
+
+#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
+#define POST_DELAY 0x50
+
+.Lhlt:
+ xchg %al, %ah
+ mov $POST_DELAY, %dh
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+.flash_setup:
+ movl $FLASH_DELAY, %ecx
+.flash_delay:
+ outb %al, $0xED
+ loop .flash_delay
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %dl
+ xorb $1, %dl
+ movb %dl, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+ decb %dh
+ jnz .flash_setup
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+ .long CONFIG_FSP_ESRAM_LOC /* FSP base address */
+
+CAR_init_params:
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index 1b83c13..b899741 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -452,6 +452,21 @@ stackless_PCIConfig_Read:
esram_init_done:
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
+ /* Copy FSP image to eSRAM and call it. */
+ /* TODO: FSP location/size could be got in a routine. */
+ cld
+ movl $(0x00040000), %ecx /* 256K DWORDs = 64K */
+ shrl $2, %ecx
+ movl $CONFIG_FSP_LOC, %esi /* The source address. */
+ movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */
+ rep movsl
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+sd_led:
+
.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */
.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
@@ -488,6 +503,7 @@ L43:
jmp stackless_PCIConfig_Read
L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
/* Turn on SD LED to indicate ESRAM successfully initialized */
movl $SD_HOST_CTRL, %ebx
movb 0(%ebx), %al
@@ -496,3 +512,5 @@ L44:
/* Loop forever */
jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
+#endif /* CONFIG_ENABLE_DEBUG_LED */
the following patch was just integrated into master:
commit 9fd0895cb4a8cf8d4ece09d62628b6d4b91177ae
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Feb 2 07:17:06 2016 -0800
soc/intel/quark: Enable ESRAM
The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires
that utils/xcompile/xcompile change the machine architecture from i686
to i586 to ensure that the Quark does not attempt to execute unsupported
instructions:
* Adjust Makefile.inc to add the RMU to the coreboot image
* Add code to enable the ESRAM
Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
file from the EDK2 tree (https://github.com/tianocore/edk2.git) to
enable
easy differences and correct issues in coreboot that were found in EDK2.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_RMU_FILE"
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Remove power from the board
* Apply power to the board
* Testing is successful if the SD LED is on indicating that the end of
esram_init.inc was reached
Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13440
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei(a)gmail.com>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/13440 for details.
-gerrit
Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13632
-gerrit
commit abde3effe98a706d9afbf4c91b6a437304a5f4f8
Author: Ben Gardner <gardner.ben(a)gmail.com>
Date: Mon Feb 8 12:18:09 2016 -0600
intel/fsp1_0: Allow the MRC cache to live in a FMAP region
The new option CONFIG_MRC_CACHE_FMAP will cause fastboot_cache.c to
look in the FMAP for a region named "RW_MRC_CACHE" and prevents adding
a CBFS file named "mrc.cache".
Tested on a fsp_baytail-based board.
Change-Id: I248f469c7e3447ac4ec7be32229fbb5584cfd2ed
Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com>
---
src/drivers/intel/fsp1_0/Kconfig | 9 +++++++++
src/drivers/intel/fsp1_0/Makefile.inc | 2 ++
src/drivers/intel/fsp1_0/fastboot_cache.c | 16 ++++++++++++++--
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
index 28df90e..6aa8949 100644
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ b/src/drivers/intel/fsp1_0/Kconfig
@@ -68,10 +68,19 @@ config ENABLE_MRC_CACHE
This can either be used for fast boot, or just because the FSP wants
it to be saved.
+config MRC_CACHE_FMAP
+ bool "Use MRC Cache in FMAP"
+ depends on ENABLE_MRC_CACHE
+ default n
+ help
+ Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
+ You must define a region in your FMAP named "RW_MRC_CACHE".
+
config MRC_CACHE_SIZE
hex "Fast Boot Data Cache Size"
default 0x10000
depends on ENABLE_MRC_CACHE
+ depends on !MRC_CACHE_FMAP
help
This is the amount of space in NV storage that is reserved for the
fast boot data cache storage.
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 2c972b4..ea8f61e 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -31,6 +31,7 @@ fsp.bin-type := fsp
endif
ifeq ($(CONFIG_ENABLE_MRC_CACHE),y)
+ifneq ($(CONFIG_MRC_CACHE_FMAP),y)
$(obj)/mrc.cache:
dd if=/dev/zero count=1 \
bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
@@ -41,4 +42,5 @@ mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
endif
+endif
diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c
index 5c7179e..68150f9 100644
--- a/src/drivers/intel/fsp1_0/fastboot_cache.c
+++ b/src/drivers/intel/fsp1_0/fastboot_cache.c
@@ -19,6 +19,7 @@
#include <bootstate.h>
#include <console/console.h>
#include <cbfs.h>
+#include <fmap.h>
#include <ip_checksum.h>
#include <device/device.h>
#include <cbmem.h>
@@ -55,11 +56,22 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache)
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
size_t region_size;
- *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
+
+ if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) {
+ struct region_device rdev;
+ if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
+ *mrc_region_ptr = rdev_mmap_full(&rdev);
+ return region_device_sz(&rdev);
+ }
+ *mrc_region_ptr = NULL;
+ return 0;
+ } else {
+ *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
CBFS_TYPE_MRC_CACHE,
®ion_size);
- return region_size;
+ return region_size;
+ }
}
/*
the following patch was just integrated into master:
commit cff5f09e9340229cade13960f1c08ede7ec5596f
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 8 08:37:53 2016 -0800
drivers/intel/fsp1_1: Make fsp_run_silicon_init public
Remove the "static" declaration from fsp_run_silicon_init and declare
the routine in ramstage.h. This routine can be called directly when FSP
is already in RAM.
TEST=Build and run on Galileo
Change-Id: Iddb32d00c5d4447eab5c95b0ad5c40309afa293e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13630
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/13630 for details.
-gerrit
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13630
-gerrit
commit 40a6e794bdd38caf44c0ee5953ea3d3786155bcd
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 8 08:37:53 2016 -0800
drivers/intel/fsp1_1: Make fsp_run_silicon_init public
Remove the "static" declaration from fsp_run_silicon_init and declare
the routine in ramstage.h. This routine can be called directly when FSP
is already in RAM.
TEST=Build and run on Galileo
Change-Id: Iddb32d00c5d4447eab5c95b0ad5c40309afa293e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 1 +
src/drivers/intel/fsp1_1/ramstage.c | 8 +++-----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
index 9729a5a..5ce6aa8 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -23,6 +23,7 @@
/* Perform Intel silicon init. */
void intel_silicon_init(void);
+void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
/* Called after the silicon init code has run. */
void soc_after_silicon_init(void);
/* Initialize UPD data before SiliconInit call. */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 20ec323..277b609 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -89,9 +89,8 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
"ERROR - Missing one or more required FSP HOBs!\n");
}
-static void fsp_run_silicon_init(int is_s3_wakeup)
+void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
{
- FSP_INFO_HEADER *fsp_info_header;
FSP_SILICON_INIT fsp_silicon_init;
SILICON_INIT_UPD *original_params;
SILICON_INIT_UPD silicon_init_params;
@@ -99,8 +98,7 @@ static void fsp_run_silicon_init(int is_s3_wakeup)
UPD_DATA_REGION *upd_ptr;
VPD_DATA_REGION *vpd_ptr;
- /* Find the FSP image */
- fsp_info_header = fsp_get_fih();
+ /* Display the FSP header */
if (fsp_info_header == NULL) {
printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
return;
@@ -191,7 +189,7 @@ void intel_silicon_init(void)
/* FSP_INFO_HEADER is set as the program entry. */
fsp_update_fih(prog_entry(&fsp));
- fsp_run_silicon_init(is_s3_wakeup);
+ fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup);
}
/* Initialize the UPD parameters for SiliconInit */