Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447
-gerrit
commit b21bbba7eb7c931488f7c597c1b3386281ca0650
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 14:48:53 2016 -0800
soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_HOBS"
* Add "select DISPLAY_UPD_DATA"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* MemoryInit returns 0 (success) and
* The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/romstage/romstage.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 0951b81..19d0642 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -14,9 +14,12 @@
* GNU General Public License for more details.
*/
+#include <arch/early_variables.h>
+#include <console/console.h>
#include <fsp/car.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
+#include <soc/pm.h>
#include <soc/romstage.h>
void car_soc_pre_console_init(void)
@@ -25,3 +28,14 @@ void car_soc_pre_console_init(void)
set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
UART_BASE_ADDRESS);
}
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+struct chipset_power_state *fill_power_state(void)
+{
+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+ ps->prev_sleep_state = 0;
+ printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
+ return ps;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13631
-gerrit
commit 0931ddcde45bb66900405dd98ceb88e3bbaf3de1
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 8 07:12:30 2016 -0800
soc/intel/quark: Call FSP SiliconInit
Optionally relocate FSP into DRAM and then call FSP SiliconInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_FSP_ENTRY_POINTS"
* Add "select DISPLAY_HOBS"
* Optionally add "select RELOCATE_FSP_INTO_DRAM"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* FSP entry points are displayed and
* The message "FspSiliconInit returned 0x00000000" is displayed and
* The HOBs are displayed correctly and
* The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed
Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 7 +++++++
src/soc/intel/quark/Makefile.inc | 2 ++
src/soc/intel/quark/chip.c | 33 +++++++++++++++++++++++++++++++++
src/soc/intel/quark/chip.h | 31 +++++++++++++++++++++++++++++++
4 files changed, 73 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 08272f0..aab509a 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -174,6 +174,13 @@ config FSP_ESRAM_LOC
help
The location in ESRAM where a copy of the FSP binary is placed.
+config RELOCATE_FSP_INTO_DRAM
+ bool "Relocate FSP into DRAM"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ Relocate the FSP binary into DRAM before the call to SiliconInit.
+
#####
# FSP PDAT binary
# The following options control the FSP platform data binary
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 915360a..e5594be 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -22,10 +22,12 @@ romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+ramstage-y += chip.c
ramstage-y += memmap.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+CPPFLAGS_common += -I$(src)/soc/intel/quark
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
# Chipset microcode path
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
new file mode 100644
index 0000000..f14dde0
--- /dev/null
+++ b/src/soc/intel/quark/chip.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "chip.h"
+#include <console/console.h>
+#include <fsp/ramstage.h>
+
+static void soc_init(void *chip_info)
+{
+ /* Perform silicon specific init. */
+ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
+ intel_silicon_init();
+ else
+ fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+}
+
+struct chip_operations soc_intel_quark_ops = {
+ CHIP_NAME("Intel Quark")
+ .init = &soc_init,
+};
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
new file mode 100644
index 0000000..59c8793
--- /dev/null
+++ b/src/soc/intel/quark/chip.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
+
+#include <stdint.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+struct soc_intel_quark_config {
+ uint32_t junk;
+};
+
+extern struct chip_operations soc_ops;
+
+#endif
the following patch was just integrated into master:
commit 87df8d08d676f79b894da84ebe6f8a57f69ba5b1
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 14:37:13 2016 -0800
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei(a)gmail.com>
See https://review.coreboot.org/13445 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13547
-gerrit
commit 4495c8cc4be63467621bce52260b2453278fcecf
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 1 15:26:26 2016 +0100
build system: Build Chrome EC firmware on request
With the Chrome EC's "board" name set in Kconfig, the build system will
build and add the EC firmware, too. Available for the EC and the USB
PD controller.
Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 25 ++++++++++++++++++++++++
src/ec/google/chromeec/Makefile.inc | 38 +++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 2600593..59a9781 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -73,3 +73,28 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP
depends on EC_GOOGLE_CHROMEEC_SPI
hex
default 0
+
+config EC_EXTERNAL_FIRMWARE
+ depends on EC_GOOGLE_CHROMEEC
+ def_bool n
+ help
+ Disable building EC firmware if it's already built externally (and
+ added manually.)
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for EC"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the EC firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
+
+config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC_PD && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for PD"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the PD firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index ad9de9e..759c0da 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -26,4 +26,42 @@ smm-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
verstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
+# These are Chrome EC firmware images that a payload (such as depthcharge) can
+# use to update the EC. ecrw is the main embedded controller's firmware,
+# pdrw is for a USB PD controller.
+CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME))
+CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME))
+
+cbfs-files-$(if $(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME),y) += ecrw
+ecrw-file := $(obj)/mainboard/$(MAINBOARDDIR)/ecrw
+ecrw-name := ecrw
+ecrw-type := raw
+ecrw-options := -A sha256
+
+cbfs-files-$(if $(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME),y) += pdrw
+pdrw-file := $(obj)/mainboard/$(MAINBOARDDIR)/pdrw
+pdrw-name := pdrw
+pdrw-type := raw
+pdrw-options := -A sha256
+
+$(obj)/mainboard/$(MAINBOARDDIR)/ecrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)/RW/ec.RW.flat $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/pdrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)/RW/ec.RW.flat $@
+
+.PHONY: $(obj)/mainboard/$(MAINBOARDDIR)/ecrw $(obj)/mainboard/$(MAINBOARDDIR)/pdrw
+
endif
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13643
-gerrit
commit b3fe37f8362cd8f70a7163213548a465a54df546
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue Feb 9 14:01:08 2016 +0100
google/chromeos: backup -> back up
See discussion on https://review.coreboot.org/13600 and
https://review.coreboot.org/13601
Change-Id: Ia8274b0b296d6b398f75c0d91a6fded4c5f57e10
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/vendorcode/google/chromeos/Kconfig | 2 +-
src/vendorcode/google/chromeos/vbnv_cmos.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 4a889b1..2a565dc 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -51,7 +51,7 @@ config CHROMEOS_VBNV_CMOS
VBNV is stored in CMOS
config CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
- bool "Backup Vboot non-volatile storage from CMOS to flash."
+ bool "Back up Vboot non-volatile storage from CMOS to flash."
default n
depends on CHROMEOS_VBNV_CMOS
help
diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c
index 22acefa..6dfc74c 100644
--- a/src/vendorcode/google/chromeos/vbnv_cmos.c
+++ b/src/vendorcode/google/chromeos/vbnv_cmos.c
@@ -52,7 +52,7 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy)
}
#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH)
-static void backup_vbnv_cmos(void *unused)
+static void back_up_vbnv_cmos(void *unused)
{
uint8_t vbnv_cmos[VBNV_BLOCK_SIZE];
@@ -62,5 +62,5 @@ static void backup_vbnv_cmos(void *unused)
/* Save to flash, will only be saved if different. */
save_vbnv_flash(vbnv_cmos);
}
-BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, backup_vbnv_cmos, NULL);
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, back_up_vbnv_cmos, NULL);
#endif
the following patch was just integrated into master:
commit 5d7df71cfe6c5a4c8615f33d194cb34947f53c05
Author: david <david_wu(a)quantatw.com>
Date: Fri Jan 8 20:49:48 2016 +0800
google/lars: Set I2C[4] port voltage to 1.8v
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.
TEST=Built & booted lars board. Verified that I2C
port 4 is operating at 1.8V level
Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321000
Original-Commit-Ready: David Wu <david_wu(a)quantatw.com>
Original-Tested-by: David Wu <david_wu(a)quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13627 for details.
-gerrit
the following patch was just integrated into master:
commit 825f937b81dda8cb0f73f27fb2146047d3db0f4e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 26 16:34:23 2016 -0800
skylake mainboards: Enable backing up VBNV from CMOS to flash
Enable the option to back up Vboot non-volatile data from CMOS
to flash as these boards have the necessary nvram fmap region
and are using vboot2 which does not backup to the TPM.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell
Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45
Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324123
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13601
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13601 for details.
-gerrit
the following patch was just integrated into master:
commit fe970134543389634e9e6c78bc91a005b1548628
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 26 16:30:36 2016 -0800
chromeos: Add option to back up VBNV CMOS into flash
This adds a new kconfig option that will back up the VBNV data
from CMOS to flash, and restore it if the CMOS data is invalid
during boot.
This allows special flags to not get lost when power is lost,
RTC reset is triggered, or CMOS is corrupted.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell:
1-boot and run "enable_dev_usb_boot"
2-reboot and check that it is enabled with crossystem
3-run "mosys nvram clear"
4-reboot and check that it is still enabled
Change-Id: I38103d100117da34471734a6dd31eb7058735c12
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 8a356e616c6885d5ae3b776691929675d48a28f9
Original-Change-Id: I06e7ddff7b272e579c704914a0cf8cc14d6994e8
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324122
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13600
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13600 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13600
-gerrit
commit 24fb6c457d23b1d04404be6f8b2afed9e1038b79
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 26 16:30:36 2016 -0800
chromeos: Add option to back up VBNV CMOS into flash
This adds a new kconfig option that will back up the VBNV data
from CMOS to flash, and restore it if the CMOS data is invalid
during boot.
This allows special flags to not get lost when power is lost,
RTC reset is triggered, or CMOS is corrupted.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell:
1-boot and run "enable_dev_usb_boot"
2-reboot and check that it is enabled with crossystem
3-run "mosys nvram clear"
4-reboot and check that it is still enabled
Change-Id: I38103d100117da34471734a6dd31eb7058735c12
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 8a356e616c6885d5ae3b776691929675d48a28f9
Original-Change-Id: I06e7ddff7b272e579c704914a0cf8cc14d6994e8
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324122
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/Kconfig | 8 ++++++++
src/vendorcode/google/chromeos/Makefile.inc | 5 +++++
src/vendorcode/google/chromeos/vbnv_cmos.c | 31 +++++++++++++++++++++++++++++
3 files changed, 44 insertions(+)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 79d6918..4a889b1 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -50,6 +50,14 @@ config CHROMEOS_VBNV_CMOS
help
VBNV is stored in CMOS
+config CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
+ bool "Backup Vboot non-volatile storage from CMOS to flash."
+ default n
+ depends on CHROMEOS_VBNV_CMOS
+ help
+ Vboot non-volatile storage data will be backed up from CMOS to flash
+ and restored from flash if the CMOS is invalid due to power loss.
+
config CHROMEOS_VBNV_EC
bool "Vboot non-volatile storage in EC."
default n
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index ee8b50d..7d62b5b 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -28,6 +28,11 @@ verstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c
romstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c
ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c
+bootblock-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+verstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+romstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+
bootblock-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c
verstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c
romstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c
diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c
index e0d7ba1..22acefa 100644
--- a/src/vendorcode/google/chromeos/vbnv_cmos.c
+++ b/src/vendorcode/google/chromeos/vbnv_cmos.c
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <bootstate.h>
+#include <console/console.h>
#include <types.h>
#include <pc80/mc146818rtc.h>
#include "vbnv.h"
@@ -24,6 +26,21 @@ void read_vbnv_cmos(uint8_t *vbnv_copy)
for (i = 0; i < VBNV_BLOCK_SIZE; i++)
vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i);
+
+ if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH)) {
+ if (verify_vbnv(vbnv_copy))
+ return;
+
+ printk(BIOS_INFO, "VBNV: CMOS invalid, restoring from flash\n");
+ read_vbnv_flash(vbnv_copy);
+
+ if (verify_vbnv(vbnv_copy)) {
+ save_vbnv_cmos(vbnv_copy);
+ printk(BIOS_INFO, "VBNV: Flash backup restored\n");
+ } else {
+ printk(BIOS_INFO, "VBNV: Restore from flash failed\n");
+ }
+ }
}
void save_vbnv_cmos(const uint8_t *vbnv_copy)
@@ -33,3 +50,17 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy)
for (i = 0; i < VBNV_BLOCK_SIZE; i++)
cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i);
}
+
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH)
+static void backup_vbnv_cmos(void *unused)
+{
+ uint8_t vbnv_cmos[VBNV_BLOCK_SIZE];
+
+ /* Read current VBNV from CMOS. */
+ read_vbnv_cmos(vbnv_cmos);
+
+ /* Save to flash, will only be saved if different. */
+ save_vbnv_flash(vbnv_cmos);
+}
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, backup_vbnv_cmos, NULL);
+#endif