Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13633
-gerrit
commit 6c5a2f54bea982a2393b4876e39169fb4c5340ce
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 5 11:01:24 2016 +0100
vboot2: Store depthcharge graphic assets only in RO
These files aren't updated (or updatable), and as such don't need to be
copied to the RW sections.
Change-Id: Ie78936792ad651fbf8500fc7e34f0899e33a904c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot2/Makefile.inc | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 34f1f74..61cf71d 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -95,4 +95,8 @@ regions-for-file = $(subst $(spc),$(comma),$(sort \
%/romstage) \
mts \
%/verstage \
+ locales \
+ locale_%.bin \
+ font.bin \
+ vbgfx.bin \
,$(1)),COREBOOT,COREBOOT FW_MAIN_A FW_MAIN_B)))
the following patch was just integrated into master:
commit 08ec1ae2c2e3be36e08d019719691d30f1106c87
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Tue Jan 26 14:06:26 2016 +1100
mb/intel/d510mo: Explicitly select NIC on PCI in devicetree
While the board configuration still works without this,
It's nicer to have the device statically defined since
the NIC is hardwired to the board.
Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
Reviewed-on: https://review.coreboot.org/13455
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13455 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13645
-gerrit
commit edb77704151cdf54dfe9cbf3303acc116c2e3ef9
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Feb 9 09:06:46 2016 -0700
Kconfig: Move defaults for CBFS_SIZE
We want the question for CBFS size to be next to the rom size in the
mainboard directory, but that doesn't seem to work for how people
want to set the defaults. Instead of having the list of exceptions
to the size, just set the defaults at the end of kconfig.
- Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into
the chipset Kconfigs (gm45, nehalem, sandybridge, x4x)
- Override the default for HAVE_INTEL_FIRMWARE on skylake.
- Move the HAVE_INTEL_FIRMWARE default setting into the firmware
Kconfig file
- Move the location of the default CBFS_SIZE=ROM_SIZE to the end of
the top level kconfig file, while leaving the question where it is.
Test=rebuild Kconfig files before and after the change, verify that
they are how they were intended to be.
Note: the Skylake boards actually changed value, because they were
picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the
0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after
the HAVE_INTEL_FIRMWARE default. Affected boards were:
Google chell, glados, & lars and Intel kunimitsu.
Change-Id: I2963a7a7eab037955558d401f5573533674a664f
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/Kconfig | 18 +++++++++---------
src/northbridge/intel/gm45/Kconfig | 4 ++++
src/northbridge/intel/nehalem/Kconfig | 4 ++++
src/northbridge/intel/sandybridge/Kconfig | 4 ++++
src/northbridge/intel/x4x/Kconfig | 4 ++++
src/soc/intel/skylake/Kconfig | 4 ++++
src/southbridge/intel/common/firmware/Kconfig | 6 ++++++
7 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index feefc91..53c0d75 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -376,17 +376,9 @@ menu "Mainboard"
source "src/mainboard/Kconfig"
+# defaults for CBFS_SIZE are set at the end of the file.
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
- default 0x100000 if HAVE_INTEL_FIRMWARE || \
- NORTHBRIDGE_INTEL_X4X || \
- NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \
- NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \
- NORTHBRIDGE_INTEL_SANDYBRIDGE || \
- NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
- SOC_INTEL_BROADWELL
- default 0x200000 if SOC_INTEL_SKYLAKE
- default ROM_SIZE
help
This is the part of the ROM actually managed by CBFS, located at the
end of the ROM (passed through cbfstool -o) on x86 and at at the start
@@ -1206,3 +1198,11 @@ config MAX_REBOOT_CNT
Internal option that sets the maximum number of bootblock executions allowed
with the normal image enabled before assuming the normal image is defective
and switching to the fallback image.
+
+config CBFS_SIZE
+ hex
+ default ROM_SIZE
+ help
+ This is the part of the ROM actually managed by CBFS. Set it to be
+ equal to the full rom size if that hasn't been overridden by the
+ chipset or mainboard.
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 98ce644..6ee6558 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -27,6 +27,10 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_EDID
select INTEL_GMA_ACPI
+config CBFS_SIZE
+ hex
+ default 0x100000
+
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/gm45/bootblock.c"
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 028921c..3658bd8 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -25,6 +25,10 @@ config NORTHBRIDGE_INTEL_NEHALEM
if NORTHBRIDGE_INTEL_NEHALEM
+config CBFS_SIZE
+ hex
+ default 0x100000
+
config VGA_BIOS_ID
string
default "8086,0046"
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 3e517b1..d2a7cb2 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -45,6 +45,10 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
+config CBFS_SIZE
+ hex
+ default 0x100000
+
config VGA_BIOS_ID
string
default "8086,0106"
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index f643bb2..4ee90a4 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -28,6 +28,10 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_GMA_ACPI
select EARLY_CBMEM_INIT
+config CBFS_SIZE
+ hex
+ default 0x100000
+
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/x4x/bootblock.c"
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 0ebdaa4..c0ce9ad 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -64,6 +64,10 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "soc/intel/skylake/bootblock/pch.c"
+config CBFS_SIZE
+ hex
+ default 0x200000
+
config CPU_ADDR_BITS
int
default 36
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index 62b9a31..c36b235 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -146,4 +146,10 @@ config LOCK_MANAGEMENT_ENGINE
If unsure, say N.
+config CBFS_SIZE
+ hex
+ default 0x100000
+ help
+ Reduce CBFS size to give room to the IFD blobs.
+
endif #INTEL_FIRMWARE
the following patch was just integrated into master:
commit f2ad50fedad9a412c9e9600b79ec2c68c63242e2
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 8 16:19:56 2016 -0800
console: Disable SQUELCH_EARLY_SMP if SMP is not selected
Add a "depends on SMP" to the value SQUELCH_EARLY_SMP Kconfig value to
disable its selection when SMP is not enabled.
TEST=Build for Galileo
Change-Id: Ia3aa1d2169ed793e1bb26538b74b12347453d5af
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13639
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei(a)gmail.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13639 for details.
-gerrit